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TC9464FN
SUMM-DELTA MODULATION DA CONVERTER WITH BUILT-IN 8 TIMES OVERSAMPLING DIGITAL/ANALOG FILTER
TOSHIBA
TC9464FN
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9464FN
E-A MODULATION DA CONVERTER WITH BUILT-IN 8 TIMES
OVERSAMPLING DlGITAL/ANALOG FILTER
The TC9464FN is a second-order E-A modulation 1-bit DA
converter incorporating an 8 times oversampling digital/
analog filter developed for digital audio equipment.
Because the IC includes an analog filter it can output a
direct analog waveform, thus reducing the size and cost
of the DA converter.
FEATURES
It Built-in 8 times oversampling digital filter
0 Built-in digital de-emphasis filter
SSOP24-P-300-0.65A
Weight : 0.149 (Typ.)
0 In serial operating mode, output amplitude can be set in 128 steps of resolution using
microcontroller commands
o In parallel control mode, soft mute output can be set in 64 steps in 20ms
o Built-in LR common zero detection output function
u DAC oversampling ratio (OSR) : 192fs
0 Double-speed operation capable
0 Sampling frequencies: 44.1kHz, 32kHz, 48kHz
o Built-in third-order analog filter
It The digital filter and DA converter characteristics are as shown next page
DIGITAL FILTER (at fs=44.1kHz)
PASSBAND TRANSIENT
DIGITAL FILTER RIPPLE BANDWIDTH ATTENUATION
Standard 8fs i0.11dB 20k--24.1kHz -26dB or less
Operation
Publt-speed 8fs $0.110“; 20k--24.1kHz -2tidB or less
Operation
DA CONVERTER (VDD = 5V)
OSR DISTORTION S/N RATIO
Standard
Operation 192fs - 85dB (Typ.) 96dB (Typ.)
Double-speed
Operation 96fs - 85dB (Typ.) 86dB (Typ.)
2001 -08-1 0
TOSHIBA TC9464FN
PIN ASSIGNMENT BLOCK DIAGRAM
- (SM) (EMP) (BS)
LRCK BCK DATA HS ATT SHIFT LATCH VDX XO XI GNDX MCK
(i2(i2(ii2)(i'2a(D(iir)(D(D(Ds(D(D
Vow U 24am 1 l I I I l s-l
T1 I 2 23 Cl CBK INTERFACE MICROCONTROLLER OSCILLATOR
P/S E 3 22 l D_ATA CIRCUIT INTERFACE CIRCUIT CIRCUIT
VDA E4 21 l HS ,
RD E 5 20 I] ATT(SM) I j
GNDA n 6 19 l SHIFT(EMP) DIGITAL FILTER CIRCUIT TIMING
VR r 7 18 l LATCH(BS) ATTENUATOR CIRCUIT GENERATOR
GNDA E 8 17 CI VDX DE-EMPHASIS FILTER CIRCUIT
LO E9 16 l xo I
VDA n 10 15 u XI
ZD Ell 14E] GNDX 2.4 MODULATOR CIRCUIT
GNDD I 12 13G MCK I
l- ----------------- 1 ------ T
TEST l OUTPUT OUTPUT l
CIRCUIT l": CIRCUIT l: CIRCUIT 'C,-
"--n, I I g
: ANALOG ANALOG I
I FILTER FILTER I
L1JL290JLOt0Lt00J0.0t.0L10JL19L1.2)
PIN DESCRIPTION VDD T1 PE VDA RO GNDA VR GNDA LO VDA ZD GNDD
PIN No. SYMBOL I/O FUNCTION REMARKS
1 VDD - Digital block power pin
2 T1 I Test pin Always set to low.
3 P/T I Parallel/serial mode select pin
4 VDA - Analog power pin
5 RO 0 Right channel analog data output pin
6 GNDA - Analog GND pin
7 VR I Reference voltage input pin
8 GNDA - Analog GND pin
9 LO 0 Left channel analog data output pin
10 VDA - Analog power pin
11 2D 0 Zero data detection output pin common to left and right channels
12 GNDD - Digital GND pin
13 MCK 0 System clock output pin
14 GNDX - Crystal oscillator GND pin
15 XI I Crystal oscillator connecting pins 4%
16 XO 0 Generate the clock required by the system. XI XO
17 VDX - Crystal oscillator power pin
18 LATCH I In serial mode, data latch signal input pin Schmitt
(BS) In parallel mode, de-emphasis filter mode select pin input
19 SHIFT I In serial mode, shift clock input pin Schmitt
(EMP) In parallel mode, de-emphasis filter control pin input
20 ATT I In serial mode, data input pin Schmitt
(SM) In parallel mode, soft mute control pin input
21 FT!; I Standard/doubIe-speed operation control pin
When H : standard operation, when L : double-speed mode
22 DATA I Data input pin
23 BCK I Bit clock input pin
24 LRCK I LR clock input pin
2001 -08-1 0
TOSH I BA TC9464FN
DESCRIPTION OF BLOCK OPERATION
Crystal Oscillator Circuit and Timing Generator
The clock required for the IC's internal operation can be generated by connecting a crystal and
capacitors as in the diagram below. The IC will also operate when a system clock is input from an
external source through XI (pin 15). However in this case, due consideration should be taken of the
fact that waveform characteristics such as jitter and rising/falling characteristics of the system clock
significantly affect the DA converter noise distortion and the S/N.
TO INTE RNAL CIRCUIT
GNDX XI xo VDX MCK
ll 16.9344MH2
E lCL CL--10-33PF
Use a crystal with a low IC value and good startup characteristics.
Fig.1 Crystal Oscillator Circuit
The timing generator generates the clocks or process timing signals required for such functions as
digital filtering and de-emphasis filtering.
. Data Input Circuit
DATA and the LRCK are loaded to the LSI internal shift registers on the BCK signal rising edge.
Accordingly, as shown in the Fig.2 timing example, the DATA and LRCK signals must be input on
the BCK signal falling edge. In addition, DATA is designed so that the 16 bits before the change
point of LRCK are regarded as valid data. Therefore, when BCK is 48fs or Mfs, for example,
effective data must be input before the change point of LRCK.
DATA N5415i14i13ll1zlll1l1ol9.8.7.6.5.4.3.2ILSB'VISBI15I14I13l12l11'10'9|8I7'6I5I4IBIZILSBI
Fig.2a Example of Input Timing Chart
3 2001-08-10
TOSH I BA TC9464FN
When BCK is 48fs or 64fs, input valid data before the change point of LRCK as in the figure below.
BCK THMILIHJflflmEIEIEHEIEHflflfflflflIfflflflflflfl
Fig.2b Example of Input Timing Chart
3. Digital Filter
In both standard and double-speed operation, an 8 times oversampling IIR digital filter eliminates
aliasing noise component outside the bandwidth.
Table 1 Basic Characteristics of Digital Filter (fs=44.1kHz)
PASS BAND TRANSIENT
SET MODE RIPPLE BANDWIDTH ATTENUATION
Standard i0.11dB 20.0le-24.1kHz -26dB or less
Operation
Publt-speed i0.11dB 20.0k--24.1kHz -26dB or less
Operation
Fig.3 shows the digital filter frequency characteristics. (Same as for double-speed operation.)
- 10.00
- 20.00
- 30.00
- 40.00
- 50.00
GAIN (dB)
GAIN (dB)
- 60.00
- 70.00
- 80.00
- 90.00
400.00 441 88.2 132.3 176.4 - . 0 2.0 4.0 6.0 8.01th012_014.016_018J) 20.0220 24.0
FREQUENCY (kHz) FREQUENCY (kHz)
Fig.3 Frequency Characteristics of Digital Filter (fs=44.1kHz)
4 2001-08-10
TOSH I BA TC9464FN
4. De-emphasis Filter
By switching the mode, the digital de-emphasis circuit can be set to three frequencies : 32kHz,
44.1kHz, and 48kHz.
In parallel mode (P/§=H), these frequencies are set by the LATCH (BS) (pin 18) and SHIFT (EMP)
(pin 19) pins. In serial mode (P/§=L), the frequencies are set using microcontroller commands. (For
details for setting in serial mode, see the section on the microcontroller interface function.)
Table 2 Digital De-emphasis Filter Frequency
Coefficient Setting (In Parallel Mode)
LATCH (BS) H H L L
SHIFT (EMP) H L H L
Mode (fs selection) 32 48 44.1 Off (kHz)
The digitalization of the de-emphasis filter eliminates the need for such external components as
resistors, capacitors, and analog switches. In addition, the coefficients are adjusted to reduce error
in the de-emphasis filter characteristics.
The following diagrams show the filter structure and characteristics.
INPUT DATA
IGUw)I
T f f ti H(Z) (birrblZ-1) l/TI “T2
rans er unc Ion : ---
(1-a12-1) T1=50ps,T2=15ps
Fig.4 IIR Digital De-Emphaiss Filter Fig.5 Filter Characteristics
5. DA Conversion Circuit
The TC9464FN incorporates a second-order E-n modulation DA converter for two channels
(simultaneous output type). Fig.6 shows the converter's internal structure.
. Q ( ) OUTPUT DATA
(BITSTREAM l-BIT DA CONVERSION DATA)
Second-order E-d converter : Y(z)--X(z)+(1-z-1)2Q(z)
Fig.6 E-A Modulation DA Converter
5 2001-08-10
TOSH I BA TC9464FN
The clock of the E-A modulation unit is designed to operate at 192fs. Fig.7 shows the noise shaping
characteristics.
NOISE POWER (dB)
0 500k IM
FREQUENCY (Hz)
Fig.7 Noise Shaping Characteristics
6. Data Output Circuit
The output circuit incorporates a third-order analog Iow-pass filter.
This allows the IC to directly obtain analog signals from the IC output pins RC) (pin 5) and LO (pin
PDM SIGNAL -N'''rvvr'"
RO (LO)
Fig.8 Analog Filter Circuit
6 2001-08-10
TOSH I BA TC9464FN
7. Soft Mute Circuit
The TC9464FN incorporates a soft mute function. In parallel mode (P/§=H), switching the SM pin
from low to high performs soft mute on the DA converter output. Fig.9 shows the soft mute on/
off settings and the DA converter output.
Soft mute on/off control is disabled during output level transition.
SM PIN INPUT --l '-.
OFF l ON l OFF
DA CONVERTER I l
OUTPUT LEVEL I I
l AROUND 20ms l l AROUND 20ms l
p—hl F—H
Fig.9 Changes in Soft Mute DA Converter Output Level
8. Zero Data Detection Output Circuit
The TC9464FN incorporates a zero data detection output circuit. If data in both the left and right
channels are zero data for 350ms or longer, the 2D pin (pin 11) changes from low to high.
If the data in both the L and R channels is other than zero data, 2D is fixed to L.
7 2001-08-10
TOSH I BA TC9464FN
Description of Internal Control Signals
The P/T pin can be used to switch between parallel control mode (P/T pin=high in DC setting
mode) and serial control mode (P/T" pin=low in microcontroller setting mode). The following
describes the control functions.
Parallel Control Mode (P/T'' pin=high)
In parallel control mode, pins 18, 19, and 20 are used as the mode setting pins shown in the
table below.
Table 3 Parallel Control Mode
PIN No. PIN NAME PIN DESCRIPTION
18 BS De-emphasis filter mode switching pin
19 EMP De-emphasis control pin
20 SM Soft mute control pin
Serial Control Mode (P/S pin=low : Microcontroller interface function)
In serial control mode, a microcontroller can perform the IC settings. In serial control mode, pins
18, 19, and 20 are used as the attenuator input pins as shown in the table below.
Table 4 Pins in Serial Control Mode
PIN No. PIN NAME PIN DESCRIPTION
18 LATCH Data latch signal input pin
19 SHIFT Shift clock signal input pin
20 ATT Data input pin
The LATCH and ATT signals are loaded to the LSI internal shift register on the SHIFT signal rising
edge. Accordingly, as shown in the Fig.10 timing example, the data input from the ATT pin on
the shift signal rising edge must be valid. The LATCH pulse must rise at least 1.5,us after the
final clock rising edge input from the SHIFT pin. Operating the shift clock with LATCH low
destabilizes the internal states, possibly causing malfunction.
Therefore, set the LATCH signal to low level after loading D7 to the register.
LATCH......,, |_T
sHIFTiiititItitititit
ATT lD0lo1lo2lD3lo4lDslruslD7l
A=AT LEAST 1.5ps B=AT LEAST 1.5ps
Fig.10 Example of Serial Control Mode Data Setting Timing
8 2001-08-10
TOSHIBA
In serial control mode, control is as follows.
TC9464FN
Set all the control bits when the IC power is switched on.
Table 5 Serial Mode Control
SERIAL INPUT DATA CONTROL SIGNAL
D7 0 1
D6 AT6 PBS
D5 AT5 PEMP
D4 AT4 -
D3 AT3 -
D2 AT2 -
D1 AT1 -
D0 ATO -
(1) Digital attenuator
ATO to 6 : Attenuation level setting
PBS : De-emphasis switching
PEMP : De-emphasis on/off switching
D7=low sets digital attenuator control mode. The attenuator can be set in 128 steps. The
following table shows the relationship between the commands and the output.
Table 6 Attenuator Data vs Audio Output
ATTENUATION DATA
D6 VS D0 AUDIO OUTPUT
7F(HEX) OdB
7E (H EX) - 0.069dB
01 (HEX) -42.076dB
00 (HEX) - CK)
The 01 (HEX) to 7E (HEX) attenuation value is calculated by the following formula.
ATT = 20fog (input data / 127) dB
Example : With attenuation data 7A :
ATT = 208og (122 / 127) dB = -0.349dB
D7 = high sets de-emphasis switching mode.
9 2001-08-10
TOSH I BA TC9464FN
(2) Digital de-emphasis filter
The digital de-emphasis filter is controlled by the pEMP and pM signals.
Table 7 Digital De-emphasis Filter Setting
PBS H H L
PEMP H L H L
Mode (fs selection) 32 48 44.1 Off (kHz)
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
VDD -0.3--6.0
Supply Voltage VDA -0.3~6.0 V
VDX -0.3--6.0
Input Voltage Vin -0.r-VDD+0.3 v
Power Dissipation PD 200 mW
Operating Temperature Top, - 35--85 "C
Storage Temperature Tstg - 55--150 ''C
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta = 25°C, VDD = VDX = VDA = 5V)
DC Characteristics
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. MAX. MAX. UNIT
VDD 4.5 5.0 5.5
Operating Supply Voltage VDX - Ta = -35~85°C 4.5 5.0 5.5 V
VDA 4.5 5.0 5.5
Supply Current IDD - Xl=16.9MHz - 12 20 mA
High Level VIH :33 - VDD
Input Voltage - - . VDD V
Low Level VIL 0 - x0.3
High Level IIH
- - - 10 - 10
Input Current Low Level 'IL pzA
10 2001-08-10
TOSHIBA TC9464FN
AC CHARACTERISTICS (Oversampling ratio-- 192fs)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Total harmonic distortion
Noise Distortion THD+N1 1 +nolSe 15Hz sme wave, - -85 -80 dB
full-scale input
VDD = VDX = VDA = 5V
Signal-to-noise Ration S/N 1 88 96 - dB
Dynamic Range DR 1 .1kHz sme wa1/e, -60dB 90 95 - dB
input converSIon
Crosstalk CT 1 .1kHz sme wave, full-scale - -95 -90 dB
1kHz sine wave, full-scale
Analog Output Level Aout1 1 input - 1175 - mVrms
VDD = VDX = VDA = 5V
Operating Frequency fopr - VDD--VDA--VDx2 4.5V 10 16.9344 19.2 MHz
In t Fre enc fLR LRCK duty cycle=50% 30 44.1 100 kHz
pu qu y fBCK - BCK duty cycle-- 50% 0.96 2.1168 4.3 MHz
Rise Time tr . - - 15
Fall Time tf LRCK, BCK pm (10 to 90%) - - 15 ns
Delay Time td - BCK Edge -9 LRCK, DATA - - 40 ns
2001 -O8-1 0
TOSH I BA TC9464FN
It Test circuit 1 : Using application circuit
DATA LOUT 20kHz DlSTORTION
SG BCK APPLICATION CIRCUIT
EXAMPLE FACTOR
LRCK ROUT IDEAL LPF GAUGE
SG : Anritsu MG-22A or equivalent
LPF : Shibasoku 725C built-in filter
Distortion factor gauge : Shibasoku 725C or equivalent
PARAMETER DISTORTION FACTOR GAUGE
MEASURED FILTER SETTING A WEIGHT
THD+N, CT Off A weight
S/N, DR On : IEC-A or equivalent
It AC characteristic point (Input signal setting : LRCK, BCK, DATA)
10% 90% 10% 90%
BCK -y'-N-C
DATA "i"'""' td X X I . I X X X
APPLICATION CIRCUIT
r, 50%
—C MCK GNDD
it c. GNDX ZD D
18 F r‘ 5.0V
'vi, V XI VDA y t d, +
t-v."T" d c,' 8 I 210p + -
18pF t Li": LCxo LO u v 3.3 F L-ch Analog OUT
+ g F. a . ll
s.ol+tias2"ci-; v u. GNDA d "
DX q U 2200pr't
m 2.2.YF
-C) LATCH (BS)
Ch 2200 F
n r''''"h yp
XI U'SHIFT(EMP) U GNDA u l t
EMPH tt f‘ATHSM) RO d . + - R-ch Analo OUT
" V V t..t l 2209 3BpF g
- - F CD
HS -C) HS VDA y, c3 0 +
TC9236AF SINGLE-CHIP 5.OV
PROCESSOR FOR CD - _
AO T —C DATA P/
PLAYER U S c../
BCK -C) BCK T1 Cyt, t
CHCK —C LRCK A VDD Dc-u--, 5.0V
12 2001-08-10
TOSH I BA TC9464FN
PACKAGE DIMENSIONS
SSOP24-P-300-6.65A Unit : mm
RflRRRilRRRRRfl d Tr
ii,i)njii 'file/tii-s-c-i-,-.-,-----,-.-,-'',-
0.325TYP " o.22+0.1
=1 ll" o 0.13
8.3MAX "
= 73:02 =
$1 tiii:.', a“?
tht. " e?
I'-.? l l 0.45Hh2
Weight : 0.149 (Typ.)
13 2001-08-10
TOSH I BA TC9464FN
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
14 2001-08-10
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