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TC9418FN
PLL FOR DIGITAL TUNING SYSTEM (DTS)
TOSHIBA TC9418FN
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TCQAMSIFN
PLL FOR DIGITAL TUNING SYSTEM (DTS)
FEATURES
The TC9418FN is a PLL LSI for digital tuning system (DTS)
incorporating a 2-modulus prescaler.
Each function is controlled through four serial bus lines,
allowing you to configure a high-performance digital
tuning system.
Ideal for configuring a digital tuning system in
headphone stereos and portable radios.
Incorporating a prescaler, the device can operate at VHF : SSOP24-P-300A
50~230MH2 (1 /2+pulse swallow mode) and FM : Weight : 0.31g (Typ.)
50~130MH2 (pulse swallow mode) during FMIN input,
and at HF : 1~20MHz (pulse swallow mode) and LF : 0.5~10MHz (direct divide mode) during AMIN
input.
Comes with a 17bit programmable counter, two parallel output phase comparators, a 75kHz crystal
oscillator, a reference counter, and a 20bit IF counter.
Consisting of a 75kHz crystal resonator (X'tal), the oscillator circuit is powered by a constant-voltage
power supply to generate consistently stable oscillation.
The reference frequency can be selected from seven frequencies available
(fref=1kHz, 3k, 3.125k, 5k, 6.25k, 12.25k, 25k).
Inhibit input (INH) places the device in low-power backup mode (lHDS10pA).
Comes with four lines of I/O ports and four lines of N-channel open-drain outputs
(OFF withstand voltage : 5.5V).
Operates over a voltage range of VDD=1.8--3.6V (Ta-- -10-60oC).
The package is a 24pin SSOP (0.65 pitch).
1 2001-06-19
TOSHIBA TC9418FN
PIN CONNECTION
xlN t 1 24 um
XOUT t 2 23 , DOI
VXT , 3 22 l D02
DOUTE 4 21 UVDD
DIN t 5 20 HAMIN
att s 19 JFiralN
CE I 7 18 EIGND
TEST[ 8 17 ilwcm
o/o-lisa 16 [IOUT-4
1/0-2 , 10 15 Jour-s
UO-? t 11 14 [1our-2
I/o-alj 12 13 Jour-l
BLOCK DIAGRAM
VDD GND
IN Osfilla.tor Reference divider ) MPX
XOUT circuit
V Consta nt-voltage 1kHz )TEST
XT power supply
A PSC Inhibit )INH
FM l J
4bit swallow .
FMIN 1/2 1/15, 1/16 Tri-state
(H VHF counter buffer -(DDo1
HF fr REF
SIG Phase c,
AMINC LF 13bit programmable counter - comparator
Tri-state t"
FIM HF -
1 "rl''" buffer 0002
l 32bit register I
"ei"'"'- Ill
DOUT C ly . OUT-2
. OUT-3
DIN 4 32bit shift register
Serial As
CK interface . OUT-4
' . l/O-l
IF control 12bit register ..
20bit IF counter
2 2001-06-19
TOSHIBA
PIN DESCRIPTION
TC9418FN
PIN NAME
DESCRIPTION
EQUIVALENT CIRCUIT
Crystal Resonator
These pins are used for a crystal resonator.
connect a 75kHz reference crystal
resonator to the XIN and XOUT pins.
Oscillation stops and remains idle when
the W input is low.
Use the XXT pin for a crystal oscillator
power supply. Insert a stabilizing capacitor
(0.47/1F Typ.) between this pin and GND.
Serial Data Output
Serial Data Input
Clock Input
Chip Enable Input
These are serial interface pins.
These pins are used to send and receive
data to set the divide number and divide
mode and control the IF counter and I/O
ports to and from a controller. To allow
the device to be easily interfaced to a
controller operating with a different
supply voltage, the DIN, Ck, and CE input
pins have their input threshold levels set
to 0.3 through 0.8V (0.5V Typ.), and the
DOUT pin is an N-channel open-drain
output.
Data outputs are placed in the high-
impedance state and inputs are turned off
when the W input is held low.
Test Mode Control
This input contains a pull-down resistor,
and can normally be used with GND or
l/O Port
These are 4bit I/O ports. These ports can
be set for input or output in units of one
At power-on, their input/output state and
output state are indeterminate.
The bits set for output are pulled low
when the TiilTif input is low.
2001 -06-1 9
TOSHIBA
TC9418FN
Kl'g‘ 1'fgl- PIN NAME DESCRIPTION EQUIVALENT CIRCUIT
These are 4bit I/O ports. Because these
ports are built with an N-channel open-
drain structure, they can be used for
13 OUT-1 N-Channel Open- control signals operating with different "
, , Drain Output supply voltages.
16 OUT-4 At power-on, their output state is
indeterminate.
The N-channel transistors are turned off
when the W input is low.
This is an IFsignaI input for the IF counter. Rhti2
Its input frequency is 0.35 to 12MHz Wwe
(0.2Vp-p min.). Incorporating an input amp, ngl'
17 IFIN f Signal Input it operates with a C-coupled small C)
amplitude. H%,
This input is pulled down when the W "
input is held low. is
These are power supply input pins.
18 GND Normally input a voltage VDD--1.8--3.6V
(3.0 T p.) to these pins.
Power Supply Input (tl,',,,',','),',, IN-H input is pulled low, the -
21 VDD device is placed in a low current
consumption mode (10PA or less).
This is a VCO (voltage-controlled oscillator)
input during FM and VHF bands.
It operates at 50--130MHz during FM
FM/VHF Band (pulse swallow mode) and 50--230MHz
. during VHF (1 /2+pulse swallow mode).
Local Oscillator . . .
19 FMIN Signal Input Incorporating and input amp, it operates RflNI
with a C-coupled small amplitude (0.2Up-p -
min.).
This input is pulled down when the fNiPi -ui"
input is held low. C)
This is a VCO input during AM band. " H%y
It operates at 0.5~10MH2 during LF (direct h,
AM Band Local divide mode) and l--20MHz during HF
20 AMIN . . (pulse swallow mode). Incorporating an
Oscillator Signal . . .
Input input amp.'. it operates With a C-coupled
small amplitude (0.2Vp-p min.).
This input is pulled down when the INH
input is held low.
2001 -06-1 9
TOSHIBA
TC9418FN
PIN NAME
DESCRIPTION
EQUIVALENT CIRCUIT
Phase Comparator
Output
These are the PLL's phase comparator
outputs.
DOI and D02 are output in parallel.
Therefore, filter constants can be set to an
optimum value in each FM and AM band.
Furthermore, since these pins each can be
driven high and low and placed in the
high-impedance state, Iock-up time
improvements can be easily accomplished.
These outputs are placed in the high-
impedance state when the Wfpf input is
held low.
Inhibit Input
This is an inhibit input.
When this input is driven high, all
functions of the device are enabled.
When this input is driven low, all functions
are disabled, with the device placed in
low-power backup mode (10/1A or less). At
this time, the data transferred to the
device through the serial interface is
retained, so that when the power is
turned back on again, the device can be
operated normally until data is transferred.
2001 -06-1 9
TOSHIBA
DEVICE OPERATION
CD Serial I/O port
TC9418FN
As shown in the block diagram, the TC9418FN has 32bit and 12bit registers providing a total of
44bits to set data for control of each function. Each data in these registers is transferred to and
from the controller through serial ports using the DIN, DOUT, CK, and CE pins. The data serially
transferred in one operation consists of eight address bits and 32 data bits, 40bits in total. However,
the serially transferred data to set the HO and DO pins (input mode 2) consists of eight address
bits and 16 data bits, 24bits in total.
Some of the eight address bits above can be omitted, to a minimum of four bits. In this case, use
these four bits to specify the address. (Clock can also be omitted.)
Thus, all functions can be controlled in units of registers. The following describes mainly the eight
address bits and the functions of each register.
These registers are configured in units of 32bits and 12bits, each selected by an 8bit address. The
next pages shows the address map of each register as "Register Assignments."
REGISTER ADDRESS CONFIGURATION OF 32BITS NU??? OF
Set PLL's divide number. 17
Set PLL's input and mode. 2
Detect lock state. 1
Input Set reference frequency. 3
register ****1000 Start IF counter. 1
Start IF counter gate time. 2
Set wait time. 2
Output data. 4
Total 32bits
I/O control data. 4
Input l/O port output data. 4
. ****0100 Set DO output state. 4
register Unused. 4
Total 16bits
IF counter data. 20
IF counter overflow data. 1
Monitor f counter operation. 1
Output ****1100 PLL unlock enable bit. 1
register PLL unlock data. 1
I/O port input data. 4
Unused 4
Total 32bits
* Don't care ; it can be 0 or 1 or can be omitted.
2001 -06-1 9
TOSHIBA
TC9418FN
REGISTER ASSIGNMENTS (Input)
Ingut mode 1
Address
wlslxlsl1l0lol0
OUT OUT OUT OUT
LPG P1 P2 P3 P4 P5 P6 P7 P8 P9 P10P11P12P13P14P15P16FM HF RESET R0 R1 R2 START GO G1 W0 W1 -1 -2 -3 -4
x Y A A-v-A-x-v-A-v-u
Set divide number. Unlock _ Start Wait time Output port data
detection bit selection -aRefer to 7.
-aRefer to 5.(1).
Set mode. Reference Gate time selection
frequency selection
-aRefer to 3.
u J h. -.A.- _J
programmable counter IF counter IF counter unlock detection
-rRefer to 2.(1). -ritefer to 6.(1). -rRefer to 5.(2).
Ingut mode 2
Address
L, HO HO IIO IIO IIO IIO I/O D01DO1DO2DO2 * * * *
C1 C2 C3 C4 1 2 3 4 M0 M1 M0 M1
u A A A 1
Y Y Y Y
Set l/O pins. IIO port output data. Set DO output. Unused
u J -sRefer to 4.
-rRefer to 7.
(Note) Bits marked with * are Don't care ; they can be 0 or 1.
Outgut mode
Address
HO HO IIO IIO
L, F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 OVER BUSY ENABLE UNLOCK 1 2 3 4 * * * *
u Y A A Y A Y A I
Count data for f counter. Detect IF counter Lock detection bit l/O port Unused
operation. -aRefer to 5.(2). input data
u J -sitefer to 7.
IF counter section
-Mtefer to 6.(2).
(Note) Bits marked with * are indeterminate.
2001 -06-1 9
TOSHIBA TC9418FN
C) Serial transfer format
It Data ingut mode (DOUT is placed in high-impedance state during input.)
', '. Completed
CE i.' I i' -l
10ps min. 20ps min. -c: F-i 10prs min. 10prs min.--:. i--
-e - -'. - ::: .
.. . . =". "r-IO/smite.
CK -L1rL11rLrLrLlr:1rLrLrLrLrLr" ....... --LrLrLrLj-i:.-
'--o :
Can be omitted.
-r1.i- 6pe; min. i...'
N ("X")(")(")(AoXA1)(A2)(A3)(D0XD1)(D2)(o3)(D4l 05- ....... Yd (o28)(D29)(D30)(ry31il "
u JV j :
Can be omitted. Input address
6ps mat-C: .i--
Internal .
data X
0 Data outgut mode
Completed
CE ! - ....... -...l-
ck-u-Lam-u-u-uns.':..:'-)------ ....... --LrLrLrLr:i.-
_---' : : :
Can be om itted.
DIN ccc)ae,e)tieyre,t?ut),tes(s1:ii.:,ii.:. III
Can be omitted Output address ".," i 56/5 max.
. Depends on pull- up resistance value.
:'-i. au- 6/15 max. (Low level) (High level)
Dom (High-impedance) :00 EEEE D5 LIIZDN "iiiiciisissisiit,
(High- -impedan{e)
Shift register preset i-i
(Note) DOUT normally is placed in the high-impedance state.
8 2001-06-19
TOSHIBA TC9418FN
. Connecting crystal resonator
Connect a 75kHz crystal resonator to the device's crystal oscillator pins (XIN, XOUT) as shown below.
This oscillation signal is fed to the clock generator and reference frequency divider to generate the
reference frequency for device operation. Furthermore, this crystal oscillator circuit is operated with
the voltage VXT= 1.4V Typ.) supplied by an internal constant-voltage circuit. This configuration helps
to stabilize crystal oscillation and reduce the current consumption.
XIN XOUT VXT
CL CL CX I X'tal=75kHz
' CL=15pF Typ., Cx=0.47/1F Typ.
. Programmable counter
The programmable counter block consists of a 1/2 prescaler, 2-modulus prescaler, and 4bit+ 13bit
programmable binary counters.
(1) Setting up the programmable counter block
Use 17bits for the divide number and two bits for the divide mode.
C) Setting the divide mode
Use the FM and HF bits to choose the input pins and the divide mode (pulse swallow or
direct divide mode). There are four combinations of these bits as shown below. Choose
your desired setting depending on the frequency bands used.
TYP. INPUT INPUT DIVIDE
MODE FM HF DIVIDE MODE RECEIVE FREQUENCY PIN NUM-
BAND RANGE BER
LF 0 0 Direct divide mode LWNW 0.5~10MH2 AMIN n
HF 0 1 Pulse swallow mode SW 1--20MHz AMIN n
FM 1 0 Pulse swallow mode FM 50~130MH2 FMIN n
VHF 1 1 1/2+pulse swallow mode VHF 50~230MHZ FMIN 2.n
(Note) 'n' denotes a divide number.
9 2001-06-19
TOSHIBA
© Setting divide number
TC9418FN
Set the programmable counter's divide number in binary by using the P0 to P16 bits.
It Pulse swallow mode (17bits ; HF, FM, and VHF bands)
MSB LSB
IP16IP15IP14IP13IP12IP11IP10I P9 I P8 I P7 I P6IP5 I P4IP3 I P2 I PI I POI
216 20
The range of divide numbers that can be set (pulse swallow mode) n =210H to
1FFFFH (528--131071)
(Note) For the 1/2 +pulse swallow mode, the actual divide number is twice the
programmed number.
0 Direct divide mode (13bits)
P16IP‘ISIP14IP13IP12IP11IP10I P9 I P8 I P7 I P6 I P5 I P4 EP3%P2%P1%P04
20 ( Irrelevant]
The range of divide numbers that can be set (direct divide mode) n=10H--1FFFH
(16--8191)
(Note) In direct divide mode, the data in P0--P3 does not have any effect, with P4
being the LSB.
(2) Circuit configuration of prescaler and programmable counter
C) Circuit configuration in pulse swallow mode
PSC PO-P?
Swallow counter, 4bits
2-modulus Preset
prescaler
Programmable counter,
13bits
P4--P16
Phase comparator
This circuit is configured with a 2-modulus prescaler, 4bit swallow counter, and 13bit
programmable counter.
During VHF, a 1/2 prescaler is added in the preceding stage.
2001 -06-1 9
TOSHIBA TC9418FN
© Circuit configuration in direct divide mode
preset
AMIN "f' Prerangsilt: counter, Phase comparator
In direct divide mode, the prescaler is bypassed, and only the 13bit programmable counter
is used.
(3) The FM-IN and AM-IN inputs each contain an amp, so they can operate with a capacitor-
coupled, small amplitude.
3. Reference frequency divider
This divider can generate 7 kinds of reference frequencies by dividing the oscillation frequency of
an external 75kHz crystal resonator.
(1) Setting reference frequency
Use the R0--R2 bits for this setting.
R2 RI RO JiFlr/itfiii,
0 0 0 1kHz
0 0 1 3kHz
0 1 0 3.125kHz
0 1 1 5kHz
1 0 0 6.25kHz
1 0 1 12.5kHz
1 1 0 25kHz
1 1 1 Inhibited
11 2001-06-19
TOSHIBA TC9418FN
4. Phase comparator
The phase comparator compares phases between the reference frequency signal supplied by the
reference frequency divider and the programmable counter's divide-by-n output signal and outputs
the difference. In this way, it controls the VCO via a Iow-pass filter so that the frequencies and
phases of these two signals are matched.
Since this phase comparator has two tri-state buffer DOI and D02 pins output in parallel, filter
constants can be set to an optimum value in each FM, VHF, and AM band.
These outputs also can be used for general-purpose output as set by the DO control bits. Moreover,
the DOI and D02 pins can be placed in the high-impedance state. Thus, using the DOI and D02
pins, it is possible to improve the PLL loop's Iock-up time and other characteristics.
(1) DO control bits
DO CONTROL BITS
M0 M1 DO OUTPUTSTATE
D 1 D 1 D 2 D 2
O O O O 0 0 Phase comparator output
M0 M1 M0 M1 3 1 0 Output driven low
0 1 Output driven high
1 1 Output in high impedance
D02 £5
DOI "iii] Drc en
When setting time constant in each band When using LPF in common
(filter constants switched over by placing
DO in high-impedance state)
VCC (3V)
converter
k 0.01PF
To VCO's varicap -'W--oe.
. IPF 4.7kQ
2SC41 16GR
Example of active-low bus filter (reference)
DOI, D02
2SK209Y
(Note) The filter circuits shown above are merely examples for your reference. The actual
circuit must be designed after considering your system's band configuration and
required characteristics.
12 2001-06-19
TOSHIBA TC9418FN
5. Unlock detection bit
This bit is used to detect the PLL's lock condition. Specifically, this is accomplished by using the
UNLOCK bit. It detects the phase difference between the reference frequency and the
programmable counter's divide-by-n output in periods of the reference frequency.
(1) Unlock detection bit
Unlock detect operation detects the phase difference between the reference frequency and
the programmable counter's divide-by-n output at falling edges of the reference frequency
signal. If the phases are found unmatched, that is, not locked in phase, the UNLOCK F/F is
set (UNLOCK bit=1).
The UNLOCK F/F is reset each time the RESET bit is set to 1.
Since the divide number setup and RESET bit are sent in the same data, a wait time is
provided. Any desired wait time can be selected by wait time bits. Unlock detect operation is
begun a wait time after the data is transferred.
Therefore, make sure that the wait time is set in relation to the Iock-up time.
Furthermore, since the phase difference is detected in periods of the reference frequency, the
UNLOCK bit must be waited for a duration of (period of reference frequency) +(wait time)
after the UNLOCK F/F is reset before the bit can be accessed. For this purpose, an ENABLE
bit is provided. Check to see that the ENABLE bit=1 before you access the UNLOCK bit.
This ENABLE bit is reset each time the RESET bit is set to 1, as is the UNLOCK F/F. When the
ENABLE bit= 1, you are assured that the lock condition is detected correctly.
UNLOCK DETECTION TIMING
Data transfer completed (data with a wait time) Data transfer completed (data without a wait time)
5 UNLOCK F/F reset :
. Phase difference 5 Phase difference
detected 5 detected
UNLOCK bit 5 I High or Low I
I i i : i
. . _ E Period : 3 Period :
Wait time i of ref- i g of ref- 3
: erence 5 .' erence 5
: E freq-
ENABLE bit I 5 uency "1" I uency I "1"
Since unlock detection starts with
this timing, check that the ENABLE
bit=1 before accessing the
UNLOCK bit to see the phase
difference.
13 2001-06-19
TOSHIBA TC9418FN
(2) Lock detection bit and wait time bits
0 Lock detection bit
ENABLE UNLOCK STATE
0 Invalid data -
1 0 Lock
1 Unlock
0 Wait time bits
W1 W0 UNLOCK IF COUNTER
None O~1ms
1--2ms 1.33--2.33ms
3~4ms 3.33--4.33ms
7-8ms 7.33--8.33ms
—r—-oo
—‘o—‘O
(Note) These bits are used in common to set a wait time for the IF counter
and unlock detection. Therefore, in cases when they are set to any
combination other than W1 =W0=0, if either function is restarted
during a wait time for the IF counter or unlock detection, the wait
time for the function restarted now has priority and the function in a
wait time is postponed. Then each function starts after the wait time
for the function restarted elapses.
Set to a wait time of 3~4ms for unlock detection.
Data I i i
i. Data transfer completed.
—|._Wait time of 3~4ms -ir'e,tu1'yc; I
Unlock detection starts.
Set to a wait time of 3.33-4.33ms for IF counter.
New data transfer completig during wait timewmed‘
. Reference fre uenc .
3 Wait time of q y
L 3.33--4.33ms
IF count starts. Unlock detection starts.
14 2001-06-19
TOSHIBA TC9418FN
IF counter
This is a 20bit general-purpose IF counter that can be used, for example, to detect an auto stop
signal by counting the intermediate frequency (IF) of FM or AM during auto tuning.
Measurement with a general-purpose IF counter is accomplished by setting a gate time according to
the IF input's frequency band and then setting the START bit to 1 to start the IF counter.
In this case, since the PLL's divide number data and the START bit are in the same data, a wait
time is provided. To set this wait time, the same W1 and W0 bits are used that are used to set a
wait time for unlock detection.
Thus, a wait time after data transfer is completed, clock is input from the IF pin to the 20bit binary
counter at the gate time you have set, and and the counter counts the number of clock pulses
input until count expires. You can reference the BUSY bit to determine when the IF counter has
finished counting.
Next that the OVER bit is set to 1 when the count value exceeds 220 pulses that have been input.
The frequency fed to the IF input pin can be measures by taking in the IF data from F0~F19 when
both BUSY and OVER bits=0.
(1) General-purpose counter control bits
CO GO, G1 bits ......... Bits to choose a gate time
G1 GO GATE TIME
1 64ms
—:o—‘o
© START bit .......... Each time the START bit is set to 1, measurement is started after
resetting the general-purpose IF counter.
(2) General-purpose counter output bits
(D General-purpose counter data output bits (F0~F19)
The result of counts counted by the general-purpose counter can be read out in binary
from the output register bits Fo~F19.
IFO I F1 IFZ I F3 I F4 I F5 I F6 I F7 I F8IF9 IF‘IOIF1‘IIF12IF13IF14IF‘ISIF16IF17IF18IF19I
20 219
L58 IF counter data MSB
15 2001-06-19
TOSHIBA TC9418FN
© General-purpose counter operation detect bits
BUSY OVER
' 0 .' IF counter's count-ap-l
Overflow detection
1 : IF counter's count> 220 (overflow)
:ch nt hasfinish c ntina.
-0peration monitor 0 ou er a H ed ou Ing
1 .' IF counter is counting.
(3) Circuit configuration of IF counter
IFIN 20bit binary counter l-l OVER l
Gate time control circuit HI BUSY I
Wait signal START GO G1
The IF counter block consists of an input amp, gate time control circuit, and a 20bit binary
counter.
(Note) The IFIN pin contains an amp, and can operate with a capacitor-coupled small
amplitude.
Data is set to START bit
BUSY bit l-
(1kHz)
; : E H»: :
Gate I I l 0.66ms 0.33ms
--.' 2
Wait time
Binary counter input lllllllllllllllllllllllll
16 2001-06-19
TOSHIBA
7. General-purpose I/O ports
Input mode
Output mode
I/O port input/output setup bits
|/OC1~4{
TC9418FN
/ The device has general-purpose I/O ports controlled by a serial interface.
0 : l/OI thru 4 are set for input
1 : I/O1 thru 4 are set for output
I/O port output setup bits (when I/O ports are set for input)
I/ov4 (
OUT port output setup bits
OUT1~4
I/O port input data read bits
I/OI-M (
0 : I/O1 thru 4 output are driven low
1 : I/O1 thru 4 output are driven high
0 : OUT1 thru 4 outputs are pulled low (N-channel
open-drain ON).
1 : OUT1 thru 4 outputs are placed in the high-
impedance state (N-channel open-drain OFF).
0 : Input level is low
1 : Input level is high
17 2001-06-19
TOSHIBA TC9418FN
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage VDD -0.3--4.0 V
Input Voltage 1 VIN1 -0.r-VDD+0.3 V
Input Voltage 2 VIN:? -0.3--6.0(Note 1) V
N-channel Open-Drain Output
Tolerance VOUT -0.3 6.0 V
Power Dissipation PD 400 mW
Operating Temperature Top, -10~60 °C
Storage Temperature Tstg - 55--125 "C
(Note 1) DIN, CK, and CE pins
ELECTRICAL CHARACTERISTICS (Unless otherwise specified Ta =25°C, VDD=3V)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Operating Supply *
V - 1.8 3.0 3.6
Voltage DD ( )
Data Retention Voltage VHD - INH ="L" 0.8 -- 3.6
Operating Supply INH ="H", FMIN =230MHz,
Current IDD output non-Ioaded 9 15 mA
Data Retention Current IHD - INH ="L" - 0.1 10 pA
CRYSTAL OSCILLATOR (XIN, XOUT, l/XT)
fts,elnoc'yxi"ation fXT - (*) - 75 - kHz
girrfécal Oscillation Start tST - (7::_:;Rc5r;s:|_ Lisggstor - 0.3 0.6 S
$223331: Feedback RfXT - Between XIN and XOUT pins - 15 - Mn
2osy,Jaecuet''ut ROUT - XOUT pin - 4 - k0
szmgsllfge VXT - - 1.4 - v
(*) Guaranteed at VDD=1.8~3.6V and Ta= -10-600C
18 2001-06-19
TOSHIBA TC9418FN
PROGRAMMABLE COUNTER, IF COUNTER, OPERATING FREQUENCY RANGE (FMIN, AMIN, IFIN)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
fVHF - .Sine wave input during VIN = Om/p-p 50 _ 230
input 1/2+ pulse swallow mode (*)
FMIN Si . t d ' v 0 2V MHz
me wave In unn = . -
fFM - . pu g IN p p 50 _ 130
input pulse swallow mode (*)
fHF - Sine wave input during VIN = 0.2Vp_p 1 _ 20
input pulse swallow mode (*)
AMIN . . . MHz
f Sine wave Input during VIN = Om/p-p 0 5 10
LF input direct divide mode (*) .
Sine a e in t d rin V =0.2V -
TIN f”: - y W .V I p,”, url g IN p-p 0.35 _ 12 MHz
input direct divide mode (*)
. . * VDD
Input Amplitude Range VIN - FMIN, AM|N, and IFIN pins ( , 0.2 -- 0 5 Vp-p
AM FM I F k .
.IN' IN nput eedbac Rf1 - FMIN, and AMIN pms 150 300 600 k9.
Resistance
IF I t F db k
IN. npu ee ac Rf2 - IFIN pin 500 1000 2000 k0,
Resistance
SERIAL INTERFACE (DOUT, DIN, CK, CE)
Input Leakage Current In - VIH=5.5V, VIL=0V, DIN, CK, CE pins - - i1.0 pA
Input High Level VIH - DIN, CK, and CE pins 0.8 _ 5.5 V
Voltage Low Level VIL - DIN, CK, and CE pins 0 _ 0.3
Low Level Output Current IOL1 - VOL=0.3V, DOUT pin 0.7 1.4 - mA
FF L k
Output C) ea age IOFF - VIH=5.5V, DOUT pin - - 1.0 pA
Current
OUTPUT PORTS (OUT-1~OUT-4)
Low Level Output Current IOL! - VOL=0.3V 0.7 1.4 - mA
FF L k
Output 0 ea age IOFF - VIH = 5.5V - - 1.0 pA
Current
I/O PORTS (I/O-1 to I/O-4)
Input Leakage Current ILI - VIH=3.0V, VIL=0V - - $1.0 pA
Input High Level VIH - 2.4 -- 3.0 V
Voltage Low Level " - 0 _ 0.6
Output High Level IOH - VOH = 2.7V - 0.4 - 0.8 - A
Current Low Level IOL - VOL=0.3V 0.4 0.8 -
(*) Guaranteed at VDD=1.8-3.6V and Ta-- -10-6trc
19 2001-06-19
TOSHIBA TC9418FN
DO OUTPUT (D01, D02)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX UNIT
Output OFF Leakage
I - V =3.0V, V =0V - - Al.0
Current TL TLH TLL PA
Output High Level IOH - VOH=2.7V -0.4 -0.8 - A
Current Low Level IOL - V0L=0.3V 0.4 0.8 - m
TEST AND WI PINS
mp?” Pull-Down R. - TEST pin 25 50 100 kft
Resistance
Input High Level VIH - W pin 2.4 '.'- 3.0 V
Voltage Low Level V”: - W pin 0 -- 0.6
20 2001-06-19
TOSHIBA TC9418FN
PACKAGE DIMENSIONS
SSOP24-P-300A Unit : mm
24 13 -
RflRflRflRRRfWI d Ti
ll N Q
fi?, $1
ttlt a?
iHHHi 'iieelfe1lij.,.......,.,.,..e..,,'......,...,..,e,e..,
1 l 12
0.325TYP 'ir 0.22i0.1 C 0.13
" 8.3MAX =
- 7.8i0.2 =
Ch.1 x m
er < "-C2.
'iaggggggggggi: "cti" 3.1 2::
”‘1: *- T-
tii' I l th45kth2
Weight : 0.31g (Typ.)
21 2001-06-19
TOSHIBA TC9418FN
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
22 2001-06-19
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