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TC9322FB
SINGLE CHIP DTS MICROCONTROLLER (DTS-21)
TOSHIBA
TC9322FA/FB
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9322FA, TC9322FB
SINGLE CHIP DTS MICROCONTROLLER (DTS-21)
The TC9322FA and TC9322FB are a 4bit CMOS
microcontroller for signal chip digital tuning systems. It is
capable of functioning at a low voltage of 3V and
features a built-in prescaler of operating 230MHz, PLL
and LCD drivers.
The CPU has 4bit parallel addition and subtraction
instructions (e.g., AI, SI), logic operation instructions (e.g.,
OR, AND), composite judging and compare instructions
(e.g., TM, SL), and time-base functions.
The package is an pin 64, 0.5/0.65-mm-pitch quad flat
pack package. In addition to various input/output ports
and a dedicated key-input port, which are controlled by
powerful input/output instructions (IN 1, 2, OUT 1, 2),
there are many dedicated LCD pins, a buzzer port, a 6bit
A/D converter, an IF counter, and other pins.
Low-voltage and Iow-current consumption make this
microcontroller suitable for portable DTS equipment.
FEATURES
0 O O O O O
4bit microcontroller for digital tuning systems.
Operating voltage VDD=1.8--3.6V, with low current
consumption because of CMOS circuitry (with only CPU
operating, when VDD=3V, bD--80pA Max.)
Built-in prescaler (1/2 fixed divider +2 modulus prescaler
TC9322FA
LQFP64-P-1010-0.50
TC9322FB
QFP64-P-1212-0.65
Weight
LQFP64-P-1010-0.50 : 0.32g (Typ.)
QFP64-P-1212-O.65 : 0.459 (Typ-)
: fmax2 230MHz)
Features built-in 1/3-duty, 1/2-bias LCD drivers and a built-in 3V booster circuit for the display.
Data memory (RAM) and ports are easily backed up.
Program memory (ROM): 16bitx3072 steps
Data memory (RAM) : 4bitx192 words
62-instruction set (all one-word instructions)
2001 -06-1 9
TOSHIBA TC9322FA/FB
It Instruction execution time : 40ps (with 75kHz crystal) (MVGS, DAL instructions : 80ps)
0 Many addition and subtraction instructions (12 types addition, 12 types subtraction)
0 Powerful composite judging instructions (TMTR, TMFR, TMT, TMF, TMTN, TMFN)
0 Data can be transmitted between addresses on the same row. (MVSR instruction)
0 Register indirect transfer available (MVGD, MVGS instruction).
It 16 powerful general registers (located in RAM)
It Stack levels : 2
o JUMP or CAL instruction can be used anywhere in the 3072 steps of program memory (ROM) as
there are no pages or fields.
0 16bit of any address in the 1024 steps in program memory (ROM) can be referenced (DAL
instruction).
lt Features independent frequency input pins (FMIN and AMIN) and two (DOI and D02) phase
comparison outputs for FM/VHF and AM.
0 Seven reference frequencies can be selected by program.
0 Powerful input/output instructions (IN 1, 2, OUT 1, 2)
It Dedicated input ports (Kir-k3) for key input. 26 LCD drive pins (69 segments maximum) available.
0 17 I/O ports : 10 with input/output programmable in 1bit units, and 7 output-only port. The 2
IFIN, and DO1 pins can be switched by instruction to IN (input-only) or OT (output-only).
0 Three back-up modes available by instruction : only CPU operation, crystal oscillation only, clock
9 Features a built-in 2Hz timer HF and a built-in 10/100Hz interval pulse output (internal port for
time base).
It Allows PLL lock status detection.
0 8 of the LCD segment outputs (S15~523) can also operate as key return timing outputs (KRO-KR7).
The l/O ports are not dedicated key return timing outputs but can have other uses as well.
0 Built-in 20bit, general-purpose IF counter can detect stations during auto-tuning by counting the
intermediate frequencies of each band.
0 Built-in 8bit buzzer output circuit can produce 254 different tone signals.
0 Features a built-in 2-channel, 6bit A/D converter.
0 To prevent CPU malfunctions, a built-in supply voltage drop detection circuit shuts down the CPU
when voltage falls below 1.5V.
2 2001-06-19
TOSHIBA TC9322FA/FB
PIN CONNECTION
Output A/D Converter
| P3-1(BUZR)—
| P2-3(DC—REF)
I P2-2(AD|N2)
I P2—1(AD|N1)
b-,L-"
| P3-O
| P2-0
| P1-3
| P1-2
| P‘I-1
| P1—0
Radio ON/OFF o-- HOLD I/O Port Key Return T1
Timing
IF Signal -H-lFIN/lhl Output Port= T0
Phase - DO1/OT K3
Comparison
Output -- DO2 Keylnput K2
_- GND K1
Local ---o- FMIN K0
Oscillator
Signal _ AMIN $23/KR0
Battery 0*: VDD (TOP VIEW) S22/KR1
75kH RESET $21/KR2
Z Key Return
"gi-'' OUT Timing S20/KR3
it-u-ear- NN Output Port S19/KR4
it-n- VXT S13/KR5
Q-o- VLCD S17/KR6
C1 S15/KR7
l'_ C2 515
ir-o- VEE LCD Driver (3x23=69max. SEGMENT) S14
iii'g?lrJrJ'?cfiy?l/'/2/g'tg'fj-'i--.C).t-'
VT V3 V3 Mt
3 2001-06-19
TOSHIBA
BLOCK DIAGRAM
IFIN/IN
2 10Hz
CPU Timing Gene. 2Hz F/F
Reference Divider MPX / La.
1kHz PLL OFF
4bit Swallow
1/15, 16 Counter/La.
20bit IF Counter
DATA BUS
CODE BUS
COLUMN
(16x 3072 Step)
Instruction
Prog. Counter
Stack Reg. (2 Level)
VL VEE
500H COM
500HZ KEY SCAN
TIMING GENE.
Segment Driver/La. EY Data La
S15/KR
S17/KR
S1g/KR5
$23/KR
UNLOCK F/F
Phase Com.
SIG OT
12bit Programmable
Counter/La.
(4 x 192 word)
R/W Buf
TC9322FA/FB
DOI /OT
La. MUTE
MUTE Cont.
Shit BUZR
P3-1 /BUZR
P2-3/DC-REF
P2-2/ADIN2
P2-1 /AD|N1
6bit A/D
STOP RES Wr-
STOP Power
F/F ON
RESET VDD
Doubler
Circuit
LLI PMs-
LIJ UU
2001 -06-1 9
TOSHIBA
TC9322FA/FB
EXPLANATION OF FUNCTION
PIN No.
SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
LCD common
output
Output common signals to the LCD
panel. Through a matrix with pins
Sr-sp, a maximum of 69 segments can
be displayed.
Three levels, l/LCD, VEE, and GND, are
output at 83Hz every 2ms.
VEE is output after SYSTEM RESET and
CLOCK STOP are released, and a common
signal is output after the DISP OFF bit is
set to "o".
sr-SIS
LCD segment
output
S15/KR7
$23 / KRO
LCD segment
output/ Key
return timing
output
Segment signal output pins for the LCD
panel. Together with COM1, COM2, and
COM3, a matrix is formed that can
display a maximum of 69 segments.
The signals for the key matrix and the
segment signals from pins S15/KR7~523/
KRO are output on a time division basis.
4x8=32 key matrix can be created in
conjunction with key input ports K0--K3.
Key input ports
4bit input ports for key matrix input.
Combined in a matrix with key return
timing outputs of the LCD segment pins,
data from a maximum of 4x8=32 keys
can be input and pins are pulled up. On
the key seteutining output pins, data
from 4x6=24 keys can be input and
pins are pulled down. The WAIT mode is
released when high level is applied to
key input ports set to pull-down.
Ttr-Ts
Key return
timing output
These ports output the timing signal for
key matrix. To form the key matrix, load
resistance has been built-in the N-channel
side. When the key matrix combined
with push-key, that does not need a key
matrix diode.
I/O port1
The input and output of these 4bit I/O
ports can be programmed in 1bit units.
By altering the input to I/O ports set to
input, the CLOCK STOP and WAIT modes
can be released, and the MUTE bit of
the MUTE pin can be set to "I''.
''-] i
2001 -06-1 9
TOSHIBA
TC9322FA/FB
PIN No. SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
P2-1 /
41 ~44 P2-2/
DC-REF
I/O port2
/AD analog
voltage input
/AD analog
voltage input
/Reference
voltage input
4bit I/O ports.
Input and output may be programmed in
1bit units.
Pins P2-1 through P2-2 can also be used
for analog input to the built-in 6bit, 2-
channel A/D converter.
Conversion time of the built-in A/D
converter using the successive comparison
method is 280ps. The necessary pin can
be programmed to AD analog input in
1bit units, and P2-3 can be set to the
reference voltage input. Internal power
supply (VDD) or constant voltage (VEE)
can be used as the reference voltage. In
addition, constant voltage (VEE) can be
input to the AD analog input so battery
voltage, etc., can be easily detected. The
reference voltage input, for which a
built-in operational amp is used, has high
impedance.
The A/D converter, and their control are
all executed by program.
- To A/D converter
(P2-0 pin is excluded)
45--46 P3-1 /
l/O port3
/Buzzer output
2bit l/O ports, whose input/output can
be programmed in 1bit units.
The P3-1 pin also functions as the output
for the built-in buzzer circuit. The buzzer
sound can be output in 254 different
tones between 18.75kHz and 147Hz, and
at a duty of 50%.
The buzzer output, and all associated
controls can be programmed.
47 MUTE
Mutiny output
1bit output port. Normally, this port is
used for muting control signal output.
This pin can set the internal MUTE bit to
"I" according to a change in the input
of I/O port 1. MUTE bit output logic can
be changed ; PLL phase difference can
also be output using this pin.
48 TEST
TEST mode
control input
Input pin used for controlling TEST
mode. High level indicates TEST mode,
while low level indicates normal
operation. The pin is normally used at
low level or no-connection (NC). (A pull-
down resistor is built-in).
2001 -06-1 9
TOSHIBA
TC9322FA/FB
PIN No.
SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
HOLD mode
control input
Input pin for request/release HOLD
Normally, this pin is used to input radio
mode selection signals or battery
detection signals.
HOLD mode includes CLOCK STOP mode
(stops crystal oscillation) and WAIT mode
(halts CPU). Setting is implemented with
the CKSTP instruction or the WAIT
instruction. When the CKSTP instruction is
executed, request/release of the HOLD
mode depends on the internal MODE bit.
If the MODE bit is "0" (MODE-O),
executing the CKSTP instruction while the
HOLD pin is at low level stops the clock
generator and the CPU and changes to
memory back-up mode. If the MODE bit
is "1" (MODE-1), executing the CKSTP
instruction enters memory back-up mode
regardless of the level of the HOLD pin.
Memory back-up is released when the
HOLD pin goes high in MODE-O, or when
the level of the HOLD pin level in
MODE-1.
When memory back-up mode is entered
by executing a WAIT instruction, any
change in the HOLD pin input releases
the mode.
In memory back-up mode, current
consumption is low (below 10PA), and all
the output pins (e.g., display output,
output ports) are automatically set to
low level.
IFlN/IN
IF signal input/
Input port
IF counter's IF signal input pin for
counting the IF signals of the FM and
AM bands and detecting the automatic
stop position.
The input frequency is between
o.35~12MHz (0.2up-p (Min)). A built-in
input amp and C coupling allow
operation at Iow-level input.
The IF counter is a 20bit counter with
optional gate times of 1, 4, 16, and
64ms. 20 bits of data can be readily
stored in memory.
This input pin can be programmed for
use as an input port (IN port). CMOS
input is used when the pin is set as an
IN port.
2001 -06-1 9
TOSHIBA
TC9322FA/FB
PIN No.
SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
DO1/OT
comparison
output
/Output port
comparison
output
PLL's phase comparison tri-state output
When the programmable counter's
prescaler output is higher than the
reference frequency, output is at high
level. When output is lower than the
reference frequency, output is at low
level. When output equals the reference
frequency, high impedance output is
obtained.
Because DOI and D02 are output in
parallel, optimal filter constants can be
designed for the FM/VHF and AM bands.
Pin DO1 can be programmed to high
impedance or programmed as an output
port (OT). Thus, the pins can be used to
improve Iock-up time or used as output
ports.
Power-supply
Pins to which power is applied.
Normally, VDD--1.8--3.6V (3.0V Typ.) is
applied.
In back-up mode (when CKSTP
instructions are being executed), voltage
can be lowered to 1.0V. If voltage falls
below 1.5V while the CPU is operating,
the CPU stops to prevent malfunction
(STOP mode). When the voltage rises
above 1.5V, the CPU restarts.
STOP mode can be detected by checking
the STOP F/F bit. If necessary, execute
initialization or adjust clock by program.
When detecting or preventing CPU
malfunctions using an external circuit,
STOP mode can be invalidated and
rendered non-operative by program. In
that case, all four bits of the internal
TEST port should be set to "I".
If more than 1.8V is applied when the
pin voltage is 0, the device's system is
reset and the program starts from
address "o". (Power on reset)
(Note) To operate the power on reset,
the power supply should start up
in 10~100ms.
2001 -06-1 9
TOSHIBA
TC9322FA/FB
PIN No. SYMBOL
PIN NAME
FUNCTION AND OPERATION
REMARKS
54 FMIN
programmable
counter input
Programmable counter input pin for FM,
VHF band.
The 1/2 +pulse swallow system (VHF
mode) and the pulse swallow system (FM
mode) are selectable freely by program.
At the VHF mode, local oscillation output
(VCO output) of 50~230MH2 (0.2kap
(Min)) is input and FM mode,
40~130MH2 (0.2Vp-p (Min)) is input.
A built-in input amp and C coupling
allow operation at low-level input.
(Note) When in the PLL OFF mode or
when set to AMIN input, the
input is pulled down.
55 AMIN
AM local
oscillator signal
Programmable counter input pin for AM
The pulse swallow system (HF mode) and
direct dividing system (LF mode) are
freely selectable by program. At the HF
mode, local oscillation output (VCO
output) of 1--45MHz (thill/p-p (Min)) is
input and LF mode, 0.5--12MHz (0.2Up-p
(Min)) is input.
Built-in input amp operates with low-
level input using a C coupling.
(Note) When in PLL OFF mode or when
set to FMIN input, the input is
pulled down.
57 RESET
Reset input
Input pin for system reset signals.
FSET takes place while at low level , at
high level, the program starts from
address "0".
Normally, if more than 1.8V is supplied
to VDD when the voltage is 0, the
system is reset (Power on reset).
Accordingly, this pin should be set to
high level during operation.
58 XOUT
59 XIN
60 VXT
Crystal
oscillator pins
Crystal oscillator pins.
A reference 75kHz crystal oscillator is
connected to the XIN and XOUT pins.
The oscillator stops oscillating during
CKSTP instruction execution.
The VXT pin is the power supply for the
crystal oscillator. A stabilizing capacitor
(0.47/1F Typ.) is connected.
2001 -06-1 9
TOSHIBA TC9322FA/FB
PIN No. SYMBOL PIN NAME FUNCTION AND OPERATION REMARKS
Voltage doubler boosting pin for driving
the LCD.
61 VLCD A capacitor (0.1PF Typ.) is connected to
boost the voltage.
The VLCD pin outputs voltage (3.0V),
which has been doubled from the
Voltage constant voltage (VEE : 1.5V) using the
62 C1 doubler capacitors connected between C1 and C2. 5""
boosting pin That potential is supplied to the LCD
drivers. If the internal VLCD OFF bit is set
to "I" by program, an external power
supply can be input through the VLCD
pin to drive the LCD.
63 C2 At this time, the VLCD/2 potential,
whose VLCD voltage is divided using
registers, is output from the C2 pin.
1.5V constant voltage supply pin for
driving the LCD.
64 VEE Eglr’gtgaentsupply A stabilizing capacitor (0.1/1F Typ.) is -
pin connected. This is a reference voltage for
the A/D converter, key input, and the
LCD common output's bias potential.
(Note 1) When the device is reset (voltage higher than 1.8V, or when RESET=low-yhigh)
l/O ports are set to input, the pins for I/O ports and additional functions (e.g.,
A/D converter) are set to l/O port input pins, while the lFlN/IN pins become IF
input pins.
(Note 2) When in PLL OFF mode (when the three bits in the internal reference ports all
show "1"), the IFIN and FMIN, AMIN pins are pulled down, and DOI and D02 are
at high impedance.
(Note 3) When in CLOCK STOP mode (during execution of CKSTP instruction), the output
ports and the LCD output pins are all at low level, while the constant voltage
circuit (VEE), the voltage doubler circuit (I/LCD), and the power supply for the
crystal oscillator (VXT) are all off.
(Note 4) When the device is being reset, the contents of the output ports and internal
ports are undefined and initialization by program is necessary.
2001 -06-1 9
TOSHIBA TC9322FA/FB
MAXIMUM RATINGS (Ta=25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage VDD -0.3-4.0 V
Input Voltage VIN -0.3--VDD+0.3 V
Power Dissipation PD 100 mW
Operating Temperature Topr -10--60 °C
Storage Temperature Tstg - 55--125 ''C
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, Ta =25°C, VDD=3.0V)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Range Of Operating *
Supply Voltage VDD - 1.8 3.0 3.6 V
Range Of Memory V Crystal ocillation stopped * 1 0 '"- 3 6
Retention Voltage HD (CKSTP instruction executed) . .
Under ordinary
operation and PLL on
operation, no output VDD=3.0V - 7.0 12
I FMIN =230MHz input A
DDI - Under ordinary m
operation and PLL on
operation, no output VDD=3.0V - 6.0 10
. FMIN = 130MHz input
Operating Current Under CPU operation
IDD2 - (PLL off, display VDD=3.0V - 40 80
turned on)
Soft Wait mode
IDD? - (Crystal oscllator, display circuit - 25 50 pA
operating, CPU stopped, PLL off)
I Hard Wait mode 15 30
DD4 (Crystal oscillator operating only)
Memory Retention I Crystal oscillation stopped 0 1 10
Current HD (CKSTP instruction executed) .
Crystal Oscillation *
Frequency fXT - - 75 - kHz
Crystal Oscillation . .
Startup Time tST - Crystal oscillation fXT=75kHz - - 1.0 s
For conditions marked by an asterisk (*), guaranteed when VDD=1.8-3.6V, Ta = -1ir-6iy'C.
2001 -06-1 9
TOSHIBA TC9322FA/FB
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Voltage doubler circuit
Voltage Doubler
Reference Voltage VEE - GND reference (VEE) 1.3 1.5 1.7 V
Constant Voltage
Temperature DV - GND reference (VEE) - -5 - mV/°C
Characteristics
Voltage Doubler
Boosting Voltage VLCD - GND reference (VLCD) 2.6 3.0 3.4 V
Operating frequency ranges for programmable counter and IF counter
FMIN (VHF Mode) fVHF - Sine wave input when V|N=0.2Vp_p 50 -- 230
FMIN (FM Mode) fFM - Sine wave input when V|N=0.2Vp_p 40 -- 130
AMIN (HF Mode) fHL - Sine wave input when V|N=0.2Vp-p 1 -_- 45 MHz
AMIN (LF Mode) fLF - Sine wave input when V|N=0.2Vp_p 0.5 -- 12
IFIN hr: - Sine wave input when VIN =0.2Vp-p 0.35 .- 12
Input Amplitude VIN - FMIN, AMIN, IFIN input 0.2 '.%.. 1’33 Vp-p
LCD common output/segment output (COM1--COM3, S1~523)
Output "H" Level IOH1 - VLCD = 3V, VOH = 2.7V - 0.5 - 1.0 - A
Current "L'' Level IOU - VLCD=3V, V0L=0.3V 0.5 1.0 - m
Output Voltage 1/2 v35 - No load 1.3 1.5 1.7 v
HOLD input port
Input Leak Current Ity - VIH =3.0V, lhL=0V - $1.0 pA
Input "H" Level VIH1 - - 2.4 -- 3.0 V
Voltage "L" Level VIL1 - - 0 -- 1.2
A/D converter (A/D|N1, A/DIN2, DC-REF)
Analog Input Voltage
V - AD AD -- V V
Range AD lhl1, lN2 0 DD
Analog Reference VDD
Voltage Range VREF - DC-REF, VDD=2.0 3.6V 1.0 x0.9 v
Resolution VRES - - - 6.0 - bit
Conversion Total - - VDD=2.0--3.6V - 11.0 14.0 LSB
V|H=3.0V, lhL=0V +
Analog Input Leak Ity (ADINL ADIN2, DC-REF) _1.0 pA
For conditions marked by an asterisk (*), guaranteed when VDD=1.8-3.6V, Ta = -1ir-6iy'C.
2001 -06-1 9
TOSHIBA TC9322FA/FB
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
KEY input port (Ko-Ka)
N-ch/P-ch Input
. R - - 7 1 k0
Resistance IN1 5 50 300
Input "H" Level 1/IH2 - When input with pull-down resistance 1.8 -- 3.0 V
Voltage "L" Level VIL2 - When input with pull-down resistance 0 ~ 0.3
Input "H" Level VIH3 - When input with puII-up resistance 2.7 -- 3.0 V
Voltage "L" Level VIL3 - When input with pull-up resistance 0 -- 1.2
When input resistance off,
- - - +
Input Leak Current Ity VIH =3.0V, VIL=0V - 1.0 pA
Timing output port (TO-TS)
Output "H" Level IOH1 - VOH = 2.7V - 0.5 - 1.0 - mA
Current "L" Level IOL1 - VOL=0.3V, Use LCD key-return mode 0.5 1.0 -
N-ch Load Resistance RON - No used LCD key-return mode 75 150 300 k0
DO1/OT, D02 output ; MUTE output
Output "H" Level IOH1 - VOH = 2.7V - 0.5 - 1.0 - mA
Current "L" Level IOL1 - V0L=0.3V 0.5 1.0 -
Output Off Leak
- = = - - +
Current ITL VTLH 3.0V, VTLL 0V (DOI, D02) -100 nA
General-purpose I/O ports (Pl-ir-Pa-l)
Output "H" Level IOH1 - VOH = 2.7V - 0.5 -1.0 - A
Current "L" Level IOU - VOL=0.3V 0.5 1.0 - m
Input Leak Current Ity - V|H=3.0V, VIL=0V - $1.0 PA
Input "H" Level VIH4 - - 2.4 -- 3.0 V
Voltage "L" Level VIL4 - - 0 -- 0.6
IN, RESET input port
Input Leak Current ILI - VIH =3.0V, VIL=OV - $1.0 pA
Input "H" Level VIH4 - - 2.4 -- 3.0 V
Voltage "L" Level VIL4 - - 0 -- 0.6
13 2001-06-19
TOSHIBA TC9322FA/FB
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Others
Input Pull-Down
Resistance RINZ - (TEST) 25 50 100 k0
XIN Amp Feedback
Resistance RfXT - (XIN XOUT) - 20 - Mn
XOUT Output
R - X - - k0
Resistance OUT ( OUT) 3
Input Amp Feedback RfIN1 - (FM|N,AM|N) 150 300 600 k0
Resistance RfIN2 - (IFIN) 500 1000 2000
Voltage Used To
Detect Supply Voltage VSTp - (VDD) 1.3 1.5 1.6 V
Supply Voltage Drop
Detection Temperature Ds - (VDD) - -2 - mV/°C
Characteristics
14 2001-06-19
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PACKAGE DIMENSIONS
QFP64-P-1212-0.65 Unit : mm
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Weight : 0.45g (Typ.)
16 2001-06-19
TOSHIBA TC9322FA/FB
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
17 2001-06-19
:
www.loq.com
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