TC9308 ,DTS MICRO CONTROLLER CONTAINING PLL.LCD DRIVER
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TC9308
DTS MICRO CONTROLLER CONTAINING PLL.LCD DRIVER
TOSHIBA TC9308AF
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9308AF
DTS MICRO CONTROLLER CONTAINING PLL-LCD DRIVER (DTS-11)
TC9308AF is a 4bit CMOS microcontroller for digital
tuning system capable of making 3V low voltage
operation, and containing PLL circuit, LCD driver.
CPU has 4bit parallel addition and substruction (AI/Sl
instructions, etc.), logical operation (OR and AN
instructions, etc.), plural bit judge, comparison
instructions (TM, SL instructions, etc.) and time base
function.
The package is 60-pin mini-flat type, and has abundant I
/0 ports and exclusive key-input ports controlled by the
powerful input/output instructions (IO, KEY instructions), QFP60-P-1414-0.80A
besides containing PLL circuit. Weight : 0.85g (Typ.)
By combining with the prescaler TD6134AF, it permits the
configuration of DTS that receives FM/AM and TV (VHF)
bands.
FEATURES
0 4bit micro controller for digital tuning system use
0 It is operated with 3V single power supply. (VDD=1.8--3.61/)
o Back-up of data memory (RAM) and each port are easily made. (by TNTT terminal)
0 Built-in LCD driver (1 /2 duty, 1/2 bias driving, driving frequency : 50Hz), and boosting circuit for
display
0 Program memory (ROM) : 16 bitsx2048 steps
0 Data memory (RAM) : 4 bitsx128 words
0 Powerful instruction set of 65 kinds (all single word instruction)
. Instruction executing time 80ps (75kHz crystal connection)
0 Abundant addition and substraction instructions
(addition instructions 12 kinds, substraction instructions 12 kinds)
0 Powerful compound judge instructions (TMTR, TMFR, TMT, TMF, TMTN, TMFN instructions)
98091 OEBA2
O TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can
malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing
TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss
of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the
TOSHIBA Semiconductor Reliability Handbook.
0 The products described in this document are subject to the foreign exchange and foreign trade laws.
0 The information contained herein is presented only as a guide for the ap Iications of our products. No responsibility is assumed by TOSHIBA
CORPORATION for any infringements of intellectual property or other rights 0 the third parties which may result from its use. No license is granted
, implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
0 T e information contained herein is subject to change without notice.
1999-03-1 9 1/46
TOSHIBA TC9308AF
Data transfer in same low address is possible.
Indirect transfer of register is possible. (MVRD, MVRS, MVGD, MVGS instructions)
16 powerful general registers (arranged in RAM)
Stack level : 1 level
Program memory (ROM) has no conception of page, field, and JUMP and CAL instruction can be
freely made among 2048 steps.
At the FM or TV band, swallow counter is composed by combining with prescaler TD6134AF, and is
able to receive TV VHF band.
It is possible to freely refer to the content, 16 bits, of optional address within 1024 steps in
program memory (ROM). (DAL instruction)
Independent frequency input terminal at FM and AM (FMIN, AM|N), and two phase-Comparator
outputs. (D01, D02)
7 kinds of reference frequency can be selected with program.
Powerful input/output instructions. (IO, KEY instructions)
Exclusive input port (K0~K3) for key input use and abundant 22 exclusive LCD driving terminals.
Abundant 10 HO ports (ports for which input and output can be assigned for each bit : 4,
exclusive input ports : 4, exclusive output ports : 2)
3 kinds of back-up mode (only CPU operating, Crystal oscillation and Clock stop) are possible by
instructions.
2Hz timer F/F and 10Hz interval pulse output are contained. (Internal port for time base use)
Locked condition of PLL can be detected.
Universal-type IF counter is built in.
PIN CONNECTION
U E N .- E '" o E E m N '" o m N
m E O C) u. - r- D D z z z 2 cr C)
th. < CI D - C) O E m - - - - - -
'"Tr"qr"Ir"Ir"Ir"Ir"rmr"Ier"Sr"qr"Ir"Ir",
45 44 43 42 411140 39 38 371136 35 34 331132 31
FMIN 46 PLL OUTPUT INPUT I/O 30EI 101
GND 47 PORT PORT PORT g” Koo
m [E 8 F- 2811 T3
TEST 49 w'a , g 27E|12
- _ (.1
XT 50 $7,: $255 26[In
>-U I au.
XT Ll ('58 $25 {SCI To
- MmO -
INT 52 a' 2Cl K3
VDD 53 3% r- 230 NC (VDD)
VLCD 54 or- h,,, 22f] K2
oL9 -r-
C1 55 5E $8 21a K1
C2 56 (ft, ml EU K0
'ejfl -
c3 5_7 yfi, 19Tcow
COMI 58 1811 S20
SI 59 17[l S19
$2 60 LCD DRIVER OUTPUT (22) 15H S18
a 9 It) 11 12 13 14 15
1999-03-1 9 2/46
TOSHIBA
TC9308AF
BLOCK DIAGRAM
DOUBLER
CIRCUIT
SYSTEM RESET
DATA BUS
CODE BUS
REFERENCE 7
DHNDER
OSC MPX
FMIN 16bit PROGRAMABLE COUNTER
IN 16bitlFCOUNTER
IF CONTROL
COLUMN
.(1GBIT)
(16X 2048 STEP)
DATA R EG
CPU TIMING GENE.
INSTRUCTION
ADDR. DEC.
PROG. COUNTER
STACK REG.
LCD DRIVER
LCD SEG La
10Hz 2Hz
BUFFER D02
2Hz F/F
CO M PARATO R
BUFFER DOI
BUZZER
CONTROL BUZR
(4x128 WORD)
R/W BUF.
1999-03-1 9 3/46
TOSHIBA
TC9308AF
PIN FUNCTION
PIN No.
SYMBOL
PIN NAME
EXPLANATION OF FUNCTION AND OPERATION
REMARKS
LCD Common
Output
This is a common signal output terminal to
Indication of maximum 40 segments is possible
with matrix made with S1--S20.
To this terminal, three value levels of VDD,
VEE, VLCD are output with 5ms interval and
50Hz cycle.
59, 60
SI-sito
LCD Segment
Output
This is a segment signal output terminal to
Indication of maximum 40 segments is possible
with matrix made with COM1 and COM2.
The data for these terminals are output by
the execution of SEG instruction (COM1
system) and MARK instruction (COM2 system).
Key Input Port
This is a 4bit input port for key matrix input.
16 (=4x4) key data can be input with matrix
made with T0~T3 Key Return Timing Output
All these terminals are built in pull-down
resistances.
Key Return Timing
Output Port
This is a 4bit output port for Key Return
Timing Output.
Usually, it is output the timing signal for key
matrix.
For making the matrix, it is built in load
resistance at N-ch FET side, useless the diode.
IO0--lO3
I/O Port
This is a 4bit general purpose I/O port.
It is possible to assign input and output for
each bit by program.
IN0--lN3
Input Port
This is a 4bit general purpose input port.
The input data is read into the RAM at 4bit
Buzzer Pulse
Output Port
This is the beep sound pulse output port.
It is output 3 kinds of beep sound pulse
signal by program.
Mutiny Output
This is a 1bit output port.
This is usually used as muting control signal
output.
39, 40
0T0, 0T1
Output Port
This is a 2bit general purpose output port.
Output form is N-ch FET open-drain structure,
output breakdown voltage is 12V.
i i Mi
1999-03-1 9 4/46
TOSHIBA
TC9308AF
PIN No. SYMBOL
PIN NAME
EXPLANATION OF FUNCTION AND OPERATION
REMARKS
41 IFIN
IF Counter Input
This is a f signal input terminal of 16bit
general purpose IF counter.
This terminal has built-in amplifiers, and
operates with C-connection and small
amplitude.
Built-in Input
Amplifier
42, 43 DOI, D02
Phase Comparator
Output
This is a Phase comparator output terminal of
DOI and D02 are parallel outputs.
Therefore, optimum filter constant can be set
for each band of FM/AM.
44 AMIN
AM Programable
Counter Input
This is a programmable counter input terminal
at 12bit direct frequency-divider mode.
Usually the local oscillator signal at AM band
is input to this terminal.
This terminal has built-in amplifiers, and
operates with C-connection and small
amplitude.
Built-in Input
Amplifier
45 PSC
Prescaler Control
Output
This is an output terminal which controls 1/15
or 1/16 frequency-dividing mode of two
modulus prescaler.
This output signal controls two frequency-
dividing mode of external prescaler as using
programmable counter for pulse-swallow
counter.
1/15: "L",1/16:"H"
46 FMIN
FM Programable
Counter Input
This is an input terminal of programmable
counter at 16bit swallow-counter mode.
This terminal is input the divided frequency
output signal of external prescaler, and has
built-in input amplifiers and operates with C-
connection and small amplitude.
Built-in Input
Amplifier
Inhibit Input
This is a signal input terminal for selecting
radio mode.
"H" : radio ON "L" : radio OFF
o-i>o-
49 TEST
Test Input
This is an input terminal for controlling test
mode control.
At "H" level, test mode is made, and at "L"
level, normal operation is carried out.
In the test mode, the device operates as
evaluator chip, and program evaluation is
made possible on EPROM base through
combination with external simulation board.
This terminal is built in a pull-down resistance.
1999-03-1 9 5/46
TOSHIBA TC9308AF
PIN No. SYMBOL PIN NAME EXPLANATION OF FUNCTION AND OPERATION REMARKS
- This is a connecting terminal of crystal
50 XT Crystal Oscillation resonator. . Built-in
Terminal Reference crystal ef 75kHz IS cohnecteq. Oscillator
51 XT During the execution of CKSTP instruction,
oscillation is automatically stopped.
This is a system reset signal input terminal of
the device.
52 W Initializing Input During WT is at "L" level, reset is applied, o-1>o-
and when it becomes "H" level, it is normal
operation mode.
54 VLCD These are voltage double boosting terminal
55 C1 Voltage Double for driving LCD. -
Boosting Terminal Boosting capacitors are connected to these
56 C2 terminals. (Typ. 0.1--3.3pF)
Reference Voltage
Stabilizing The stabilizing capacitor of Reference Voltage
57 C3 Capacitor is connected to this terminal for LCD driving. -
Connecting (Typ. th01--thlpF)
Terminal
53 VDD Power Supply Power supply voltage is applied.
47 GND Terminal 1/DD=1.8--3.6V (Typ. 3.0V) -
1999-03-19 6/46
TOSHIBA TC9308AF
EXPLANATION OF OPERATION
C) CPU
CPU is composed of program counter, stack register, ALU, program memory, data memory, G-
register, carry F/F and judging circuit.
Program counter (PC)
Program counter is a bolck to designate the address of program memory (ROM), and is
composed of 11 bits binary up counter. This is cleared by system reset, and the program
starts from zero address.
Usually, it's increment is made one by one everytime the one instruction is executed, but
when JUMP instruction or CAL instruction is executed, the address designated at operand part
of that instruction is loaded.
Further, when the instruction (AIS, SLT, TMT, RNS instructions, etc.) having skip function is
executed, two increments of program counter is made if the result is the condition to be
skipped, and the succeeding instruction is skipped.
MSB LSB
PC10 PC9 PC8 PC7 PC6 PCS PC4 PC? PC2 PC1 PCO
2. Stack register (STACK)
This is a register composed of 1x11 bits during the execution of subroutine call instruction,
the value obtained by adding +1 to the content of program counter, namely return address,
is housed. The content of stack register is loaded on the program counter by the execution
of return instruction. (RN, RNS instructions)
This stack level is 1 level, and nesting is 1 level.
ALU has binary 4 bits parallel addition and subtraction, logical operation, comparison and
plural bit judge functions.
This CPU has no accumulator, and all operations directly treat the contents of data memory.
1999-03-1 9 7/46
TOSHIBA TC9308AF
4. Program memory (ROM)
Program memory is composed of 16bitx2048 steps and is the address of 000H-7FFH.
Program memory has no concept of page or field, so JUMP instruction and CAL instruction
can be freely used among 2048 steps.
Further, it is possible to use optional address of program memory as data area, and its
content, 16 bits, can be loaded to the data register by executing DAL instruction.
(Note) Provide the data area at the address outside the program loop in the program
memory.
7FFH OOOH
ROM 16bitx 2048 steps
2048 steps
(Note) In DAL instruction, the address of program memory can be designated as the data
area becomes 1024 steps of 000H--3FFH.
5. Data memory (RAM)
Data memory is composed of 4bitx128 words and used for storing data.
This 128 words are expressed with row address (3bit) and column address (4 bits).
64 words (row address=4H--7H) among the data memory are indirect addressing by G-
register. For this reason, when carrying out data processing within this territory, it is
necessary to designate row address by G-register beforehand Area of 00H~0FH address in
data memory is called general register, and can be used only by designating column address
(4 bits). These 16 general registers can be used for operation and transfer between data
memories. Further, it can also be used as ordinary data memory.
(Note) The column address (4 bits) to designate general register becomes register number
of the general register.
(Note) It is also possible to indirectly designate all of row address (=0H~7H) by G-register.
1999-03-1 9 8/46
TOSHIBA TC9308AF
COLUMN ADDRESS : DC
0123456789ABCDEF
- GENERAL REGISTER
(ONE OF 00H~0FH ADDRESS)
ROW ADDRESS JDR
____________________'1
INDIRECTLY DESIGNATE 5
ROW ADDRESS (4H--7H)
BY G-REGISTER.
ix.'.; INDIRECT DESIGNATION
OF ROW ADDRESS (0H--7H)
IS ALSO POSSIBLE 7
RAM (4bit x 128 WORDS)
6. G-register (G-REG.)
G-register is a 3 bits register for addressing row address (DR=4H--7H) of 64 words in data
memory.
Content of this register is effective during executing MVGD instruction, MVGS instruction, and
is not related with the execution of other instructions.
This register is treated as one of the port, and its content is set by the execution of IO
instruction among input and output instructions.
(refer to register port item 1 page 37)
7. Data register (DATA REG.)
This is a register composed of 1x16 bits. In this register, 16 bits data of optional address
among the program memory is loaded during executing of DAL instruction. This register is
treated as one of the port, and when KEY instruction among input and output instruction is
executed, it's content is read in the data memory in 4 bits unit.
(refer to register port item 2 page 37)
8. Carry F/F (C-F/F)
This is set when carry or borrow is produced as a result of executing operational instruction,
and is reset when it is not produced. Content of carry F/F changes only when addition and
subtraction instruction is executed, and does not change during the execution of other
instructions.
1999-03-19 9/46
TOSHIBA TC9308AF
9. Judging circuit (J)
When a instruction with skip function is executed, this circuit judges it's skip condition. When
skip condition is satisfied, this circuit makes two increments of program counter, and skips
the succeeding instruction.
It is provided with 31 kinds of instructions having abundant skip function.
(refer to Item 11, explanation list of function and operation of instructions, .yd. marked
instruction page 11--17)
10.List of instruction set
65 kinds of instruction set are included, all of which consisting of one word instruction.
These instructions are expressed with 6 bits instruction code.
HIGHER RANK 00 01 10 11
LOWER 2 BITS
RANK 4 BITS 0 1 2 3
0000 0 Al M, I AD r, M LD r, M SLTI M, I
0001 1 AIS M, I ADS r, M ST M, r SGEI M, I
0010 2 AIN M, I ADN r, M MVRD r, M SEQI M, I
0011 3 SI M, I SU r, M MVRS M, r SNEI M, I
0100 4 SIS M, I SUS r, M MVSR M1, M2 SLT r, M
0101 5 SIN M, I SUN r, M MVIM M, I SGE r, M
0110 6 CAL ADDR1 ORR r, M MVGD r, M SEQ r, M
0111 7 ANDR r, M MVGS M, r SNE r, M
1000 8 AIC M, I AC r, M PLL M, C TMTR r, M
1001 9 AICS M, I ACS r, M SEG M, C TMFR r, M
1010 A AICN M, I ACN r, M MARK M, C TMT M, N
1011 B SIB M, l SB r, M IO M, C TMF M, N
1100 C SIBS M, l SBS r, M KEY M, C TMTN M, N
1101 D SIBN M, I SBN r, M WAIT P TMFN M, N
1110 E JUMP ADDR1 ORIM M, I XORIM M, I DAL ADDR2, r
1111 F ANIM M, I XORR r, M RN, RNS, CKSTP, NOOP
1999-03-1 9 10/46
TOSHIBA
TC9308AF
11.Explanation list of function and operation of instructions (Explanation of symbols)
: Data memory address
Normally, one of 00H~3FH address of data memory.
: General register
One of 00H~0FH address of data memory.
: Program counter (11 bits)
: Stack register (11 bits)
: G-register (3 bits)
: Data register (16 bits)
: Immediate data (4 bits)
: Bit position (4 bits)
: All "0"
: Code No. of port (4bit)
: Lower rank 3bit of port code No.
: General register No. (4bit)
: Program memory address in page 0 or 1 (10bit)
: Higher rank 6bit of program memory address in page 0
: Carry
: Borrow
: Port treated during the execution of PLL instruction
: Port treated during the execution of SEG instruction
: Port treated during the execution of MARK instruction
: Port treated during the execution of IO instruction
: Port treated during the execution of KEY instruction
: Register or data memory content
: Content of port indicated by code No. C (4bit)
: Content of data memory indicated by the content of register or data memory
: Content of program memory (16bit)
: Instruction code (6bit)
: Instruction having skip function
: Data memory column address (4bit)
: Data memory row address (2bit)
: Wait condition select bit at WAIT instruction
(Note)
Address 000H--3FFH of program memory address : Page 0 area
Address 400H--7FFH of program memory address : Page 1 area
1999-03-1 9 11/46
TOSHIBA
TC9308AF
. 9 MACHINE LANGUAGE (16bit)
r- EXPLANATION OF EXPLANATION OF
2 'g MNEMONIC l y, FUNCTION OPERATION IC A B c
if, E (6bit) (2bit) (4bit) (4bit)
AI M, I Add immediate data Me-(M)+I 000000 DR DC I
to memory
Add immediate data
AIS M, I to memory, then skip 1rfivf"il,, 000001 DR Dc I
if carry p y
Add immediate data
AIN M, I to memory, then skip Ir/if,,') carr 000010 DR DC I
if not carry p y
AIC M, I Add immediate data Me-(M)+l+ca 001000 DR Dc I
to memory with carry
Add immediate data
o AICS M, I to memory with carry, M‘.‘(M)+'+Ca 001001 DR DC I
- . . Skip if carry
r- then skip if carry
3 Add immediate data
m AICN M, I to memory with carry, yt-ilu])') 001010 DR DC I
r- . . Skip if not carry
V‘ then skip if not carry
E dd t
AD r, M A memm." o re-(r)+(M) 010000 DR Dc RN
a general register
9 Add memory to re-(r) o(M)
l ADS r, M general register, then Ski if can 010001 DR Dc RN
fl skip if carry p y
< Add memory to
ADN r, M general register, then SE“); (d), carr 010010 DR DC RN
skip if not carry p y
Add memory to
AC r, M general register with re-ir)+(M)+ca 011000 DR Dc RN
Add memory to
general register with re-(r)+(M)+ca
ACS r, M carry, then skip if Skip if carry 011001 DR DC RN
Add memory to
general register with re-(r)-r(M)+ca
ACN r, M carry, then skip if not Skip if not carry 011010 DR DC RN
1999-03-19 12/46
TOSHIBA TC9308AF
. 9 MACHINE LANGUAGE (16bit)
r- EXPLANATION OF EXPLANATION OF
2 'g MNEMONIC l y, FUNCTION OPERATION IC A B c
if, E (6bit) (2bit) (4bit) (4bit)
Subtract immediate
I M I -
S ' data from memory Me-(M) I 000011 DR DC I
Subtract immediate
SIS M, I X data from memory, yt-(lr).-l 000100 DR Dc I
. . Skip if borrow
then skip if borrow
Subtract immediate
= data from memory, Me-(M)-l
SIN M, I X then skip if not Skip if not borrow 000101 DR DC I
borrow
Subtract immediate
SIB M, I data from memory Me-(M)-l-b 001011 DR Dc I
a with borrow
l) Subtract immediate
'- w. data from memory Me-(M)-l-b
y SIBS M, I Jo.'i. with borrow, then Skip if borrow 001100 DR DC I
ff skip if borrow
2 Subtract immediate
- . data from memory Me-(M)-l-b
a SIBN M, I X with borrow, then Skip if not borrow 001101 DR DC I
9 skip if not borrow
r- Subtract memory from
SU ' M . - 11 D D
:1) r general register re-(r) (M) 0100 R C RN
ttt Subtract memory from
m SUS r, M X general register, then rfr.(r). (M) 010100 DR Dc RN
3 . . Skip if borrow
m skip if borrow
Subtract memory from
SUN r, M X general register, then 'tr/r). ( ) 010101 DR Dc RN
. . Skip if not borrow
skip if not borrow
Subtract memory from
SB r, M general register with re-(r)-(M)-b 011011 DR Dc RN
borrow
Subtract memory from
= general register with re-(r)-(M) -b
SBS r, M )ir.1(. borrow, then skip if Skip if borrow 011100 DR DC RN
borrow
Subtract memory from
w. general register with re-(r)-(M) -b
SBN r, M X borrow, then skip if Skip if not borrow 011101 DR DC RN
not borrow
1999-03-1 9 13/46
TOSHIBA TC9308AF
MACHINE LANGUAGE (16bit)
MNEMONIC EXPLANATION OF EXPLANATION OF
FUNCTION OPERATION IC A B c
(6bit) (2bit) (4bit) (4bit)
FUNCT ION
Skip if memory is less
than immediate data
Skip if memory is
greater than or equal Skip if (M)al 110001 DR DC I
to immediate data
SLTI M, I Skip if (M)
SGEI M, I
Skip if memory is
SEQI M, I Jo.K. equal to immediate Skip if (M)=I 110010 DR Dc I
Skip if memory is not
SNEI M, I .)K. equal to immediate Skip if (M)=l 110011 DR DC I
Skip if general
SLT r, M X register is less than Skip if (r)<(M) 110100 DR Dc RN
memory
Skip if general
register is greater
than or equal to
memory
Skip if general
SEQ r, M yd. register is equal to Skip if (r)=(M) 110110 DR Dc RN
memory
Skip if general
SNE r, M .)K. register is not equal Skip if (r)=(M) 110111 DR DC RN
to memory
Load memory to
general register
Store general register
to memory
Move memory to
destination memory
MVRD r, M referring to general [DR, (r)le-(M) 100010 DR Dc RN
register in the same
INSTRUCT ION
SGE r,M .24 Skipif(r)2(M) 110101 DR DC RN
COMPAR | SON
LD r,M re-(M) 100000 DR Dc RN
ST M, r Me-(r) 100001 DR DC RN
INSTRUCT ION
Move source memory
referring to general
register to memory in
the same row
MVRS M, r hlle-[DR, (r)] 100011 DR DC RN
TRANSFER
1999-03-1 9 14/46
TOSHIBA
TC9308AF
. 9 MACHINE LANGUAGE (16bit)
F- EXPLANATION OF EXPLANATION OF
l' g MNEMONIC l y, FUNCTION OPERATION IC A B C
if, E (6bit) (2bit) (4bit) (4bit)
a Move memory to
o MVSR M1, M2 memory in the same (DR, DCI)e-(DR, DC2) 100100 DR Dc1 DC2
F- row
3 MVIM M, I Move immediate data Me-l 100101 DR Dc I
ff to memory
111 Move memory to
E destination memory
tE MVGD r, M referring to G-register [(G), (r)]e-(M) 100110 DR Dc RN
1.... and general register
bt Move source memory
a referring to G-register
g MVGS M, r and general register Me-[(G), (r)] 100111 DR Dc RN
r- to memory
Input PLL port data
PLL M C to memory MHPLLlc 101000 DR DC 0 CN
' Output contents of [PLL] s-(M) D D 1 C
a memory to PLL port C R C N
l) Input SEG port data Me-[SEG] D D 0 C
t SEG M c to memory C 101001 R C N
2 ' Output contents of [SEG] s-iM) D D 1 C
1; memory to SEG port C R C N
a Input MARK port data
- M MARK D D
to memory s-f k R C 0 CN
2 MARK M, c Output contents of 101010
f: memory to MARK [MARK1ce-(M) DR Dc 1 CN
8 port
CI Input IO port data to Me-llOlc DR DC 0 CN
i? IO M C memory 101011
' Output contents of [IO] e-(M) D D 1 C
2 memory to IO port C R C N
tlL Input KEY port data
- KEY M c to memory MHKEWC 101100 DR DC 0 CN
' Output contents of [KEY] s-(M) D D 1 C
memory to KEY port C R C N
1999-03-19 15/46
TOSHIBA TC9308AF
. I' MACHINE LANGUAGE (16bit)
r- EXPLANATION OF EXPLANATION OF
2 'g MNEMONIC l k2) FUNCTION OPERATION IC A B c
if, E (6bit) (2bit) (4bit) (4bit)
Logical OR of general
ORR r, M register and memory re-(r)V(M) 010110 DR Dc RN
Logical AND of
ANDR r, M general register and re-(r)A(M) 010111 DR DC RN
memory
ORIM M, I Logical OR of memory Me-(M)VI 011110 DR DC I
and immediate data
Logical AND of
ANIM M, I memory and Me-(M)Al 011111 DR Dc I
immediate data
Logical exclusive OR
XORIM M, I of memory and Me-(M)(Pl 101110 DR Dc I
immediate data
LOG I CAL OPERATION
INSTRUCT ION
Logical exclusive OR
XORR r, M of general register rr-(r)O(M) 101111 DR DC I
and memory
Test general register
bits by memory bits, Skip if r [N (M)]
then skip if all bits =all "I"
specified are true
TMTR r,M .)K. 111000 DR DC RN
Test general register
bits by memory bits, Skip if r [N (M)]
then skip if all bits =all "0"
specified are false
TMFRr,M yd. 111001 DR Dc RN
Test memory bits,
TMT M, N X then skip if all bits Skip if M (N)=all "1" 111010 DR Dc N
specified are true
INSTRUCT ION
Test memory bits,
TMF M, N .)K. then skip if all bits Skip if M (N)=all "0" 111011 DR DC N
specified are false
Test memory bits,
TMTN M, N .)rd. then not skip if all
bits specified are true
Skip if M (N)
=not all "I
" 111100 DR Dc N
Test memory bits,
TMFN M, N .)K. then not skip if all
bits specified are false
Skip if M (N)
=not all "o" 111101 DR DC N
1999-03-1 9 16/46
TOSHIBA TC9308AF
. 9 MACHINE LANGUAGE (16 bit)
r- EXPLANATION OF EXPLANATION OF
2 o: MNEMONIC l U FUNCTION OPERATION IC A B c
- 1.9 a
if, E (6bit) (2bit) (4bit) (4bit)
anes‘gbmuune In STACKe-(PC)+1 and 000110
a CALL ADDR1 p g . . PG-ADDR, in page 0 ADDR1 (10 bit)
No Call subroutine in
z_ or 1 000111
I: r- page 1
82 RN Rety.rn to mam PCe-(STACK) 111111 00 - -
DEE routine
g; Return to main
m_ RNS .)K. routine and skip PCe-(STACK) and skip 111111 01 - -
unconditionally
Jump to the address 001110
a-r- s ecified in a e 0 PCE-ADDR in a e 0 .
2m JUMP ADDR1 p p g 1 p g ADDR1 (10 bit)
3 Jump to the address or 1
-'- . . . 001111
specified In page 1
At P= "0"H, the
condition is CPU
a waiting - -
9 WAIT P (Soft “ff": mode) Wait at condition P 101101 P
F- At P= 1 H, except
g for clock generator,
E all function is waiting
E (Hard wait mode)
- Load program
tE DAL ADDR2, r memory in page 0 to i:et/IDDR2+(0' 111110 A(EESZ RN
l' DATA register p g
O CKSTP Clock generator stop i',t,-1''=c,,t,k generator if 111111 10 - -
NOOP No operation - 111111 11 - -
(Note 1) During the execution of input and output instruction, control of input/output
instruction is automatically carried out at the most significant bit in Code No. (C)
of port.
0 MSB="1" of Code No. (C) : Output instruction
0 MSB="0" of Code No. (C) : Input instruction
(Note 2) In the TC9308AF, the input port treated by the execution of SEG, MARK
instruction does not exist, so these input instruction can not be used.
(Note 3) Among 10 bits of the program memory address assigned by DAL instruction, the
lower rank of 4 bits become indirect addressing based on the content of general
register.
DAL instruction executing time is 160ps.
1999-03-1 9 17/46
TOSHIBA TC9308AF
C) Connection of crystal resonator
Connect 75kHz crystal resonator with the crystal oscillator terminals (XT, x_T terminal) of the
device as shown below. This oscillation signal is supplied to clock generator and reference
frequency divider, and produced each timing signal of CPU and reference frequency signal.
Adjust the crystal oscillation frequency while monitoring LCD segment output terminal.
t x_T XT f
, Lo?) Q9 50 51 GZ) t9 '
il X'tal X'tal=75kHz
I! CL CL=30pF Typ.
(Note) Use crystal resonator of low CI value and satisfactory starting characteristics.
C) System reset
System reset is applied to the device when "L'' level is given to TNici' terminal, or when the
voltage, OV-iN-iv is supplied to VDD terminal (power on reset).
After the lapse of 100ms stand-by time succeeding to the system reset, program starts from zero
address.
As power on reset function is employed usually, TtTIT' terminal is fixed at "H" level.
(Note 1) During the system reset time and the succeeding stand-by time, LCD common output
and segment output are fixed at "L" level.
(Note 2) After system reset, all of I/O ports are set at input mode, but initialization of output
port and internal port (G-register, etc.) is not carried out. Especially, at the initial power
on stage, content of these ports is indefinite, and therefore it is necessary to make
initialization with program according to your use.
1999-03-1 9 18/46
TOSHIBA TC9308AF
C) Back up mode
If CKSTP instruction or WAIT instruction is executed when Tti"ifil" terminal is at "L" level, it can
select for the three kinds of back up mode.
1. Clock stop mode
If CKSTP instruction is executed when IN-H terminal is at "L" level, clock generator and CPU
internal of the device stop operation completely, and memory back up state can be realized
at low current consumption (IPA MAX. at VDD=3V).
At this time, LCD display driver terminals and output ports are all fixed at "L" level or off
condition. During this clock stop mode, supply voltage can be reduced down to 1.2V and
used for exchange of battery.
So this mode is available when the battery is changed in the radio set.
In clock stop mode, program stops at the execution address of CKSTP instruction.
The clock stop mode is released at TNFl="H" level or changing the input condition of I/O
port (IOO~|O3) set at input mode, and the next address is executed after the lapse of stand-
by time of 100ms.
(Note 1) In the clock stop mode, the condition of output terminal is all fixed at "L" level or
off but output port holds on the data just before clock stop mode.
(Note 2) When CKSTP instruction is executed during W="H" level, the same operation as
NOOP instruction is made (Clock stop mode is not entered).
(GND) (m) (W) (VDD)
t (Q a (G) a GD 63 (ii 6% t
:1 tl [i + L.-
o'T 2T 2 ,
l” 157
T RADI
RADIO ON/OFF SIGNAL o O
SUPPLY
EXAMPLE OF THE MEMORY BACK UP CIRCUIT USING CAPACITOR AT CLOCK STOP MODE
1999-03-1 9 19/46
TOSHIBA TC9308AF
2. Waiting mode
If WAIT instruction is executed when INH terminal is at "L" level, it can select the hardware
waiting mode or the software waiting mode.
Software waiting mode
If WAIT instruction is executed at designated operand port [P=OH], only CPU internal of
the device stop operation, and software waiting mode can be realized at low current
consumption. Since the other part of clock generator and display circuit operate normally,
at the time of using the program of clock function, the software waiting mode is effective
to realize at low current consumption during the clock operation.
Hardware waiting mode
If WAIT instruction is executed at designated operand part [P=1H], all the function
without crystal oscillator are stopped and hardware waiting mode can be realized at lower
current consumption than software waiting mode (under 100PA at VDD=3.0V). At this
time, CPU and display circuit stop operation, output terminal for LCD display is fixed at
"L" level automatically.
In these waiting mode, program stops at the execution address of WAIT instruction, and
waiting is released in following condition, so next address is executed.
Released condition of waiting mode
0 Changing to TNTT:"H" level
0 Key input terminal (K0~K3) is set at "H" level.
It 2Hz timer F/F is set at "I".
It Changing the input condition of I/O port (|00~|O3) set at input mode
0 MUTE port is set at "I".
(Note) In waiting mode, each of output terminal is held on the condition just before
waiting mode.
1999-03-1 9 20/46
TC9308AF
TOSHIBA
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1999-03-1 9 21/46
TOSHIBA
TC9308AF
C) I/O map
All ports in the device are expressed by matrix of five input and output instruction (PLL
instruction, SEG instruction, MARK instruction, IO instruction, KEY instruction) and 4 bits of code
No.C. Assignment of these ports is indicated previously as IIO map. In the I/O map, port names
treated in the execution of each input and output instruction are assigned horizontally, while
code No. of port are assigned vertically. G-register and data register are also treated as port.
Basically, the data is treated at each port as 4 bits unit, and code No. (C)=0H--7H are assigned
to input port, while code No. (C)=8H--FH are assigned to output port.
(Note 1) The port indicated with oblique line on I/O map is a port not existing in the device. In
the execution of output instruction, when data is output to the non-existing output
port, no effect is given to the content of other port or data memory. When non-
existing input port is designated during the execution of input instruction, the content
read into the data memory becomes indefinite.
(Note 2) Among the output ports on I/O map, .)'.o( marked port is unused port. The data
outputted here becomes "don't care".
(Note 3) Regarding the content of port expressed in 4 bits, Y1 corresponds to the least
significant of the data of data memory, and Y8 to the most significant bit. Data of
each port is all treated with positive logic.
(Note 4) Each port assigned by five input and output instruction and code No. C is coded as
follows :
¢m/_L1mn
I-operand part CN of input and output instruction
(Lower 3 bit value of code No. of port : o--7)
5 kinds of input and output instruction are described in No. I--5
INPUT AND OUTPUT
INSTRUCTION PLL SEG MARK IO KEY
m 1 2 3 4 5
Expresses input/output port (K : input port, L : output port)
1999-03-1 9 22/46
TOSHIBA TC9308AF
C) Programmable counter
Programmable counter block is composed of external two modulus prescaler TD6134AF, 4
bits+ 12 bits programmable binary counter, and PLL output ports to control them.
1. PLL output port (/L10--/L14)
The exclusive PLL port is used to control the division number and the dividing mode and
made access by PLL output instruction designated operand part [CN =0~4].
1) Structure of PLL port
¢L10 ¢L11 fL12 ¢L13 ¢L14
FM P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15
Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
SETTING OF PROGRAMMABLE COUNTER DIVISION NUMBER OF 16 BITS
SETTING OF DEVIDING MODE
2) Setting of dividing mode
Pulse swallow mode or direct dividing mode are selected by FM port. In AM band, it
selects the direct dividing mode. In FM or VHF band, it selects pulse swallow mode
combined with external two modulus prescaler, TD6134AF.
EXAMPLE OF OPERATING INPUT DIVISION
FM DIVIDING MODE RECEIVING BAND FREQUENCY RANGE TERMINAL NUMBER PRESCALER
0 Direct Dividing Mode MW/LW 0.5--2.5MHz AMIN n -
1/4x(1/15 or 1/16) (Note 1) (Note 2)
FM FMIN
1 Pulse swallow Mode 50~150MH2 4.n TD6134AF
1/8x(1/15 or 1/16) VHF (Note 1) FM 8.n
Pulse swallow Mode 50~250MH2 IN
(Note 1) This shows the input frequency range to TD6134AF.
(Note 2) "n" shows the programmed division number.
1999-03-1 9 23/46
TOSHIBA
TC9308AF
3) Setting of frequency division number
Division number of programmable counter is set on P0~P15 ports with binary.
o Pulse-swallow mode (16bit)
P15 P14
.)'d. Frequency division number setting range (pulse swallow mode)
n =210H--FFFFH (528--65535)
It Direct dividing mode (12bit)
P15 P14
P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
Unrelated
yd. Frequency division number setting range (Direct dividing mode)
n =10H~FFFH (16--4095)
(Note 1)
(Note 2)
(Note 3)
As the programmable counter is not provided with dividing offset, the
programmabled number becomes the actual frequency division number.
However, in the case of FM band, the actual frequency division
number becomes four times of programmed value, and in VHF band,
the actual frequency division number becomes eight times of
programmed value in combination with prescaler TD6134AF.
In case of direct dividing mode, P0~P3 port (¢L11) data becomes
unrelated and P4 port becomes LSB.
Frequency division number is entirely renewed at the time of data
setting of MSB port (¢L14).
So this prevents wrong influence from giving to the lock up time.
For this reason, the data of MSB port (¢L14) must be set at the end of
division number. Even when the data setting is considered unnecessary
(when the data is same as the previous one), the data setting of MSB
port (¢L41) must be executed.
1999-03-1 9 24/46
TOSHIBA TC9308AF
2. Circuit construction of external prescaler and programmable counter
1) Circuit construction of pulse swallow dividing mode
The circuit is composed of (1 /4 or 1/8x1/15, 1/16) 2-modulous prescaler TD6134AF and
swallow counter of 4 bits and binary programmable counter of 12 bits. In the case of FM
band, it selects 1/4 divider to the front stage of 2-modulous prescaler, and in VHF band,
it selects 1/8 divider to the front stage of 2-modulous prescaler.
The block diagram including prescaler is shown as follows.
VCC VHF/FM
10PF 0
0.1/1F
0.001%
Cji) PC 'ei,
._'01#F: PO-P?
0 01,5 AMP. Cl
. 4 BITS
g-G) BUF. Cs_iC-a, SWALLOW COUNTER
PRESET
TD6134AF
12 BITS TO PHASE
PROGRAMMABLE
OUNTER COMPARATOR
._, P4-P15
TC9308AF
2) Circuit construction of direct dividing mode
In this case, it is unnecessary to use the external prescaler, 12 bits programmable counter
is only used.
PRESET
12BIT PROGRAMMABLE COUNTER
TO PHASE
COMPARATOR
0.01M:
(iii)o-iifj, D,
P4-P15
(Note) Both FMIN and AMIN have built-in amplifiers, and the small amplitude
operation is possible through the capacitor coupling.
1999-03-1 9 25/46
TOSHIBA TC9308AF
C) Reference frequency divider
This block divides oscillating frequency of external 75kHz crystal, and produces seven kinds of
PLL reference signal, 1kHz, 3kHz, 3.125kHz, 5kHz, 6.25kHz, 12.5kHz, 25kHz. Selection of reference
signal is carried out with the data of REF select port.
The selected signal is supplied to the phase comparator as the reference frequency.
1. REF select port (¢L10)
This is an internal port to select seven kinds of reference frequency signal.
Normally, this port is made access by PLL instruction designated the operand part [CN =ol
(¢L10).
Y1 Y2 Y4 Y8
fbL10 #0 #1 #2 REF. Output Code Table
R #2 #1 #0 REFERENCE FREQUENCY
eference Frequency
Selection Code 0 0 0 0 1KHz
0 0 1 1 3kHz
0 1 0 2 3.125kHz
0 1 1 3 5kHz
1 0 0 4 6.25kHz
1 0 1 5 12.5kHz
1 1 0 6 25kHz
1 1 1 7 REF. output is stopped
1999-03-1 9 26/46
TOSHIBA TC9308AF
C) Phase comparator
The phase comparator outputs the error amount comparing the phase difference between the
reference frequency signal supplied from the reference frequency divider and the programmable
counter dividing output. VCO is controlled through low-pass filter so that the frequencies and
the phase-difference of these two signals may coincide.
Since two tri-state buffer DOI and D02 terminals are parallel output from the phase
comparator, the filter constant can be optimumly designed for each band of FM/VHF and AM.
Reference Frequency Signal
Programmable s
Counter
Output
COMPARATOR
“J M |_I l-l, |_ DC-DC
l I CONVERTER V (3V)
s I n n m F) Cl cc
l l 'I II HIGH LEVEL 445
DO l l Ji. et fe" 0.0.1.,uF
FLOATIN/g- TO VCO 1 F tL7kQ
LOW LEVEL VARACTOR -JL-''s'), - 'v',
DIODE LL cis. 22142
1 CCP .
G. 2SC4116GR 2SK209Y DO
DO Output Timing Chart Example of Active LOW-PASS Filter Circuit (for reference)
DO output timing chart and example of active Iow-pass filter circuit structured by darlington
connection of FET and transistor are shown in the above figures.
The filter circuit shown in the above figure is an example for reference, and the actual circuit
should be investigated and designed conforming to the system band construction and the
required characteristics.
1999-03-1 9 27/46
TOSHIBA
TC9308AF
C) Unlock detection bit (¢LK16)
This is the bit for detecting the locked state of PLL system. When PLL system is unlocked state,
namely, in the state in which the reference signal and the dividing frequency of programmable
counter do not coincide, the pulse is output from the phase comparator to the unlock F/F with
the cycle of the reference frequency.
By this pulse, the unlock F/F is set. At every time when the unlock-reset bit is set to "1" by PLL
output instruction designated the operand part [CN=6], the unlock F/F is reset (¢L16).
After the unlock F/F is reset, the locked condition can be detected by access the unlock
detection bit with PLL input instruction (¢K16). Since the pulse is input with the cycle of the
reference frequency, after the unlock F/F is reset, it is necessary to make access the unlock
detection bit after the time exceeding the cycle of the reference frequency. If the time is shorter
than the cycle, the correct locked condition can not be detected.
So the test enable F/F is prepared. Every time when the unlock reset bit is set to "I", the test
with the unlock detection timing. In short, it is able to detect
the unlock condition correctly at "1" state of the test enable bit (¢K16).
enable F/F is reset and set to
REFERENCE FREQUENCY
PROG RAMMABLE
COUNTER OUTPUT
DO OUTPUT
PHASE ERROR
LOCK DETECTION STROBE
EXECUTION OF
UNLOCK RESET
UNLOCK DETECTION BIT
TEST ENABLE BIT
$—--—-f
Y1 Y2 Y4 Y8
UNLOCK
UNLOCK TEST 0 0
DETECTION ENABLE
UNLOCK DETECTION
Detected PLL unlock condition
PLL normal operation (Undetected unlock)
At every time when the unlock reset bit is set
to "1", the unlock F/F and the test enable F/F
is reset.
TEST ENABLE
Possible to detect PLL unlock condition
condition
Waiting for the detection of PLL unlock
1999-03-1 9 28/46
TOSHIBA TC9308AF
C) General IF counter
16 bits general IF counter is able to detect the auto-stop signal with counting intermediate
frequency (IF) of FM or AM band at auto-tuning mode. The general f counter is available for
auto tuning function of IF counting type easily in combination with TA8132F, a AM/FM IF+MPX
IC corresponding to DTS. IF counter block is composed of 16 bits binary counter and the port for
IF counter control.
1. IF counter data port (¢K11~¢K15)
This is the data input port for input the counted data of IF counter and operating condition.
The data is read into data memory by PLL input instruction designated the operand part
[CN =1--51.
¢K11 ¢K12 fbk13 ¢K14
Y1 Y2 Y4 Y8 - - -
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
20 215
LSB IF Counter Data Input MSB
The counted data of IF counter is inputted with binary from the input port, F0~F15.
Y1 Y2 Y4 Y8
BUSY MANUAL OVFLOW 0 Overflow Detection
f,' : f Counter Values216-1
: IF Counter Value>216 (Overflow condition)
Operation Mode
{0 : IF Counter Auto Mode
1 : f Counter Manual Mode
Operation Monitor
{0 : Ended of IF Counting
1 : During IF Counting
This is the input port for detecting operation condition of IF counter (¢K15).
In case of using IF counter, the counted data (F0~F15) should be calculated after confirming
"o" of BUSY bit (end of IF counting) and OVFLOW bit (not overflow condition).
1999-03-1 9 29/46
TOSHIBA TC9308AF
2. IF counter control port (¢L15)
This is the data output port controlled for f counter operation. This port is made access by
PLL output instruction designated the operand part [CN=5].
Y1 Y2 Y4 Y8 Selection bits of IF counter Gate-time
sr/s/Fr, MANUAL #0 #1 #0 #1 GATE-TIME [ms]
1 1 16
Change the mode (AUTO/MANUAL) of IF Counter
1 : Manual mode
0 : Auto mode
Control start or stop of IF counter
{1 : IF Counter starts
0 : f Counter stops
At the auto mode (MANUAL bit is set to "o"), the STA/W bit is set to "1" every time, IF
counter starts. IF counter counts during the gate time selected by #0, #1 bits, and it ends
automatically. ----
At manual mode, when the STA/STP bit is set to "1", IF counter counts continuously until
the STA/''irt'P" bit is set to "O".
(Note) At -lNT4--''0", IF counter is reset by compulsorily.
3. Circuit construction of IF counter
IF counter is composed of input Amp., gate-time control circuit, 16 bits binary counter.
FO-F15 OVFLOW
OVERFLOW
16 BITS BINARY COUNTER DETECTION
SIGNAL
TA8132AF
GATE TIME CONTROL CIRCUIT =
t I BUSY MANUAL
START MANUAL
TC9308AF
At AM band AM IF signal is input to IFIN (TC9308AF Pin 41) from TA8132AF directly, at FM/
VHF band 1/8 divided output of FM/VHF IF signal is input to IFIN.
(Note) IFIN terminal has built-in amplifier, and the small amplitude operation is possible
through the capacitor coupling.
(Note) If it is used without TA8132AF, 1/8 divided IF signal should be input to IFIN
(TC9308AF Pin 41) at FM/VHF band.
At AM band, IF signal is input directly.
1999-03-1 9 30/46
TOSHIBA TC9308AF
O LCD driver
The TC9308AF contains LCD driver of 1/2 duty and 1/2 bias driving (frame frequency=100Hz).
Two common terminals (COM1, COM2) output three potentials of voltage, VDD, VEE, VLCD level
respectively with 1/4 phase difference.
40 segments can be displayed by the combination of these common outputs and 20 segment
outputs (S1~SZO). That is to say, both COM1 system segment and COM2 system segment can be
displayed by one segment output, what is called dynamic display method.
LCD driver does not contain segment decoder, so 40 segments can be freely used by program for
7-segment display or mark segment display.
COM1 system segment output is controlled by execution of SEG instruction and COM2 system
segment output is by execution of MARK instruction.
l. Timing chart of LCD driver
Below are shown the timing chart of COM1, COM2 output wave form and four kinds of
segment output wave form.
I 20ms
""""" VDD
COM1 I I ----vEE
I I t - VLCD
I I LCD SEGMENT
COM2 I t
l I l l COM1 COM2
I I I I SYSTEM SYSTEN
l I I '----VDD
I I - VLCD
SEGMENT I I '
OUTPUT , I -
(Note) During system reset and back up mode (CKSTP instruction executing),
common output and segment output are all fixed at "L'' lavel
automatically.
2. COM1 system segment port (¢L20~¢L24)
This is a port group to output 20 segment data of COM1 system. It is made access by SEG
output instruction. Segment data is treated with 4 bits unit, and COM1 system segment turns
"ON" when data "1" is output, while COM1 system segment turns "OFF" when data "0" is
output.
Y1 Y2 Y4 Y8
s s s s s s s s s s s s s s s s s s s s
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
¢L20 ¢in fbL22 ffL23 ¢L24
1999-03-1 9 31/46
TOSHIBA
TC9308AF
3. COM2 system segment port (/L30--/34)
This is a port group to output 20 segment data of COM2 system. It is made access by MARK
output instruction. Segment data is treated with 4 bits unit, and COM2 system turns "ON"
when data "1" is output, while COM2 system segment turns "OFF" when data "0" is output.
Y1 Y2 Y4 Y8
s s s s s s s s s s s s s s s s s s s
1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
¢L31 ¢L32 ¢L33 ¢L34
o DISP OFF bit (¢L35)
This bit controls turning on or off of LC display. When data
is set to this bit, common
outputs and segment outputs are all fixed at "L" level, all display becomes turned off.
When data "0" is set to this bit, display becomes normal action. And this bit is reset to
"o" after system reset.
(Note)
(Note)
The name of each port of COM1 system and COM2 system corresponds to the
name of segment output terminal, respectively. And as the content of each port
don't accept DISP OFF bit's influence, even display off made by DISP OFF bit, it is
able to output the data to each segment port normally.
Decoding of segment can be made by providing the segment decode pattern in
the program memory and reading it into the data memory by using DAL
instruction. Therefore LCD driver doesn't have built-in segment decoder especially.
As DAL instruction refers to the data in the program memory with 16 bits unit,
assignment of segment port appropriated to the made 7-segment display is
continuously performed with 8 bits unit (7-segment+1 mark) for example port
S1~S4, port S5--S8 both COM1 system and COM2 system in common.
Y1 Y2 Y4 Y8
DISP . . . 1 : All LC display is turned off
OFF 2( >.< It 0 : LC display normal operation
4. Voltage boosting circuit for LC display
TC9308AF has built-in voltage boosting circuit for LC display, it is able to stabilize LC display
driving at the low voltage operation. This circuit is composed with 1.5V reference voltage
circuit (VEE) and voltage double boosting circuit (VLCD), be connected the boosting capacitor
as follows.
l VDD VLCD C1 C2 C3 l
v w, ft fish, r59 Ci?,
oo-tClif-, "iuc"i' 'ff, C=0.1luF Typ.
VDD-- 1,8~3,6V C >:<1MQ c C
3.0V Typ.
)K. Be connected the register for improving the motive characteristics of voltage
boosting circuit.
1999-03-1 9 32/46
TOSHIBA TC9308AF
C) Input and output port
I/O port IO0--IO3 (¢KL41)
I/O port is 4 bits CMOS type, and is capable of making input and output setting with each
Input and output setting of I/O port is made by the content of I/O control internal port.
Setting to input port can be made by setting "0" to the bit of I/O control port
corresponding to I/O port, while setting to output port can be made by setting "I" in the
In case of input port setting, the present data input I/O port is read into the data memory
by the execution of IO input instruction designated the operand part [CN=1] (¢K41). At this
time, input data is set to output latch of I/O port (¢L41) in the same.
In case of output port setting, output condition of I/O port is controlled execution of IO
output instruction designated the operand part [CN=1]. And the present output data of I/O
port is read into the data memory by the execution of IO input instruction (¢K41).
(Note) l/O control port is made access by KEY instruction designated the operand part
[CN=1]. After system reset, the content of this port is all reset to "o", and I/O port
is all set up input mode.
(Note) During the clock stop mode (executing CKSTP instruction), output condition of HO
port set at output mode is all fixed at "L" level automatically, but each output latch
holds on the data just before the clock stop mode.
(Note) At the time of changing input condition of I/O port set at input mode, it cancels
the execution of WAIT and CKSTP instructions and makes the operation restart. In
case of setting "1" to l/O-bit of MUTE control port, MUTE port is made to set to
"1" compulsorily by the same condition.
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢KL41 IOO lOl I02 |03 ¢L51 IOO lOl K92 I03
E—J %—J
I/O PORT Set Up Input and Output of HO PORT
General input port IN0--IN3 (¢K43)
|N0~IN3 is input port of 4 bits, CMOS type. By the execution of IO input instruction
designated the operand part [CN :3], input data is read into the data memory. The data is
input with positive logic.
Y1 Y2 Y4 Y8
¢K43 INO INI IN2 IN?
1999-03-1 9 33/46
TOSHIBA TC9308AF
3. General output port 0T0, 0T1 (¢L42)
0T0 and 0T1 are output port of 2 bits, N-ch FET open-drain structure. It is made access by
the execution of IO output instruction designated the operand part [CN =2] (¢L42). When this
port is set to "1", the N-ch transistor turns on, so output becomes "L'' level. When this port
is set to "o", the N-ch transistor turns off, output becomes high impedance. To make the
output "H" level, be connected puII-up resistor. Then output can drive the voltage of 0~12V.
(Note) During the clock stop mode (executing CKSTP instruction), 0T0, 0T1 output is off
condition automatically, but the content of port is held on the previous data.
Y1 Y2 Y4 Y8
¢L42 0T0 0T1 ik. .)K.
4. Key timing output port T0~T3 (¢L46)
T0--T3 is exclusive output port of 4 bits, CMOS type. Normally, it is used as output of key
return timing signal for key matrix. So, the resistor is built-in at Nch transistor side and sink
current is decreased.
Therefore, of using push key, the diode can be omitted on the key matrix. Output port is
made access by IO output instruction designated the operand part [CN =6] (¢L46). In case of
using for normal output port, take care to make the external circuit because of output
impedance of "L" level increased.
(Note) During the clock stop mode (executing CKSTP instruction), T0~T3 output is fixed at
"L" level automatically, but the content of port is held on the previous data.
Y1 Y2 Y4 Y8
f L46 T0 T1 T2 T3
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TOSHIBA TC9308AF
5. MUTE port (¢KL40)
This is a 1bit CMOS type exclusive output for muting control. Normally, it is made access by
IO output instruction designated operand part [CN=0] (¢L40).
Further, by the execution of IO input instruction designated operand part [CN =ol, content of
present output data is read into data memory (¢K40).
And according to the data of MUTE control port (¢L50), MUTE port is controlled.
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢L40 MUTE ik. >:< M.'. ¢L50 W IIO POL )K
a—J u---'
don't care I
o INH Bit
In case of setting "1" to this bit, MUTE port is set to "1" compulsorily by changing of TiilTf
input level (''L"-y''H'' or "H"-9"L").
0 HO Bit
In case of setting "1" to this bit, MUTE port is set to "L'' compulsorily by input level
changing of I/O port set at input mode.
0 POL Bit
The bit controls output polarity of MUTE port. In case of setting "0" to this bit, the data
of MUTE port is output with positive logic. In case of setting "I" to the bit, the data of
MUTE port is output with negative logic.
(Note) After system reset, the content of TNT-T, I/O, POL each bit is reset to "0".
1999-03-1 9 35/46
TOSHIBA TC9308AF
O Buzzer port
Buzzer output is available as beep sound for confirmation of key operation, and as alarm sound.
It uses as 1bit general output port. The buzzer output condition is controlled by buzzer control
port (¢L43) as follows. Buzzer control port is made access by IO output instruction designated
the operand part [CN=3].
Y1 Y2 Y4 Y8 Selection Bits of Buzzer Port Output Mode
#0 #1 #2 #3 #2 #3 BUZZER OUTPUT MODE
'-r-o '-e-u
f 0 0 Single Output (Mode A)
1 0 Continuous Output (Mode B)
0 1 Continuous Output for 100ms Period
(At intervals of 50ms) (Mode C)
1 1 Continuous Output for 100ms Period
and At intervals of 500ms (Mode D)
Selection Bits of Buzzer Frequency
#0 #1 BUZZER FREQUENCY [kHz]
0 0 Don't use
0 1 1.5
(Note) In case of using buzzer port as general output port, the following data is set to
buzzer control port.
#0 #1 #2 #3 OUTPUT CONDITION OF BUZZER PORT
0 0 0 O L
0 0 1 0 H
(Note) In case of setting all "o" to the buzzer control port and of executing CKSTP or
WAIT (at P=1H) instruction, buzzer output is reset.
(Note) In case of using as general output port, output is fixed at "L" level by executing
CKSTP instruction, but the content of this port is held on.
Below are shown the timing chart of buzzer signal output and buzzer frequency wave form.
Buzzer Frequency Output
Mode A -lllllll, (1kHZ/1.5kHz/3kHz) 1kHz -!-I-r
50ms 1.5kHz ei-I-i-I-
ModeB LLLLLLLLLI ----- I 1
WI |_l ci-
ModeC Ill" Illlll -
50ms 50ms f Output Condition 200ps133ps
of Mode C
Mode D I I I I I -
500ms500ms
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TOSHIBA TC9308AF
C) Register port
G-register and data register stated in the explanation of CPU are also treated as one of internal
ports.
1. G-register (¢L44)
This is a register to make addressing of low address (DR=4H--7H) of data memory during the
execution of MVGD instruction and MVGS instruction. This register is made access by IO
output instruction designated the operand part [CN =41.
(Note) Content of this register is effective only during the execution of MVGD instruction
and MVGS instruction, and gives no effect during the execution of other
instructions.
Y1 Y2 Y4 Y8
¢L44 #0 #1 #2 i.'4 #2 #1 #0 DR
Low address of data (1:5; 1 0 0 4H
memory is designated 1 O 1 5H
I 1 1 0 6H
1 1 1 7H
(NOTE) It is possible to indirectly designate all low address of data
memory by setting data OH--7H on G-register. (DR=0H--7H)
2. Data register (/K54--/K57)
This is 16bit register on which the data of program memory is loaded by the execution of
DAL instruction. Content of this register is read into the data memory in 4bit unit by the
execution of KEY input instruction designated the operand part [CN =4~7].
This register is available for the decoding of LCD segment, or for the taking of band edge
data of radio and coefficient data during binary to BCD conversion.
Y8 Y4 Y2 Y1
D D D D D D D D D D D D D D D
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
¢K57 ¢K56 fbK55 ¢K54
MSB Program memory 16bit data LSB
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TOSHIBA
C) Key input
TC9308AF
Exclusive 4 bits key input terminal for key matrix data input is provided. Four terminals contain
pulldown resistors.
1. Key input port (¢K52)
This is exclusive key input port of 4 bits, the data of key input terminal is read into the data
memory by the execution of KEY input instruction designated part [CN =ill.
Y1 Y2 Y4
¢K52 K0 K1 K2
2. Key status bit (¢K45)
Key Status Bit
Key status bit (KEY ON) is provided for purpose of knowing the outline of present key input
status. Content of this bit is read into data memory by execution of IO instruction designated
operand part [CN=5].
0 KEY ON bit
Logical OR of four input data of K0~K3 terminals is output. This is available for judging
existance of key input. When KEY ON bit is "1" (In case of inputting "H" level to key
input terminal K0--K3), it releases execution of WAIT instruction, the operation is removed.
1999-03-1 9 38/46
TOSHIBA TC9308AF
C) Internal control port
Internal control port is used for reading into data memory the inside condition of device which
must be known in the execution of program, or for resetting the inside condition of device.
Y1 Y2 Y4 Y8 Y1 Y2 Y4 Y8
¢K44 INH 0 0 0 ¢K45 F/F 10Hz
H_J H_J
Timer Interval
r-------,-:,:--''---))------'-')-'-'"""'""
Y1 Y2 Y4 Y8
2Hz CLOCK . .
¢L45 F / F Y'.! ..x.
RESET RESET
1. W input port (¢K44)
This is an input port for inputting the data of TNTI input terminal. Content of this port is
read into the data memory by IO instruction designated the operand part [CN=4]. Data "I''
and "o" represent radio "ON" mode and "OFF" mode, respectively.
At radio off mode, it stops operating of PLL and IF counter block. When TNT-T bit of MUTE
control port is "I", MUTE port is set to "1" compulsorily by changing the data of TNT? input
port. At fNifif input port is "1", it releases execution of CKSTP instruction and the operation is
removed. By changing the condition of TNTT input port, execution of WAIT instruction is
released.
2. 2H2 timer F/F (¢K45)
2H2 timer F/F is set by 2Hz (500ms) signal. With the execution of IO output instruction
designated the operand part [CN =5] this timer is reset by setting data "1" to 2Hz F/F RESET
bit. This F/F output is read into the data memory by execution of IO input instruction
designated the operand part [CN =51.
As 2H2 timer F/F is automatically set every 500ms, it is usually available for counting of
clock.
Since 2H2 timer F/F is reset only by 2Hz F/F RESET bit, count error takes place unless data
"I" is set to 2Hz F/F RESET bit within 500ms period, and correct times is not obtainable.
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TOSHIBA TC9308AF
(Note) Condition of 2H2 timer F/F output becomes "0" at power on reset or after
execution of CKSTP instruction.
2H2 TIMER F/F OUTPUT
(SETTING "1" TO Reset
2HZ F/F RESET BIT, t<500ms
2H2 CLOCK I
3. 10Hz interval pulse (¢K45)
10Hz interval pulse is output to 10Hz bit with 100ms period, duty 50% pulse. This is read
into the data memory by the execution of IO input instruction designated the operand part
[CN=5]. This output has no flip flop and is available for mute time counting etc.
10Hz INTERVAL
PULSE OUTPUT
4. Other control bit (¢L45)
o CLOCK RESET bit
Every time data "1" is set to this bit, clock of under 50Hz is reset (10Hz interval pulse is
also reset). This bit is used for adjusting time of clock.
Accuracy of clock at this time is -0, +0.02 second.
5. TEST port (¢L57)
This is an internal port for testing function of device. It is made access by KEY output
instruction designated the operand part [CN=7]. Never fail to set data "o" in ordinary
program.
Y1 Y2 Y4 Y8
¢L57 #0 #1 .2(. .)k
u-v---'
Set the data "0" surely.
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TOSHIBA
TC9308AF
C) Application to evaluator chip
When "H" level is supplied to TEST terminal (Test mode), device operates as evaluator chip, and
functional evaluation of developing program can be made by utilizing external simulation board
and EPROM. In the test mode, the device operates with the program written in EPROM,
irrespective of the content of program memory in the device.
As key timing output port (T0--T3) and output port (0T0, 0T1) are transferred to the input and
output terminal for control of simulation board at this time, actual T0~T3 and 0T0, 0T1 port
signal are output from the simulation board side.
Below is shown connection diagram of the device and simulation board in case that it is used as
evaluator chip.
A- 256k EPROM
SIMULATION BOAD
A_c-st
- 5Vi10%
_ 3VA10%
SUPPLIED
SUPPLIED
TC9308AF
OPERATING MONITOR LED ACTUAL T0~T3
0T0, 0T1 PORT OUTPUT
0T1 IE 0
3— GND
POWER SUPPLY OF
DEVICE 3Vur 10%
SUPPLIED
J \SYSTEM RESET SWITCH
(Note) Supply 31/* 10% voltage to the device and 5Vi10% voltage to the simulation board
even during back-up mode.
(Note) Each terminal of the device except that shown above can be used normally.
(Note) In case of back-up mode (execution of CKSTP instruction), operating monitor LED on
the simulation board turns off.
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TOSHIBA TC9308AF
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Power Supply Voltage VDD -0.3--4.0 V
Input Voltage VIN -0.3--VDD+0.3 V
Power Dissipation PD 100 mW
Operating Temperature Topr -10--60 "C
Storage Temperature Tstg -55--125 "C
Open Drain Output
Breakdown Voltage VBDS 12 V
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta =25°C, VDD=3.0V)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Operating Power Supply VDD - X 1.8 3.0 3.6
Voltage Range
Memory Holding Voltage
Crystal oscillation stops
VHD - (Excuting CKSTP instruction), 1.2 3.6
I Normal operation, output
DD1 No-Ioad
At only CPU operation
IDD2 - (Radio off, lighting display) - 75 150
At stand-by mode (Radio off,
I - - 1 A
DD3 only crystal oscillation) 50 00 [1
Crystal oscillation stop
IHD - (Excuting CKSTP instruction) - 0.1 1.0
Operating Power Supply
Current
Memory Holding Power
Supply Current
Crystal Oscillation
- .yd. - -
Frequency fXT 75 kHz
girx‘sécal Oscillation Starting tST - Crystal oscillation=75kHz - - 1.0 s
VOLTAGE DOUBLE BOOSTING CIRCUIT
Voltage Double Reference
V - V f 1.2 1. 1.
Voltage EE DD re erence 5 8 V
Voltage Double Boosting
Voltage VLCD - VDD reference 2.4 3.0 3.6
)..k. Marked items are guaranteed by all conditions of VDD=1.8--3.6V, Ta = -10--6ty'C
1999-03-1 9 42/46
TOSHIBA TC9308AF
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
PROGRAMMABLE COUNTER, IF COUNTER
Operating Frequency fIN1 - (FMIN, AMIN) 0.5 25
Range VIN =0 3Vp p MHz
f - . - 0.35 -- 20
lN2 (IFIN)
le =o.5~2.5MHz
V - 0.3 ~ V -0.3
Operating Input llN11 (FMIN, AMIN) DD V
. - - p-p
Amplitude Range V|N2 - fIN =0.35 2.0MHz 0.3 _ I/DD-O.?
(IFIN)
FMIN-PSC Propagation VIN =0.3Vp-p
Delay Time tpd - CL--15PF(FMIN) - - 400 ns
PSC Maximum Load
Capacity CL - (PSC) - - 15 pF
LCD COMMON OUTPUT
" " VLCD=0V, VOH =2.7V
H Le el I - -100 -200 -
Output V OHI (COM1, 2) PA
Current " " VLCD=0V, VOL=0.3V
L Level IOL1 - (COM1, 2) 100 200 -
LCD SEGMENT OUTPUT
" " VLCD=0V, VOH =2.7V
H Level I - -50 -100 -
Output 0H2 (S1--S20) pA
Current " " VLCD=0V, VOL=0.3V
L Level IOLZ (S1~520) 50 100
KEY RETURN OUTPUT PORT
Output " "
H Level I - V =2.7V TO~T3 -0.5 - 1.0 - mA
Current 0H3 OH ( )
N-ch FET Side Load
Resistance RON - VOL=3.OV (T0 T3) 37 70 140 kn
MUTE, BUZR, PSC OUTPUT
Output "H" Level IOH4 - VOH =2.7V -300 -600 - A
Current "L" Level IOL4 - v0L=o.3v 300 600 - '
GENERAL PURPOSE OUTPUT PORT
tet,', "L" Level IOL4 - VOL=0.3V (0T0, 0T1) 300 600 -
Output Off-Leakage - ’u
Current ILDS - VDS - 12V (0T0, 0T1) - - 1.0
.yci Marked items are guaranteed by all conditions of VDD=1.8~3.6V, Ta= -10--6iy'C
1999-03-1 9 43/46
TOSHIBA TC9308AF
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
DOI, 2 OUTPUT
Output "H" Level lOH4 - l/OH =2.7V -300 -600 - A
Current "L" Level IOL4 - V0L=0.3V 300 600 - "
Output Off-Leakage - - +
Current ITL - VTLH =3.OV, VTLL=OV - - 1100 nA
GENERAL PURPOSE l/O PORT
Output "H" Level I0H4 - V0H=2.7V (lO0--lO3) -300 -600 -
Current "L" Level |OL4 - VOL=0.3V (|OO~|O3) 300 600 - PA
Input Leakage Current lly - VIH=3.01/, lhL=0V - $1.0
Input "H" Level IhHI - (|OO~|O3) 2.4 _ 3.0 v
Voltage "L" Level 1/IL1 - (|OO~|O3) 0 - 0.6
Tlil', INPUT, GENERAL PURPOSE INPUT PORT
Input Leakage Current 'Ll - VIH=3.OV, lhL=0V - 11.0 PA
Input "H" Level VIHZ - (ltlrr, IN0--IN3) 2.4 ~ 3.0 v
Voltage "L" Level V|L2 - (W, IN0--IN3) 0 - 0.6
KEY INPUT PORT
Input Pull-down
Resistance RIN1 - (K0 K3) 80 140 280 km
Input "H" Level 1/IH3 - (K0--K3) 2.1 ~ 3.0 V
Voltage "L" Level l/ILS - (K0--K3) 0 - 0.6
IN-H INPUT PORT
Input Leakage Current 'Ll - VIH=3.OV, 1/IL=0V - 11.0 PA
Input "H" Level VIH4 - - 2.6 - 3.0 V
Voltage "L" Level lhL4 - - 0 - 1.2
OTHERS
Input Pull-down
Resistance RIN2 - (TEST) 25 45 90 kfl
XT Input Feedback -
Resistance RfXT - (XT XT) 2.5 10 15 M0
WT Output Resistance ROUT - (rr) 50 100 200 kfl
1999-03-19 44/46
TOSHIBA TC9308AF
EXAMPLE FOR CONNECT WITH PRESCALER TD6134AF
Vcc VHF/FM
0.55M: wr
0001,»
-(2 o CD--"-,
(iii) 0001/5 , .i.
0.001PF TD6134AF
I /-"i'_.i.? Ci)-
Cti) 4 5 0.01/1F
TC9308AF
1999-03-1 9 45/46
TOSHIBA TC9308AF
OUTLINE DRAWING
QFP60-P-1414-0.80A Unit : mm
17.6:t0.3
14.0:02
1 4.0:!:0.2
17 6:0 3
cu. tf
Cp.-.-,
-T.LL N
Weight : 0.859 (Typ.)
1999-03-1 9 46/46
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