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TC9296AF
DIGITAL SERVO SINGLE CHIP PROCESSOR BUILT IN 1 BIT DA CONVERTER
TOSHIBA TC9296AF
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9296AF
DIGITAL SERVO SINGLE CHIP PROCESSOR BUILT IN 1 BIT DA
CONVERTER
FEATURES
The TC9296AF is a single chip processor which
incorporates the following function : synchronous
separation protection and interpolation, EFM
demodulation, Error correction, microcontroller interface,
digital equalizer for use in servo LSI and servo control
circuit.
In addition, the TC9296AF incorporates a 1 bit DA
converter. In combination with the head amplifier
TA2066F for digital servo, the TC9296AF allows simplified,
adjustment-free structuring of CD player system.
QFP100-P-1620-0.65
Weight : 1.69 (Typ.)
Sync pattern detection, sync signal protection and synchronization can be made correctly.
Built in EFM demodulation circuit, subcode demodulation circuit.
Capable of correcting dual C1 correction and triple C2 correction using the CIRC correction
theoretical format.
Jitter absorbing capacity of A6 frames.
Built in 16K RAM.
Built in digital out circuit.
Built in variable pitch control circuit.
Built in digital peak meter circuit.
Built in L/R independent digital attenetor.
Audio output responds to bilingual function.
Reed timing free subcode Q data and capable of synchronous output with audio data.
Built in data slicer and analog PLL (free-adjustment VCO).
Capable of automatic adjustment function of focus servo and tracking servo, offset, loop gain and
balance.
961001 EBA1
OTOSHIBA is continually working. to improve the quality and the reliability of its products. Nevertheless, semiconductor
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
OThe information contained herein is subject to change without notice.
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
is assumed. by TOSHIBA CORPORATION for any infringements of intellectual property or.other rights of. the third
parties which may result from its use. No license IS granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
1997-08-27 1/14
TOSHIBA TC9296AF
0 Built in digital equalizer for phase compensation.
o Built in RAM for digital equalizer coefficient and capable of variable pickup.
0 Built in focus, tracking servo control circuit.
Search control corresponds to every mode and can realize high speed and stable search.
Built in AFC circuit and APC circuit for CLV servo of disc motor.
Built in defect and shock-free circuit.
Built in 8 times oversampling digital filter and 1 bit DA converter.
Soft mute function.
Capable of double speed operation.
Built in microcontroller interface circuit.
9 CMOS silicon structure and high speed, low power consumption.
0 100 pin flat package.
1997-08-27 2/14
1997-08-27 3/14
BLOCK DIAGRAM (TOP VIEW)
TC9296AF - 3
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SSA (5,3
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vsm (fy)
_|\ DA
CV Converter
Generater
< Audio
Output
om Ct----'
[01 e---"
ZOI (rc---'
tol (tr-I
Covrection
Interface
Address
16k RAM
NOWG GH--w
aows (S-s
NOWi (i--'
Servo Comm“ Block
dOWG (ir-v
om Ci--'
owe Ci--,
Dan (it--
081 Ct------
ooa C-i-o
Automatic Control
gital Equaiizer :
CD-ROM
Digxta! Out
Separation
Demoduration
_"''"",
'i')"ri',
i,-:--:',
'i"yi'l'ririr''rr'ri'"ii"'"j,"
'i''''',")'':'
Subcode
Status
Slicer
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TOSHIBA
TC9296AF
TOSHIBA TC9296AF
PIN FUNCTION
PIN No. SYMBOL I/O FUNCTIONAL DESCRIPTION REMARKS
1 MCK 0 Internal master clock output terminal.
Test terminal. . .
2 TESTO I Normally set either to "H" or open. With pull-up resistor
-_.r.-r_ Chip enable for microcontroller interface.
3 CCE I . . . .
The bus line becomes active at "L". Schmitt input
4 BUCK I Data sending/receiving clock input terminal.
5 BUSO . .
6 BUS1 Data input/output terminal for microcontroller Schmitt in.put
7 BUS2 l/O interface. Open drain OUIPUI
With puII-up resistor
8 BUS3
9 DOUT 0 Digital output terminal.
10 ROUT 0 CD-ROM data output terminal.
11 DACK O P-ROM data reading clock output terminal.
This can be select 2.8/5.6MH2 by command.
Correction flag output terminal. It turns to "H"
12 IPF o when AOUT output is unable to correct C2
correction.
Output terminal of CRCC judgment result of
13 SBOK O subcode Q data. It turns "H" when CRCC
judgment is OK.
14 CLCK I Input terminal for subcode P-W data reading
clock.
15 VDD - Digital supply voltage terminal. (+5V)
16 V55 - Digital ground terminal.
17 DATA 0 Output terminal subcode P-W data.
18 SFSY O Regenerated frame sync signal output.
19 SBSY O Subcode block sync signal output.
20 SPCK 0 T"y"." status signal reading clock output
terminal. (176.4kHz)
21 SPDA 0 Processor status signal output terminal.
22 COFS o Correction frame clock output terminal.
(7.35kHz)
Lock status output terminal. It turns to "H"
23 W 0 when sync pattern of 17ms during EFM signal
are not detected consecutively.
24 MONIT O LSI internal signal monitor terminal.
DMOP, DMON terminal mode settin terminal. . .
25 DMCNT I This outputs AFC and APC errors atg"L". With pull-up resistor
26 TESIN I Test input terminal.
- Test in ut terminal. . .
27 DACT I Norma|I|)y set either to "H" or open. With pull-up resistor
1997-08-27 4/14
TOSHIBA TC9296AF
PIN No. SYMBOL I/O FUNCTIONAL DESCRIPTION REMARKS
28 PVREF - PLL reference supply voltage terminal. (VREF)
Phase difference signal output terminal of EFM 3-state output
29 PDO O . .
signal and PLCK signal. (21/REF, I/REF, AVSS)
TMAX detection output treminal.
DETECTION RESULT TMAX OUTPUT 3-state output
30 TMAX O Longer than "AVSS" (2VREF, l/REF, AVSS)
Shorter than fixed freq. "2VREF"
Within the fixed freq. "VREF"
31 LPFN I Inversion input terminal of LPF amplifier. Analog input
32 LPFO O Inversion output terminal of LPF amplifier. Analog output
33 PZVREF - PLL reference supply voltage terminal. (2VREF)
34 VCOF O VCO filter terminal.
35 AVss - Analog ground terminal.
36 SLCO 0 Data slice level output terminal. Analog output
37 RFI I RF signal input terminal. Analog input
38 AVDD - Analog supply voltage terminal. (+5V)
39 AVSS - Analog ground terminal.
40 RFIS I RFRP detection input terminal. Analog input
41 VREF - Analog reference supply voltage terminal.
42 RFRO O RFRP detection output terminal. Analog output
43 RFRP I RF ripple signal input terminal. Analog input
44 FEI I Focus error signal input terminal. Analog input
45 SBAD I Sub beam adder signal input terminal. Analog input
46 TWD I Window comparator input terminal. Analog input
Test in ut terminal. . .
47 TSIN I 2',s,tm"atl set either to "H" or open. With puII-up resistor
48 TEI I Tracking error signal input terminal. Analog input
49 TEZI I Tracking error zero inputter terminal. Analog input
50 ZVREF - Analog reference supply voltage terminal.
51 FOO 0 Focus servo equalizer output terminal. Analog output
52 TRO 0 Tracking servo equalizer output terminal. Analog output
53 LDC O ALPC circuit ON/OFF signal output terminal.
It output "H" when laser ON.
Focus balance control signal output terminal.
54 FEBC o It outputs PWM signal of 3-state. (323:2: 0;}:ErtAVSS)
(PWM carrier : 88.2kHz) ' '
1997-08-27 5/14
TOSHIBA TC9296AF
PIN No. SYMBOL I/O FUNCTIONAL DESCRIPTION REMARKS
Tracking balance control signal output terminal.
. 3- tat t t
55 TEBC 0 It outputs PWM signal of 3-state. (2:, e I)', pu AV )
(PWM carrier : 88.2kHz) REF, REF, SS
Disc motor equalizer output terminal.
56 DMO o It outputs PWM signal of 3-state. (3233“? Je,',", )
(PWM carrier : 88.2kHz) REF, REF, SS
Feed moter equalizer output terminal.
57 FMO o It outputs PWM signal of 3-state. (32'3“? 1)'ef,, )
(PWM carrier : 88.2kHz) REF, REF, SS
Disc motor equalizer output terminal.
. . 2- t t t t
58 DMOP 0 It outputs PWM signal when +polarity. (Vs a evou)pu
(PWM carrier : 88.2kHz) DD, ss
Disc motor equalizer output terminal.
. . 2- t t t t
59 DMON 0 It outputs PWM signal when -polarity. (VS a evou)pu
(PWM carrier : 88.2kHz) DD, ss
Feed motor equalizer output terminal.
60 FMOP o It outputs PWM signal when +polarity. Estatevou;put
(PWM carrier : 8&2kHz) DD, ss
Feed motor equalizer output terminal.
. . 2- t t t t
61 FMON o It outputs PWM signal when -polarity. (VS a evou)pu
(PWM carrier : 88.2kHz) DD, ss
62 FLGA
63 FLGB o External flag terminal for internal signal.
64 FLGC
65 l/SS - Digital ground terminal.
66 VDD - Digital power supply voltage terminal. (+5V)
67 FLGD 0 External flag terminal for internal signal.
External shock signal input terminal.
68 EXTS I It makes tracking equalizer gain up mode when With puII-up resistor
at "L".
69 IOO
70 lOl
I/O General I/O port.
71 lO2
72 IO3
73 VPD 0 Phase comparator output terminal of variable 3-state fyti.'.ut
pitch control. (VDD. Hi2, I/ss)
X'tal selection terminal. It is "L" at 16.9344MH2
74 CKSE I
and "H" at 33.8688MHz.
75 VXI I Clock input terminal for variable pitch VCO. Analog input
76 VXO O VXI terminal input buffer output terminal.
1997-08-27 6/14
TOSHIBA TC9296AF
PIN No. SYMBOL I/O FUNCTIONAL DESCRIPTION REMARKS
77 XVDD - 'ftaros.cilatiy. circuit power supply voltage
terminal. (+5V)
78 XI I X'tal oscillation circuit input terminal.
79 XO 0 X'tal oscillation circuit output terminal.
80 XVSS - X'tal oscillation circuit ground terminal.
81 DVSS - Analog ground terminal for DA converter R
channel.
82 RO o R channel data output terminal.
83 W O R channel data inversion output terminal.
84 DVDD - DA converter supply voltage terminal. (+ 5V)
85 m o L channel data inversion output terminal.
86 LO 0 L channel data output terminal.
87 DVSS - Analog ground terminal for DA converter L
channel.
Test terminal.
88 TEST1 I ' With ll- . t
Normally set either "H" or open. I pu up rests or
Test terminal.
89 TEST2 l . Wi h ll- .
Normally set either "H" or open. it pu up resistor
90 VDD - Digital supply voltage terminal. (+5V)
91 Vss - Digital ground terminal.
Test terminal.
92 TEST3 . - .
I Normally set either "H" or open. With pull up resistor
93 BCK C) Bit clock output terminal.
(1.4122MHz)
94 AOUT 0 Audio data output terminal.
Channel clock output terminal.
It outputs "L" when L channel and "H" when R
95 LRCK O channal.
The output polarity can be invertible by
command.
96 WDCK 0 Word clock output terminal. (88.2kHz)
Subcode Q data emphasis flag output terminal.
97 EMPH o It turns to H when emphaels ON and. L .
when OFF. The output polarity can be invertible
by command.
Double speed mode output terminal.
98 H50 0 It outputs "H" when normal speed and "L''
when double speed.
Test terminal.
99 TEST4 I . Wi h ll- .
Normally set either "H" or open. it pu up resistor
100 AST I Reset Signal, Input terminal.
It turns to L when resetting.
1997-08-27 7/14
TOSHIBA TC9296AF
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Power Supply Voltage VDD -0.3-5.5 V
Input Voltage VIN -0.3--VDD +0.3 V
Power Dissipation PD 1250 mW
Operating Temperature Topr - 25--75 "C
Storage Temperature Tstg - 55--150 "C
DC CHARACTERISTICS (Unless otherwise specified, VDD = 5V, 2VREF =4.2V, VREF = 2.1V, Ta = 25°C)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Operating Supply Voltage VDD - 4.75 5.0 5.25 V
. XI=16.9344MHz,
Operating Supply Current IDD - In normal mode - 55 90 mA
"H" Level VIH CMOS input 3.5 - -
In ut Volta e " - .
p g "L Level VIL terminals - - 1.5 V
Input Current l' Level 'lH - VIH =5V 0xcept analog - - 1.0
"L Level h. lhL=0V input terminal -1.0 - - A
Try State Leak "H" Level ITLH - 1hH=5V @Terminal - - 1.0 '
Current "L" Level ITLL 1/IL=0V -1.0 - -
"H" Level IOH - VOH=4.6V (DTerminal - -1.0
"L" Level IOL - VOL=0.4V 2.0 - -
"H" Level IOH - VOH=4.6V (DTerminal - -1.0
Output Current "L" Level IOL - VOL=0.4V 2.0 - - mA
"H" Level 'OH - VOH=3.8V (3)Terminal - - -1.0
"L" Level IOL - VOL=0.4V 1.0 - -
VREF Output ON Resistance RON - - - 500 n
. Rupm STerminal 25.0 50.0 75.0
Pull-Up Resistance RUP(2) BUS3~BUSO 8.0 20.0 32.0 kn
Pull-Down Resistance RDW - CKSE 25.0 50.0 75.0 kn
Osc.Amp.Feedback Resistance RN - XI XO between 2.0 4.0 6.0 M0
TERMINAL NAME CONDITION
MCK, BUSO, BUS1, BUS2, BUS3, DOUT, ROUT, DACK, VDD=5.0V, Vforce=4.6/0.4V
COTerminal TMAX, FMOP, FMON, DMOP*, DMON*, FLGA, FLGB, (*) DMOP, DMON (DMCNT="H")
FLGC, FLCD, VPD, BCK, AOUT, LRCK, WDCK
2)Terminal IPF, SBOK, DATA, SFSY, SBSY, SPCK, SPDA, COFS,
LOCK, MONIT, LDC, IOO, lol, IO2, |O3, EMPH, HSO
(3)T . I FEBC, TEBC, FMO, DMO, DMOP*, DMON* 2VREF=4.0V, Vforce=3.8/0.4V
ermma (*) DMOP, DMON (DMCNT="L")
@Terminal TMAX, IOO, lol, lO2, IO3, VPD VDD=5.0V, 1/force--4.6/0.41/
(STerminal DMCNT, DACT, EXTS, ITS-T, TESTO--TEST4
1997-08-27 8/14
TOSHIBA TC9296AF
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Total Harmonic 1kHz sine wave
Distortion + Noise THD + N 1 Full-scale input - - 85 - 80 dB
S/N Ratio S/N 1 90 98 - dB
. 1kHz sine wave
D R DR 1 - B
ynam'c ange -60dB input conversion 90 95 d
Cross-talk CT 1 IkHz sme'wave - -95 -85 dB
Full-scale input
TEST CIRCUIT 1 : Application circuit example-it is used.
LOUT 20kHz DISTORTION
TC9296AF FACTOR
ROUT IDEAL LPF GAUGE
LPF : SHIBASOKU 725C BUILT-IN FILTER
DISTORTION FACTOR GAUGE : SHIBASOKU 725C OR EQUIVALENT
DISTORTION FACTOR GAUGE
MEASURING ITEM FILTER SETTING A WEIGHT
THD + N, CT OFF A WEIGHT : IEC-A OR EQUIVALENT
S / N, DR ON
1997-08-27 9/14
TOSHIBA TC9296AF
AC CHARACTERISTICS
Clock system timing
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
"H" Le el t 18 - -
Clock Width " " V HW
L Level tLW . 18 - -
. . . - XI input ns
Input Rising Time tr - - 10
Input Falling Time tf - - 10
. "H" L I t - - 60
Transfer Time " " eve pHL1 - Xl-9hek
(1) L Level tpLH1 - - 60
. "H" Level t - - 60
Transfer Time " " pHL2 - MCK-9BCK ns
(2) L Level tpLH2 - - 60
Transfer Time "H" Level tpHL3 - MCK-9COFS - - 100
(3) "L" Level tpLH3 - - 100
Output RISIrlg Tlrne (1) tor1 - MCK, BCK - - 15 ns
Output Falling Time (1) tof1 - - 15
Out ut Risin Time 2 t - - 40
p . g . ( ) or2 - COFS ns
Output Falling Time (2) tof2 - - 40
tr tf I tHW I ttyy _,
tpLH1 tor1 tof1
MCK / N
tpH L2. 3
tpLH2, 3
BCK, COFS
1997-08-27 10/14
TOSHIBA TC9296AF
MICROCONTROLLER INTERFACE
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
- WRITE, SRC mode 1.0 - -
BUCK Clock Width H Level tBHW - QDRC mode(x1) 6.0 - -
- QDRC mode (x2) 3.0 - -
"L" Level tBLW - 1.0 - -
CCE "H" Clock Pulse Width tCC - CCE falling reference 1.0 - -
-ttt, BUCK Delay Time tCB - ttt rising reference 0 - -
CCE Status Data Access Time tCS - CCE falling reference - - 0.1 ps
Write Data Setup Time tWB - BUCK rising reference 0 - -
Write Data Hold Time tWH - BUCK falling reference 0.5 - -
Read Data Access Time tRD - BUCK falling reference 0.4 - 0.5
ACK Data Access Time tBA - BUCK falling reference 0.4 - 0.5
Status Data Disable Time t521 - CCE falling Reference 0.4 - 0.5
Data Disable Time ts22 - -aStatus output - - 0.1
(a)Write command mode
(ps-com output)
tCB tBLw tBHw
BUCK --, _
tWB tvetwis
BUSO~3
Command Data
(TC9296AF output)
IEEJ t521 tBA
BUSO--3
N Status / ACK
OFF mode Write command mode OFF
1997-08-27 11/14
TOSHIBA TC9296AF
(b) Read command mode
(p-com output)
tca tBLw l tBHw
BUCK -_ / N
tWB _ WH
BUSO-2
(TC9296AF output)
tcs tsz1 tRD tBA
BUSO-3 ( ) < ( j (
h Status ( RO Parity
OFF mode Read command mode OFF
(c) Idle mode
(y-com output)
CC_E_\ )/—
BUSO-3
(TC9296AF output)
tcs tszz
use 3 X Status y
OFF Idle mode OFF
1997-08-27 12/14
TOSHIBA
APPLICATION CIRCUIT EXAMPLE-1 (+ 5V single power supply used)
345v -c
16.9344MHELC
'ii-Tal-C
TC9296AF
16.9344MH1=
GNDA D-t Q-C) GND9 Ll+ D-
LO H LI Vcc D-
- - tn - h l
VDDX LO D-C Ll LO D- 10:1F_1 :c Ana og OUT
XI TC9296AFVDA D 'FCGND” NC D JF',
- TA2009F 47m
xo RO x-C GND13 W D- + -
GNDX RO E RO D- 10? _1kQ c'-lcch Analog OUT
GNDA D-t RI GND D-t Ji?
x-C) GND16 A RI+ D-
ANALOG FILTER IC
APPLICATION CIRCUIT EXAMPLE-2 " 5V two power supply used)
tVCC gr
4 . a F
l:|+: s:
GNDAD-t F-o-w 33pF x 18:2;
LO D-e3:.la)/je,-o.., tt, 18kQ 8 H: Jka L-ch Analog OUT
- 56pF 18pF Ct,','; "'
LOO I w] _ 18m (32 c-aL.
VDDX 33kg 33PF 3 ii; gt
VDA j')'-'',?';'
XI TC9296AF -
GNDX R0 IL
GNDA b)
f7”: lkQ R-ch Analog OUT
Ti-AAC-"''-
(Cautions)
It Quality of crystal oscillation wave form largely affect S/N ratio and noise distortion.
Further, this is also true then system clock is input externally through the XI terminal.
0 The wiring between the TC9296AF output and the TA2009F input must be made the
shortest.
o The condenser between VDD and GND shall be connected as close to the pin as possible.
1997-08-27 13/14
TOSHIBA TC9296AF
OUTLINE DRAWING
QFP100-P-1420-0.65 Unit : mm
2.7:0J2
‘ 3.05MAX
0.15zt0.1
01 5 +£1.05
l 1210.2
Weight : 1.69 (Typ.)
1997-08-27 14/14
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