TC9284BF ,CD SINGLE CHIP PROCESSOR WITH BUILT-IN 1BIT DA CONVERTERTC9284BFT(‘Q7RARFv . v IThe TC9284BF is a single chip processor for syncseparation protection/synch ..
TC9285P ,INFRARED REMOTE CONTROL RECEIVING LSITC9285PT(‘Q7REPThe TC9285P is an infrared Remote Control signalreceiving LSI is suited for remote c ..
TC9293AF ,SUMMTC9293AF/AFN/ANT(‘Q702AF T(‘Q7QRAFN T(‘Q7QRANEAS MODULATION SYSTEM DA CONVERTER WITH ANALOG FILTERT ..
TC9293F ,Summ-Delta Modulation System DA converter with analog filterTC9293F/FN/NT(‘Q7QRF T(‘Q7QRFN T(‘Q7QRMI‘,EAS MODULATION SYSTEM DA CONVERTER WITH ANALOG FILTERTC92 ..
TC9293FN ,Summ-Delta Modulation System DA converter with analog filterTC9293F/FN/NT(‘Q7QRF T(‘Q7QRFN T(‘Q7QRMI‘,EAS MODULATION SYSTEM DA CONVERTER WITH ANALOG FILTERTC92 ..
TC9293FN ,Summ-Delta Modulation System DA converter with analog filterTC9293F/FN/NT(‘Q7QRF T(‘Q7QRFN T(‘Q7QRMI‘,EAS MODULATION SYSTEM DA CONVERTER WITH ANALOG FILTERTC92 ..
TDA7391 ,35W BRIDGE CAR RADIO AMPLIFIERELECTRICAL CHARACTERISTICS (V = 14.4V; R =4Ω, f = 1KHz, T =25°C, unless otherwiseS L ambspecified)S ..
TDA7391PD ,32W BRIDGE CAR RADIO AMPLIFIERFUNCTIONAL DESCRIPTIONPin Function DescriptionThe input stage is a high impedance type also capable ..
TDA7391PD13TR ,32W BRIDGE CAR RADIO AMPLIFIERELECTRICAL CHARACTERISTICS (V = 14.4V; R =4Ω, f = 1KHz, T =25°C, unless otherwiseS L ambspecified)S ..
TDA7393 ,2 X 32W DUAL BRIDGE CAR RADIO AMPLIFIERTDA7393 2 x 32W DUAL BRIDGE CAR RADIO AMPLIFIERHIGH OUTPUT POWER CAPABILITY:2 x 35W max./4Ω2 x 32W ..
TDA7393HS ,2 X 32W DUAL BRIDGE CAR RADIO AMPLIFIERELECTRICAL CHARACTERISTICS (V = 13.2V; f = 1KHz; R = 600Ω;R =4Ω;T =25°C;S g L ambRefer to the appli ..
TDA7394 ,2x30W dual bridge car radio amplifier£7
WaRO)t
fifi4-till'l,1il!ll!li9ll!
ft,8(f)1f0oiiC(o)liul(f)g)
TDA7394
2 x 30W DUAL B ..
TC9284BF
CD SINGLE CHIP PROCESSOR WITH BUILT-IN 1BIT DA CONVERTER
TOSHIBA TC9284BF
TENTATIVE TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9284BIF
CD SINGLE CHIP PROCESSOR WITH BUILT-IN 1BIT DA CONVERTER
The TC9284BF is a single chip processor for sync
separation protection/synchronization, EFM
demodulation, error correction / interpolation,
microcomputer interface, CLV servo a focus tracking servo
in CD player system. And, built-in 1bit DA converter.
In combination with the TA8190F/TA8191F/TA2031F/
TA2035F/TA2065F/TA2077F, which are focus tracking
servo LSI, a CD player system can be composed very
simply.
FEATURES
0 Positive sync pattern detection, sync signal protection and QFP80-P-1420-0.80A
synchronization. Weight : 1.57g (Typ.)
o Built-in EFM demodulation and subcode demodulation circuit.
It Has the correction capacity of single and double corrections for C1 and C2 correcting units,
respectively, using CIRC correction theoretical format.
0 Jitter absorbing capacity of 15 frames.
It Built-in 16K RAM.
0 Built-in digital out circuit.
0 Smooth muting through zero cross detection.
0 Read timing free subcode Q data.
It Built-in data slicer and analog PLL (free-adjustment VCO adopted) circuit.
It Focus/tracking loop gain auto adjusting function incorporated.
o Built-in AFC and APC circuits for disc motor CLV servo.
o Built-in focus tracking servo control circuit.
0 Tracking search control capable of coping with all modes.
It Built-in 1bit DA converter.
Function of DA converter.
(1) Built-in 8-time oversampling digital filter.
(2) Built-in soft mute function.
Built-in microcomputer interface circuit.
Double speed play is possible.
In CMOS structure, high speed and low power dissipation.
80 pin flat package.
1 2001-06-19
TOSHIBA
PIN CONNECTION / BLOCK DIAGRAM
(Top view)
m LPFO
0 PDCNT
o TEOF
b FELZ
3 2VREF
DATA SLICER AD CONVERTER
DETECTION CIRCUIT
CLV SERVO CIRCUIT FOCUS/
TRACKING
SEPARATION
CIRCUIT
ADDRESS
CIRCUIT
DEMODULATION
F-is PLL CIRCUIT
SPDA INTERNAL
STATUS
CORRECTION
CHCK OUTPUT
CIRCUIT
BCK AUDIO OUTPUT
DOUT DIGlTALOUT
CONVERTER
ENERATO
TRACKING
SEARCH
CONTROL
CIRCUIT
CIRCUIT
SERVO STATUS
SIGNAL
GENE RATING
CIRCUIT
CORRECTION
CIRCUIT
16K RAM
CORRECTION
SYSTEM TIMING
GENERATOR
CONTROL
DATA BUS
INTERFACE
SUBCODE
DEMODULATION
TC9284BF
1234567891 111 111
SSISSIQBE‘S‘E‘EESaaaaxmlsafizgaé
a > 2ieMlunMaat2aDDDDNJDrclreVtD-l
k9 u2lugluglagim>0ayttgtntn mo. mmU
r-lr-lr- R
2 2001-06-19
TOSHIBA TC9284BF
PIN FUNCTION
PIN No. SYMBOL I/O FUNCTIONAL DESCRIPTION REMARKS
1 GNDA - Analog grand terminal for DA converter(R channel) -
2 RO 0 R channel data forward output terminal. -
3 AR5 0 R channel data reverse output terminal. -
4 VDA - Analog power supply terminal for DA converter. -
5 co O L channel data reverse output terminal. -
6 LO 0 L channel data forward output terminal. -
7 GNDA - Analog grand terminal for DA converter(L channel) -
8 TEiT3 I Test terminal. Normally, keep at "H" level or open.
9 TEST4 I Test terminal. Normally, keep at "H" level or open. With puII-up resistor
10 'tTerry I Test terminal. Normally, keep at "H" level or open.
Subcode Q data CRC check adjusting result output
11 SBOK 0 terminal. -
The adjusting result is OK at "H" level.
12 VDDD - Digital supply voltage terminal. (+5V) -
13 GNDD - Digital ground terminal. -
"fl BU$SO I/O Egg??? and data sending/receiving input/output 'ttteric',',"),,
17 BUS3 . With puII-up resistor
Command and data sending/receiving chip enable signal
18 Ctr I input terminal.
The bus line becomes active at "L'' level. Schmitt input
19 BUCK I fom.marpd and data sending/receiving clock input
terminal.
20 PFCK 0 Regeneration system frame periodic signal output -
terminal. 7.35kHz
21 Arr I Reset input terminal. With puII-up resistor
The internal system is reset at "L" level.
22 SUBSYC O Subcode sync signal output terminal. -
23 SUBD O Subcode P~W output terminals. -
24 CLCK I Subcode P~W data readout clock input terminal. -
25 VDDD - Digital supply voltage terminal. -
26 GNDD - Digital ground terminal. -
Defect detection signal output terminal. VREF when
27 DFCT O defect is detected. Normally, HiZ. -
28 TEL2 0 Tracking gain adjusting analog switch output terminals -
29 TEL1 VREF or HiZ.
Tracking servo loop low frequency phase compensator
30 TGUL O change-over analog switch output terminal. -
HiZ (gain up) when detecting shock. Normally, VREF-
2001 -06-1 9
TOSHIBA TC9284BF
PIN FUNCTION
PIN No. SYMBOL I/O FUNCTIONAL DESCRIPTION REMARKS
Tracking servo loop middle/high frequency phase
31 TGUH2 compensator change-over analog switch output
0 terminals. -
Hi2 (gain up) when detecting shock. Normally, VREF-
32 TGUH1 TGUH1 is used at normal regeneration and TGUH2 is
used at double speed regeneration.
Tracking actuator kick signal output terminal. Kicks in
33 TKIC O the outer circumferential direction at "H" level and in 3-state output
the inner circumferential direction at "L" level.
Feed servo ON/OFF analog switch output terminals.
34 FMON O Servo on at "HiZ". -
Servo off at "I/REF".
35 TEST1 I Test terminal. Normally, keep at "H" level or open. With pulI-up resistor
Feed motor FWD/BWD feeding control signal output
terminal.
36 FMFB 0 Feed in the outer circumferential direction at "H" level 3-state output
and in the inner circumferential direction at "L" level.
37 TEST I Test terminal. Normally, keep at "H" level or open. With pulI-up resistor
38 DMON O Disf motor driving elrcult gain change-over analog -
switch output terminal.
Disc motor CLV servo AFC signal output terminal.
COMMAND DMFC OUTPUT OPERATION
39 DMFC O DMFK H Motor acceleration 3-state output
DMSV PWM CLV servo ON
DMBK L Motor deceleration
DMOFF VREF CLV servo OFF
40 DMPC 0 Disc motor CLV servo APC signal output terminal. 3-state output
41 2VREF I Double times reference voltage input terminal. (VREFXZ) -
Servo mode indicating signal output terminal.
SEL LD ON/OFF FOCUS SERVO OPERATION
42 SEL o L. OFF OFF LD OFF 3-state output
HiZ ON OFF Focus Search
Normal play, etc.
O 0 Focus Servo ON : FOK)
4 2001-06-19
TOSHIBA TC9284BF
PIN No. SYMBOL I/O FUNCTION DESCRIPTION REMARKS
Focus actuator driving signal output terminal in the
focus search mode.
COMMAND OPERATION
43 FCSI o OUTPUT . 3-state output
FORST H Lens gets for away from disc
FOSET L Lens gets near disc
Others HiZ Other than focus search
Focus actuator driving signal output terminal in the
focus gain adjusting mode.
COMMAND OPERATION
44 FKIC o OUTPUT . 3-state output
FGASR H Lens gets for away from disc
FGASS L Lens gets near disc
Others HiZ Other than focus adjustment
4 FEL2 . . . . .
5 O Fucus agam adjusting analog switch output terminals. -
46 FEL1
47 FEI I Focus error signal input terminal. Analog output
48 TESH I Treckmg error Signal input sample holding analog -
switch input terminal.
Tracking servo operation ON/OFF analog switch
49 TEOF o output terminal. -
VREF when the tracking servo is OFF.
50 SBAD I Sub beam adding signal input terminal. .
. . . . Analog input
51 RFRP I RF ripple signal input terminal.
52 VREF I Reference voltage input terminal. (+2.1V) -
53 RFI I RF signal input terminal. Analog input
54 GNDA - Analog ground terminal. -
55 DTSC2 0 Data slice control EFM signal passive output terminal. -
56 MONIT o Internal signal(EFMO, PLCK, LOCK and MBOV)output -
terminal. Selected by command.
57 DTSC1 0 Data slice control EFM signal negative output terminal. -
58 VDDA - Analog supply voltage terminal. (+5V) -
PDO output control terminal.
59 PDCNT I At "L" level, PDO output is made to HiZ by force. -
60 PDO o Phase error signal output terminal between EFM signal 3-state output
and PLCK.
2001 -06-1 9
TOSHIBA TC9284BF
PIN No. SYMBOL I/O FUNCTIONAL DESCRIPTION REMARKS
TMAX signal output terminal.
Hiz at time of system clock.
TMAX PERIOD TMAX OUTPUT
61 TMAX O Longer than L 3-state output
specified period
Shorter than
specified period HQVREF)
Specified period HiZ
62 LPFN I LPF amplifier inverting input terminal for PLL. -
63 LPFO O LPF amplifier output terminal for PLL. -
64 VCOF I VCO filter terminal. -
65 TESTX I Test terminal. -
- Double speed monitor output terminal.
66 HS o . " " -
Double speed operation at L level.
67 GNDD - Digital ground terminal. -
Processor status signal output terminal.
68 SPDA 0 Correction process judging result, memory buffer -
capacity, etc.
Correction system frame periodic signal output
69 COPS 0 terminal. 7.35kHz. -
Word clock output terminal.
70 WDCK o Normally, 88.2kHz. -
Channel clock output terminal.
71 CHCK 0 Normally, 44.1kHz. -
Bit clock output terminal.
72 BCK o Normally, 1.4112MHz. -
73 AOUT 0 Audio data output terminal. -
Emphasis ON/OFF indication signal output terminal.
74 EMPH O Emphasis ON at "H" level. -
75 DOUT 0 Digital out output terminal. -
76 TEST2 I Test terminal. Normally, keep at "H" level or open. With puII-up resistor
77 VDDX O Oscillator supply voltage terminal. -
78 XI I
Crystal oscillator connecting terminal. [a E ,
79 xo XI x0
80 GNDX Oscillator grand terminal. -
6 2001-06-19
TOSHIBA TC9284BF
MAXIMUM RATINGS (Ta =25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Power Supply Voltage VDD -0.3--6.0 V
Input Voltage VIN -0.3--VDD+0.3 V
Power Dissipation PD 1250 mW
Operating Temperature Topr -35--85 "C
Storage Temperature Tstg - 55~150 "C
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, VDD = 5V, 2VREF =4.2V, VREF =2.1V, Ta =25°C)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Operating Supply Voltage VDD - Ta = -35~85°C 4.5 5.0 5.5 V
. XI=16.9344MHz
Operating Supply Current IDD - In normal mode - 40 70 mA
"H" Level VIH (1) - Whole input terminals except 3.5 - VDD+0-3
"L'' Level V|L(1) BUSO--3, BUCK and ctr 0 - 1.5 V
Input Voltage "H" Level VIH (2) BUSO--3, BUCK, CCE 4.0 - VDD+0.3
"L" Level VIL(2) (Schmitt input) 0 - 1.0
"H" Level 'IH VIH =5V CMOS input terminals - - 1.0
Input Current - except analog input pA
"L" Level h. VIL=0V terminal -1.0 - -
Try State Leak "H" Level ITLH - VIH=5V - - 1.0 A
Current "L" Level ITLL VIL=01/ -1.0 - - /r
" " WDCK, CHCK, BCK,
H Level IOH (1) VOH =4.6V AOUT, DOUT, xo - - -2.0
- VOUT=VDD
"L" Level 'OL(1) VOL=0-4V 2.0 - -
" " SBOK, PFCK, SUBSY_C,
H Level loH (2) VOH = 4.6V SUBD, CLCK, SEL, HS, - - - 0.5
- FCSI, FKIC, PDCNT,
Output "L'' Level IOLQ) VOL=0.4V MONIT, COFS,SPDA 1.0 - -
Current VOUT = V00 mA
" " TKIC, FMFB, DMFC,
H Level IOH (3) l/OH = 3.8V DMPC, TMAX - - - 0.4
" " - VOUT=2VREF
L Level |OL(3) VOL=O.4V 1.0 - -
" " PDO
H Level IOH (4) VOH = 3.8V - - - 1.0
" " - VOUT=2VREF
L Level kor(4) VOL=0.4V 1.0 - -
Analog Switch "H" Level IOFH VIH=5V - - 1.0 A
OFF Current "L" Level IOFL - VIL=0V -1.0 - - ”
7 2001-06-19
TOSHIBA TC9284BF
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
FEL1/2, TEL1/2, FMON,
Analog Switch ON RON (1) TGUL, TGUH1/2, DFCT, - - 0.3 k0
Resistance - TEOF, DMON
RON (2) TESH - - 0.6
RUPm AT't' - 50 -
PulI-up Resistance RUP(2) - TEST, TESTI--5 - 30 - k0
RUP(3) BUS3--0 8 - -
Oscillation Amplifier
Feedback Resistance RN - XI XO between 2 4 6 kfl
Operating Frequency Ratio fop - XI 6 - 28 MHz
Total Harmonic 1kHz sine wave
Distortion + Noise THD + N 1 Full-scale input - - 85 - 80 dB
S/N Ratio S/N 1 90 98 - dB
. 1kHz sine wave
Dynamic Range DR 1 -60di? input conversion 90 95 - dB
Cross-talk CT 1 1kHz 5'“e.wa"e - -95 -85 dB
Full-scale input
TEST CIRCUIT 1 : Application circuit example-it is used.
TC9284BF
LOUT 20kHz DISTORTION
FACTOR
APPLICATION CIRCUIT EXAMPLE-2 ROUT IDEAL LPF GAUGE
.' SHIBASOKU 725C BUILT-IN FILTER
DISTORTION FACTOR GAUGE : SHIBASOKU 725C OR EQUIVALENT
MEASURING ITEM
DISTORTION FACTOR GAUGE
FILTER SETTING A WEIGHT
THD + N, CT
S/N, DR
A WEIGHT : IEC-A OR EQUIVALENT
2001 -06-1 9
TOSHIBA TC9284BF
AC CHARACTERISTICS
(1) Clock system timing
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Clock Pulse "H" Level tHW 18 - -
Width . . . L Level tLW - XI input 18 - - ns
Input Rising Time tr - - 10
Input Falling Time tf - - 10
Transfer Time "H" Level tpHL1 - - 60
- XI M K
(1) "L" Level tpLH1 -9 C - - 60
Transfer Time "H" Level tpHL2 - MCK-9BCK - - 60 ns
(2) L Level tpLH2 - - 60
Transfer Time "H" Level tpHL3 - MCK-9COFS - - 100
(3) "L" Level tpLHs - - 100
Output P/y Time (1) tor1 - MCK, BCK - - 15 ns
Output Falling Time (1) tofl - - 15
O t tRisin Time 2 t - - 40
UTPU ".9 ll (2) or2 - COFS ns
Output Falling Time (2) tof2 - - 40
tr tf tHW th
tor1 totl
tpHL2, 3 tpLH2, 3
BCK, COFS
9 2001-06-19
TOSHIBA TC9284BF
(2) Microcomputer interface timing
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Clock Pulse "H" Level tBHW - BUCK 10 - -
Width (1) "L" Level tBLW 10 - - [us
Clock Pulse " " --.-
H Le el t - CCE 6 - -
Width (2) V CC
Delay Time (1) tCB - CCE-YBUCK - - 6
Delay Time (2) tWB - Command Data-9BUCK 0 - - s
Delay Time (3) tcs - CCE-9Status Output - - 6 ’1
Delay Time (4) tBC - BUCK-RTT? 6 - -
Setup Time (1) tRD - BUCK-aRead Data Output - - 6 s
Setup Time (2) tBA - BUCK-SACK, Each Parity Output - - 6 '
. BUCK-aStatus, ACK,
Hold time (1) t521 - Each Parity Output - - 6
Hold time (2) tszz - CCE-ystatus Output - - 6 pe;
Hold time (3) tWH - BUCK-9Command Data 6 - -
(a)Write command processing mode
(Microcomputer output)
tCB tBLW
tWB tWH ltws
BUSO-3
(TC9284BF
Output) tcs tSZ1 Command Data tBA
BUSO--3
" Status , ACK
OFF Mode Write Command Processing Mode OFF
10 2001-06-19
TOSHIBA
(b)Read command processing mode
(Microcomputer Output)
TC9284BF
tCB tBLW J tBHw tBC
BUCK --) sL)I:-ss
tum tWH I
BUSO-3
(TC9284BF
Output) tcs t$21 _ tRD _ tBA
BUSO--3 V Status y L RO l Parity
OFF Moje Read Command Processing Mode OFF
(c) Idle mode
(Microcomputer Output)
BUSO-3
(TC9284BF
Output) tcs tsz2
BUSO-3 1( Status ,
OFF Idle Mode OFF
(3) Data output timing
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
"H" Le el t - - - 30
Transfer Time " " V PHL BCK-9AOUT, WDCK, CHCK ns
L Level tpLH - - - 30
Output P/y TITne tor - AOUT, WDCK, CHCK - - 15 ns
Output Falling Time tof - - - 15
AOUT X X
CHCK, WDCK tor, tof
tof " tor
_. L _. l.
TOSHIBA
(4) Output timing for subcode P~W
TC9284BF
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Clock Pulse "H" Level tHW - 2 - -
Width "L" Level tLW - 2 - - ps
Setup Time tsup - PFCK-9SUBD 0.4 - - s
Read AccessTime tRAC - CLCK-YSUBD 1.2 - - #
SUBD I P E Q X R
"-tSUP - tRAC
tHW tLW
(5) Output timing for subcode Q
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
"H" Level tpHL - -50 - 200
. PFCK-9SBOK, SUBSYC
Transfer Time "L" Level tpLH - -50 - 200 ns
Output Rising Time tor - - - 40
Output Falling Time tof - SBOK, SUBSYC - - 40 ns
tpHL tpLH
susiir)c_ ¢—
tof u tor
(6) Status signal output timing
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
. "H" Level tHDH - - - 200
H I T WDCK-9SPDA
old 1me "L" Level tHDL - - - 200 ns
Out ut Risin Time t - - - 40
p .g . or SPDA ns
Output Falling Time tof - - - 40
"''-Nss_l-stss_l-sss_l-Ns_l-
SPDA X X
tHDH, tHDL tor, toi
12 2001-06-19
TOSHIBA TC9284BF
(7) Digital out output timing
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
"H" Level t - - - 60
Transfer Time " " pHL MCK-9DOUT ns
L Level tpLH - - - 60
Output RISng T_ir.'le tor - DOUT - - 14 ns
Output Falling Time tof - - - 14
DOUT X
tor, tof tpLH
13 2001-06-19
TOSHIBA
APPLICATION CIRCUIT EXAMPLE-1 (+5V single power supply used)
16.9344MH2|=|
ANALOG FILTER IC
APPLICATION CIRCUIT EXAMPLE-2 (iSV two power supply used)
3_l5v -c
16.9344MHZ =,
XI TC9284BF "t
(Cautions)
q; 2 :5;
r-M-o 33pF
N 18kg
TC9284BF
GNDA D-t it-C) GND9 Ll+ D-
LO H LI Vcc D--
VDDX Fo H F LO D- 10fF_1kQ :ch Analog OUT
XI TC9284BFVDA 331m GND12 NC D (ii!
X0 " t-C) GND1IA2009F VRI D- Af
GNDX RO f),ylfii E R0 D- 10:1F_1k9 c',-1f1 Analog OUT
GNDA D-t RI GND D-t [lg
Q-C GND16 A Rl+ D-
kn L-ch Analog OUT
18kQ s, at “
H 33pF a 'rd, g
- '- M
+ - 1kQ R-ch Analog OUT
0 Quality of crystal oscillation wave form largely affect S/N ratio and noise distortion.
Further, this is also true then system clock is input externally through the XI terminal.
0 The wiring between the TC9284BF output and the TA2009F input must be made the
shortest.
o The condenser between VDD and GND shall be connected as close to the pin as possible.
2001 -06-1 9
TOSHIBA TC9284BF
PACKAGE DIMENSIONS
QFP80-P-1420-0.80A Unit : mm
1 . OTYP
, F :i
3.05MAX
0.2i0.1
l i 1.2i0.2
Weight : 1.57g (Typ.)
15 2001-06-19
TOSHIBA TC9284BF
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
16 2001-06-19
:
www.loq.com
.
