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TC9270FTOSN/a684avaiSUMM-DELTA MODULATION SYSTEM DA CONVERTER WITH A BUILT-IN DIGITAL ATTENUATOR DIGITAL FILTER


TC9270F ,SUMM-DELTA MODULATION SYSTEM DA CONVERTER WITH A BUILT-IN DIGITAL ATTENUATOR DIGITAL FILTERTC927OF/NT(‘Q77nF T(‘Q77nl\lEyAMODULATION SYSTEM DA CONVERTER WITHTC927OF, TC927ON are a 2'nd order ..
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TC9270F
SUMM-DELTA MODULATION SYSTEM DA CONVERTER WITH A BUILT-IN DIGITAL ATTENUATOR DIGITAL FILTER
TOSHIBA
TC9270F/N
TENTATIVE
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9270F,, TC9270N
Z-AMODULATION SYSTEM DA CONVERTER WITH
A BUILT-IN DIGITAL ATTENUATOR DIGITAL FILTER
TC9270F, TC9270N are a 2'nd order 2-n modulation
system 1-bit DA converter with a built-in 8 times over
sampling FIR type digital filter developed for digital
audio equipment.
As the de-empahsis filter has been incorporation, it is
possible to construct small the digital filter-the analog
output unit at a low price.
FEATURES
Built-in 8 times over-sampling FIR type digital filter.
Over sampling ratio(OSR) of 2-n modulation circuit is
384fs or 256fs.
Built-in digital de-emphasis filter.
Permits microcontrollers to attenuate output levels(128
steps) during serial mode.
Simultaneous outputs L-ch and R-ch.
Compatible with double speed operation.
Built-in Digital 0 Detection.
Pin of OSCE can be stopped system clock.
TC9270F
SOP28-P-450-1.27
TC9270N
SDlP28-P-400-1.78
Weight
SOP28-P-450-1.27 : 0.89 (Typ.)
SDlP28-P-400-1.78 : 2.2g (Typ.)
Characteristics of the digital filter and DA converter are as follows.
DIGITAL FILTER
PASS-BAND TRANSIENT STOP-BAND
DIGITAL FILTER RIPPLE BAND WIDTH SUPPRESSION
Standard Operation 8fs 10.003dB 20k--24.1kHz -68dB
Double Speed Operation 4fs i0.05dB 20k-24.1kHz -40dB
DA CONVERTER
OSR NOISE DISTORATION S/N RATIO
Standard Operation 384fs -90dB (TYP) 100dB (TYP)
Double Speed Operation 192fs -87di? (TYP) 98dB (TYP)
o 2 kinds of package, Pin 28 flat package and Pin 28 DIP shrunk package.
TOSHIBA TC9270F/N
PIN CONNECION
p/T; tl V 28 El VDD
RZ E 2 27 El LRCK
TST t 3 26 El BCK
VDA E 4 25 a DATA
RO t 5 24 l FFET
Wy E 6 23 [I OSCE
GNDA t 7 22 , ATT(MUTE)
GNDA E 8 21 l srnFr(Etu2)
Co E 9 20 l LATCH (Et/il)
LO E 10 19 El MCK
VDA t 11 18 l LZ
GNDX t 12 17 l C
XI E13 16 El GNDD
xoE 14 15 El VDX
BLOCK DIAGRAM
ATT SHIFT LATCH
VDD LRCK BCK DATA RESET OSCE (MUTE) (EM2) (W) MCK LZ C GNDD VDX
7 1 1 1
Data input Interface pCON Interface
Digital "0"
Detection
ATT Level
8 Times over sampling Timing
Digital Filter Gen.
Interpolation Filter Interpolation Filter
E-A Modulation E-zl Modulation
Output Output
6 7 8 9 1 11 1
P/T; RZ TEST VDA RO R) GNDA GNDA E) LO VDA GNDX XI xo
2 2001-09-05
TOSHIBA TC9270F/N
DESCRIPTION OF PIN FUNCTIONS
No SYMBOL I/O FUNCTION & OPERATION REMARKS
1 P/ff I Parallel control, serial control, switching pin. Pull-up resistance
2 R2 0 R-ch digital "o" detection output pin.
3 TEST I Test pin. Normally, use at "H". Pull-up resistance
4 VDA - Analog power supply pin.
5 RO o R-ch data forward output pin.
6 W O R-ch data reverse output pin.
7 GNDA - Analog ground pin.
8 GNDA - Analog ground pin.
9 co O L-ch data reverse output pin.
10 LO o L-ch data forward output pin.
11 VDA - Analog power supply pin.
12 GNDX - Crystal oscillator ground Pin.
Crystal oscillator connection pin.
13 XI I Connect to a crystal oscillator, generates needed frequency -giii5l,
14 XO o
for the system. XI X0
15 VDX - Crystal oscillator power supply pin.
16 GNDD - Digtal ground pin.
17 C I Clock Select pin. "L" ; 256fs, "H" ; 384fs. Pull-up resistance
18 L2 0 L-ch digital "0" detection output pin.
19 MCK 0 System clock output pin.
LATCH Serial mode : Data latch signal input pin. .
20 (th7fT) I Parallel mode : De-emphasis filter mode select pin. Pull-up resistance
21 SE I Serial mode : Shift clock input pin. Pull-up resistance
(EM2) Parallel mode : De-emphasis filter mode select pin.
22 ATT I Serial mode : Data input pin. Pull-up resistance
(MUTE) Parallel mode: Soft mute cantrol pin. ("H" Soft mute ON)
23 OSCE I System clock control pin. "L'' : System clock stop Pull-up resistance
24 -kTrirt'f' I Reset pin. "L'' : Reset E-st circuit and ATT data 00(HEX) Pull-up resistance
25 DATA I Audio data input pin.
26 BCK I Bit clock input pin.
27 LRCK I LR clock input pin.
28 VDD - Digital power supply pin.
TOSHIBA TC9270F/N
OPERATION DESCRIPTION FOR EACH BLOCK
1. CRYSTAL OSCILLATION CIRCUIT AND TIMING GENERATOR
Clock required for internal operation can be generated when crystal and capacitors are connected
as shown in FIG.1 So external system clock signal may be applied to the X1 terminal at Pin 13.
However are must be taken in using system clock since the S/N ratio and noise distortion
performance can be greatly affected by Jitter, rise and fall characteristics-etc. of system clock.
->r--i>r-- to internal circuit
I Kh A 2.: Kh
ll?,) 13 14 Ily Q} 'dy
GNDX XI llll l x0 vox MCK OSCE
L; X'tal/ICL CL=22PF
Use crystal with Low CI value and quick response.
FIG.1 Configuration of crystal oscillation circuit
The timing generator generates the timing signal for digital filter, digital attennator, de-emphasis
filter 2-n demodulator circuit.
C (Pin 17) XI INPUT CLOCK
L 256fs
H 384fs
Internal system clock can be stopped by OSCE pin but output of DAC will become unstable.
OSCE (Pin 23) SYSTEM CLOCK
L Stop
H Normal operation
2. DATA INPUT CIRCUIT
Data and LRCK are taken into the shift register at the leading edge of BCK.
As shown in the following timing example, it is necessary to input data and LRCK synchronized
with the falling edge of BCK.
In parallel mode (P/T='Ti''), input data length is fixed to 16 bits.
In serial mode (P/T="L"), input data length can be selected to 16, 18, or 20bits.
4 2001-09-05
TOSHIBA TC927OF/N
1514131211109 8 7 6 5 4 3 2
I111111111111H
1514131211109 8 7 6 5 4 3 2
FIG.2a Example of input timing diagram (16bit Input)
If BCK is 48fs or 64fs, please input DATA as follows.
M L M L
rrrrrrrr S 151413121110 9 8 7 6 5 4 3 2 S _........ S 151413121110 9 8 7 6 5 4 3 2 s
DATA B B B B
FIG.2b Example of input timing diagram (16 bit input)
When BCK=48fs or 64fs.
TOSHIBA TC9270F/N
3. DIGITAL FILTER, DE-EMPHASIS FILTER
Foldover noise component outside the band is removed by the 8 times over-sampling FIR type
digital filter. The construction and basic characteristic of the digital filter are changed by the
standard and double speed operations.
oStandard operation oDouble speed operation
Input data
2X over-sampling
FIR type digital filter
(93taps)
De-emphasis
IIR type digital filter
4X over-sampling
FIR type digital filter
(33taps)
8X over-sampling
Digitally filtered data
Input data
2X over-sampling
FIR type digital filter
(45taps)
De-emphasis
IIR type digital filter
2X over-sampling
FIR type digital filter
(25taps)
4X over-sampling
Digitally filtered data
FIG.3 Construction of digital filter
Table-1 Basic characteristics of digital filter (fs=44.1kHz)
MODE PASS-BAND TRANSIENT STOP-BAND
RIPPLE BAND WIDTH SUPPRESSION
Standard operation i0.003dB 20.0le-24.1kHz -68dB
Double speed operation i0.05dB 20.0k--24.1kHz -40dB
6 2001-09-05
TOSHIBA TC9270F/N
Digital filter frequency characteristics
oStandard operation
0 th08
-20 0.06
ai" a 0.04
l:?. T?
-40 0.02
3 fi 0
F: -60 t
a' a' -0.02
< -8t) < -0.04
-120 -0.1
0 20 40 60 80 100 120 140 160 180 0 2 4 6 8 10 12 14 16 18 20 22 24 26
Frequency (kHz) Frequency (kHz)
FIG4. Fre uenc characteristics FIGS Frequenc characteristics
atop gand) (pass and)
0Double speed operation
-20 0.3
A ,4 (hit
98 5'3
V -40 V 0.1
1: -60 t
a' a' -0.1
< -80 4 -0.2
-120 -05
0 10 20 30 40 50 60 70 80 90 0 2 4 6 8 10 12 14 16 18 20 22 24 26
Frequency (kHz) Frequency (kHz)
FIG6. Frequenc characteristics FIG7. Frequenc characteristics
(stop and) (pass and)
7 2001-09-05
TOSHIBA TC9270F/N
The built-in digital de-emphasis circuit can be set to coup with sampling frequency of 32kHz,
44.1kHz, and 48kHz. The selection is done as shown in the following table.
Table.2 Truth table for de-emphasis filter selection
LATCH (EM1) H H L L
SHIFT (EM2) H L H L
MODE (fs SELECT) 44.1 OFF 48 32 (kHz)
Since the de-emphasis filter is a digital circuit, resistors, capacitors, and analog switches are not
requided. Filter construction is shown below.
|G(Jw)|
Input Data Output Data w
1/T1 1/T2
a0+a1Z" -
Transfer function =-' l1 . £132,115
1-blz-1 2= ps
FIG.8 Digital De-emphasis filter construction FIG.9 Filter Characteristics
4. INTERPOLATION FILTER AND DITHER CIRCUIT
The interpolation filter linearly interpolates 8fs after the digital filter and over to 16fs in the dither
circuit, DC offset and dither have been added to Data in order to areven noise by the idling
pattern peculiar to E-A Modulation DAC. After adding the dither 384fs is over sampled in sample
and hold circuit.
5. DA CONVERSION CIRCUIT
2 times E-A modulation DA converter for 2 channels (simultaneous output type) is incorporated in
the TC9270F/N. The internal circuit construction is as shown in fig.10.
The conversion time for the bitstream output is 1/384fs. (in 384fs mode)
In case if CD application, fs=44.1kHz
conversion time
Tset = (1 /384 x44.1kHz) = 59.05ns
DATA INPUT - "Z1 l (D l '21 I i Q DATA OUTPUT
T (DA CONVERSION DATA)
FIG.10 E-A Modulation circuit
8 2001-09-05
TOSHIBA TC9270F/N
6. The E-n modulation section is designed to operate at same frequency as the master clock in both
standard and double speed operation.
NOISE POWER (d8)
0 I l t so'ok ' l I IM
FREQUENCY (Hz)
FIG.11 Noise shaping characteristics
7. DATA OUTPUT CIRCUIT
In the data output circuit, the 384fs or 256fs data are added to the data shift by rising and falling
edge of clock. By differentiating these forward signal and the reverse signal in the external analog
circuit, DA conversion of Low distortion factor high S/N ratio be obtained.
bit stream
D Q D _
1bit conversion data Q A
-NVrr-o
CK (XI) . Fr-
D 6 D -
r CK i" CK $_
Analog Output
AAA ho
FIG.12 Data output circuit
9 2001-09-05
TOSHIBA TC9270F/N
8. INTERNAL CONTROL SIGNAL EXPLANATION
Parallel and serial control mode can be selected by the p/T' terminal. The controll functions are
example as follow.
8-1 PARALLEL CONTROL MODE (p/S" PIN = H)
In parallel control mode, Pin 20, 21, 22 are set as follow.
TabIe-3 Terminal name at parallel mode
PIN No. PIN NAME FUNCTION
20 EM1 De-emphasis control signal 1
21 EM2 De-emphasis control signal 2
22 MUTE If set to "H", digital mute for output is ON.
8-2 SERIAL CONTROL MODE (P/§=L .' FOR MICRO PROCESSOR CONTROL USE)
In serial control mode, the TC9270F/N can be controlled by micro processor. The control
function of Pin 20, 21, 22 are as
TabIe-4 Terminal name at serial mode
PIN No. PIN NAME FUNCTION
20 LATCH Data latch for input signal.
21 SHIFT Shift clock signal input terminal
22 ATT Att data input terminal
Latch and att signal are entered to the shift register of the LSI at the rising edge of the shift
signal.
Also, the latch signal should rise after a minimum of 1.5ps of the last data is shifted to the
register.
If the shift pulse is changed while catch is Low, Mis-operation may occur. Latch should be keep at
Low until after D7 is shifted into the register.
LATCH . . . Ct
s A s B ,
SHIFT I t I f I t I t I t I t I t I t
ATT I DO I D1 I D2 I D3 I D4 I D5 I D6 I D7 I
A=more 1.5/15 B=more 1.5/15
FIG.13 Example for serial control mode data
10 2001-09-05
TOSHIBA TC9270F/N
In serial control mode, the control features are as follow.
TabIe-S Serial mode control
SERIAL INPUT DATA CONTROL SIGNAL
D7 0 1 ATO-6 : Attenuation level setting
D6 AT6 0 1 #EML 2 : De-emphasis option set
D5 AT5 EMP - HS : Double speed mode setting
D4 AT4 CHS MODE BITI, 2 : Input data bit select
D3 AT3 MONO - MONO : Stereo/Mono setting
D2 AT2 HS - CHS : Mono mode L/R mode
D0 ATO pEhll1 BITI MODE : Digital filter fs selection
C) Digital attenuator
D7= L is the command for digital attenuator. If can be set to 28 levels as show below.
TabIe-6 Audio output of attenuation DATA
ATTENUATION CONTROL DATA AUDIO OUTPUT
7F (HEX) OdB
7E (HEX) - 0.069dB
01 (HEX) -42.076dB
00 (HEX) - oo
The attenuation value can be calculated from input data as follow :
ATT= 208og (input data /127)dB
Example .' In case of attenuator=7A
ATT= 20tog (122 / 127)dB = - 0.349dB
Digital attention change from OdB to -oo with a slope of 1024s/f
© MONO, CHS
1) MONO is the commend for switching bit stereo and mono mode.
"H"- MONO "L"- STEREO
2) CHS selects the left or right channel in MONO mode.
"H"- R channel "L"- Left channel
(Note) : In parallel mode, both MONO and CHS are set to "L" an correspond to stereo mode.
11 2001-09-05
TOSHIBA TC9270F/N
Table-7 Mono, CHS control feature
MONO CHS CONTROL FEATURE
L H Stereo mode
H L Left channel
H H mono
Right channel
(3) MODE, EMP, PEMI, PEM2
These control the fs selection and coefficient selection for De-emphasis filter.
Table-8 De-emphasis filter and digital filter coefficient setting
MODE EMP PEM1 PEM2 DIG. FILTER COEFFICIENT DE-EMPHASIS COEFFICIENT
O 0 44.1 kHz 44.1 kHz
0 - O 1 44.1kHz OFF
1 0 44.1kHz 48 kHz
1 1 44.1kHz 32 kHz
0 0 44.1kHz OFF
1 0 0 1 44.1kHz OFF
1 0 48 kHz OFF
1 1 32 kHz OFF
0 0 44.1kHz 44.1 kHz
1 1 0 1 44.1kHz OFF
1 0 48 kHz 48 kHz
1 1 32 kHz 32 kHz
HS is for selecting normal speed mode and double speed mode.
"H" Double speed mode "L" - Normal In parallel mode it is fixed to "L" normal speed mode.
S) BITL BIT2
These are for selecting input data length.
Table-9 Input data length settings
BITI BIT2 INPUT DATA LENGTH
L - 16
12 2001-09-05
TOSHIBA TC927OF/N
9. ZERO DETECT FUNCTION
This device has a built-in input data digital zero detection function. If zero data is continued for
over (215/fs)sec "LZ" and "RZ" Pin become "H".
LRCK I R I L I R I L I R I L I R I L R I L I R I L I R I
normal normal norrTial normal . normal normal normal norma norma
DATA Izero data Izero data Izero data Izero data I data data data data data data data data I data I
*Normal data : It's audio data excepting for Zero data.
FIG.14 Zero detect cancel timing
10.RESET FUNCTION
The internal circuit can be reset by setting reset bit to "L".
In reset mode, outputs are as follow.
LO, 1.5 both fixed at "L"
RO, "kR5" both fixed at "H"
Output timing at reset is as follows.
XI -l I I I I l I I I l l I I I I I I I I-
RESET 1
LO, RO 1 bit 1 bit 1 bit 1 bit
DA OUTPUT DA OUTPUT DA OUTPUT DA OUTPUT
m E 1 bit 1 bit 1 bit 1 bit
_ DA OUTPUT DA OUTPUT DA OUTPUT DA OUTPUT
FIG.15 Reset and output relationship
The clock signal (XI input) is required for resetting internal circuit and output when setting reset to
13 2001-09-05
TOSHIBA TC9270F/N
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
VDD - 0.3--6.0 V
Power Supply Voltage VDA -0.3--6.0 V
VDX - 0.3--6.0 V
Input Voltage Vin -0.r-VDD+0.3 v
. . . TC927OF : 600
Power Dissipation PD TC9270N: 800 mW
Operating Temperature Top, - 35--85 "C
Storage Temperature Tstg - 55--150 ''C
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta = 25°C, VDD = VDX = VDA = 5V)
DC CHARACTERISTICS
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN TYP. MAX UNIT
VDD 4.5 5.0 5.5
Power Supply Voltage VDX - Ta= -35--85oc 4.5 5.0 5.5 V
VDA 4.5 5.0 5.5
Power Dissipation IDD - XI=16.9MHz - 30 40 mA
"H"Level VIH VDDXO.7 - VDD
Input Voltage "L"Level VIL - 0.0 - vDDx0.3 V
"H"Level IIH
Input Current "L"Level 'IL - -1.0 - 1.0 pA
1, 3,17, 20, 21, 22, 23,
. Pin 24
PuII-up Resiso RUP - Ta=25°C, at 0V force 100 150 300 k0
measure current.
AC CHARACTERISTICS (*) : Ta = 25°C
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN TYP. MAX UNIT
Noise Distortion (*) THD+ N 1 1kHz Sine wave, full-scale input - -90 -85 dB
S/N Ratio (*) S/N 1 95 100 - dB
1kHz Sine wave
. * ' -
Dynamic Range ( ) DR 1 -60 Input Conversion 90 95 dB
Cross-talk (*) CT 1 1kHz Sine wave, full-scale input - -95 -90 dB
Operating Frequency fop, - 10 16.9344 19.2 MHz
In ut Fre uenc fLR LRCK duty cycle=50% 30 44.1 100 kHz
p q y fBCK BCK duty cycle = 50% 0.96 1.4112 6.2 MHz
Rise Time tr 0 tl - - 15 ns
Fall Time tf - LRCK, BCK(10% 90%) - - 15 ns
Delay Time td - BCKlEdge -9 LRCK, DATA - 50 - 50 ns
14 2001-09-05
TOSHIBA TC9270F/N
It TEST CIRCUIT-l ; Application Circuit Example 1 is used.
DATA LchOUT1 20 kHz DISTORTION
S G BCK Application Circuit Example-1 FACTORL
LRCK RchOUTI IDEAL LPF GAUGE
SG : ANRITSU MG-22A or equivalent
LPF .' SHIBASOKU 725C BiuIt-In Filter
Distortion Factor Gauge : SHIBASOKU 725C or equivalent
Distortion factor gauge
filter setting A weight
THD + N, CT OFF
S/N, DR ON
Measuring Item
A weight : IEC-A or equivalent
0 AC CHARACTERISTIC POINT; (Input signal; LRCK, BCIC DATA)
10% 90%
50% 90% 10v
BCK _/_\_/_\ / N °/_\_- ....... -
50% tf tr
DATA , X - ..... -
LRCK --)ll p'"
15 2001-09-05
TOSHIBA TC9270F/N
APPLICATION CIRCUIT
pF ciirs- 24k!)
Cl 68pF
18k9. 35km ILL
u. LL U- Cl I g
. 1 In .. tX r',, l to
. '-. a 2 N . Cl La Ln
XI ' E: 3; co -vdifi:, L-ch OUT
a 18kQ 36kQ cu l” 10/IF 1m
EMPH : _ ”L
Ps NDA "-t
CD Pla er - 18kQ 36km . c: LL 1 F 1k
1 chi yroccesor tTt RO n- LL 5: if, fg Op n R-ch OUT
p p U . 2k "e. C N ur "'"rf
TC9263F I- cr" F x g
N _ so
BCK 2:: 24kQ
CHCK - 68pF
16 2001-09-05
TOSHIBA
PACKAGE DIMENSIONS
SOP28-P-450-1.27
2i'pppcpopppppp1i'----,----
8 8:0 2
1 1.8:03
j? "ynluuuloojj,
0.995TYP - T 0.43:0.1 j5lolysliif _
1.27 _ _
L 19.0MAX
18.5Hh2
Weight : 0.8g (Typ.)
TC9270F/N
Unit : mm
(450mil)
I I 1.0i0.2
TOSHIBA TC9270F/N
PACKAGE DIMENSIONS
SDIP28-P-400-1.78 Unit : mm
28 15 "i
J""''1r-1rOC''lf-ll-1l-1r-1f-1i-lr-nFTr-1I-'l O
3) 3 g
l-It-JI-lL-llc-JL-lL-dt-ICJ/lr-lr-IL:
26.1MAX
25.6K0.2
“a r'?-
-a- m.
1 .243TYP 04610.1
Weight : 2.29 (Typ.)
18 2001-09-05
TOSHIBA TC9270F/N
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
19 2001-09-05
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