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TC9240
AUDIO LCD DRIVER IC
TOSHIBA TC9240F
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC9240F
AUDIO LCD DRIVER IC
The TC9240F is a driver IC designed for exclusive use for
output expansion LCD which is controlled by serial data.
FEATURES
0 1/2 or 1/3 duty and 1/2 or 1/3 bias can be switched.
0 Max. 124 segments can be displayed in the 1/2 duty
mode and 186 segments in the 1/3 duty mode.
o Built-in display synchronizing circuit enables display in
multi-chip configuration.
o Built-in oscillation circuit with externally connected QFP80-P-1420-0.80A
capacitor and resistor. Weight . 1 57g (Typ.)
0 Connected to the controller using the tree-wire system.
0 Display data split in 3 segment blocks enables efficient data transfer.
PIN CONNECTION
O T" o trt co Ps u, m
k.) I go 1.0 m in m m m Ln m to in in a E D U U U 0 L9 U U o © o o o O U U U 0 Q 0 o o
F- 0 Lu Ltd LLI Ltd LU LU LLI LIJ Ud LIJ LU LU LU LU LU LU LU LU LLI UJ Ud UJ
U) U V1 V3 v, U3 V3 V3 m V5 V1 V5 U1 U5 V1 v, v, VT V3 V5 U3 V1 V1 V)
-rLrLrLrLrLrLrLrLrLrLrLrLCLrLrLrLrLrLrLrLrLrLrLri,
s4 63 62 6160 59 58 57 56 55 54 53 52 5150 49 48 47 4s 45 44 43 42 41 N
CE 65 40 SEG39
DATA-IN 66 39 SEG38
CK 67 38 SEG37
OSC 68 37 SEG36
SEL 69 36 SEG35
2/3 70 35 SEG34
Cr 71 M SEG33
E 72 TOP VIEW 33 SEG32
VDD 73 (QFP-80PIN) 32 SEG31
VLC1 74 31 SEG30
VLC2 75 30 SEG29
Wm 76 29 SEG28
GND 77 28 SEG27
COM1 78 27 SEG26
COM2 79 26 SEG25
com 80 25 SEG24
k 1 2 3 4 5 6 7 8 9 1011 12 13 141516171819 20 21 22 23 24 A
Ctr-tNitrous/sabotage-tNm.;'?.'",'';:).-?:.',
u7u700000000e-e-r-r-r-r-eer-r-rNtNtNtN
ugtuugugugugrslugrslruu2Wu2u2u7u?u2u?u?u?u?u2u2u7
"but/UBI/uh/uh/tual.".".""'."":":)":"'")",
V9V9V9V9V9V3L0V7V7V9V7V9V9V9
980508EBA2
O TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can
malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing
TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss
of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent products specifications Also, please keep in mind the precautions and conditions set forth in the
TOSHIBA Semiconductor Reliability Handbook.
1998-05-15 1/10
TOSHIBA
BLOCK DIAGRAM
SEGO SE61 _................ SEGGO SEG61
62bit OUTPUT DRIVER
62 CH DATA SELECTOR
186bit DATA LATCH
**_%_OE
TC9240F
C) GND
DATA tiD- 72 STAGE SHIFT-REGISTER
OSC CISCSSIT 1/4 I 1/2 or 1/3 - COM2
I I I TIMING
SEL - - I GENERATION C0M3
SYNCHRONOUS CIRCUIT - CIRCUIT COM-OUT
' N...,'
SY-NC 2 / 3 VLC1 Vch VLc3
PIN DESCRIPTION
2) SYMBOL PIN NAME DESCRIPTION REMARKS
73 VDD Power Supply Pin .
77 GND GND Pin Power Supply Pin (5V_0.5V)
L,- -1- V
1 SEGO LCD segment drive output pins -flT-'LC1
Segment Output Pin 1/2 or 1/3 dety can be switched. o . I
62 SEG61 1/2 or 1/3 bias _ B]
VLC3 Fl
_.....-.... . . VDD
72 BL Blanking Input Pin All 'le?/,1"_rrlt',',,a,,re, put Ih the-blenkmg
state when L level signal IS input. RUP
71 CT Lamp Test Input Pin All seg-ments light when L level
signal IS input.
980508EBA2'
O The products described in this document are subject to foreign exchange and foreign trade laws.
0 The information contained herein is presented only as a guide for the ap lications of our products. No responsibility is assumed by TOSHIBA
CORPORATION for any infringements of intellectual property or other rights D the third parties which may result from its use. No license is granted
b implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
O T e information contained herein is subject to change without notice.
1998-05-15 2/10
TOSHIBA TC9240F
2) SYMBOL PIN NAME DESCRIPTION REMARKS
. . Display data input pins
E h I I P .
65 C C 'p Se ect nput m Input data becomes valid only when
. CE = "H".
66 DATA Data In ut Pin o-Wo-
p Display data is input synchronizing with _
. f CK clock Schmitt
67 CK Clock Input Pin rise o .
When CE = "H" changes to CE = "L",
data is latched and display is updated.
This pin serves as an oscillator when a VDD
capacitor and a resistor are connected '-
68 OSC Oscillation Pin externally.
Master Input
In the slave mode, COM-OUT output
from the master IC is input to this pin. lave Input
Master/slave switching input when VDD
Master/Slave "P". than 2 pieces of this IC are used
69 SEL Switchin Pin simultaneously.
g "H" = Master Mode
"L'' =Slave Mode
Synchronizing input/output pin when VDD
more than 2 pieces of this IC are used
64 SYNC Synchronous Pin simultaneously. -
Master Mode Synchronous output '-
Slave Mode Synchronous input
1/2 or 1/3 duty switching input
70 2/3 Duty Switching Pin "H" =1/2 duty mode cr-f
"L" =1/3 duty mode
74 VLC1 LCD drive voltage input pins
75 VLC2 Bias Input Pin Set input voltage to -
76 VLC3 VDD2VLc1c2VLc22VLC32GND
78 COMI l _._
Common pin drive output ._+:ELLC1
79 COM2 Common Output Pin In the 1/2 duty mode, COM3 pin is o-. I
used in the open state. _ m
80 COM3 V ?,thch
Synchronizing clock output pin VDD
63 COM-OUT Common'Clock Supplies clock to the OSC pm of the
Output Pin slave IC.
fCOM = fosc/ 4[Hz]
1998-05-15 3/10
TOSHIBA TC9240F
DESCRIPTION OF OPERATION
1. Data Input Format
It Display data are input at the following timings:
(LSB) " (MSB)
DATA / D0 X D1 X D2 X D3 X cm-ay on-ly Dn)\
(Display) (OLD)
>(Display)
0 For data length, 48 bits (D0~D47) are transferred 3 times in the 1/2 duty mode and 72
bits (D0--D71) 3 times in the 1/3 duty mode
0 3 bits (last 3 bits) from MSB side of data are address data.
(D45--D47 in the 1/2 duty mode, while D69--D71 in the 1/3 duty mode.)
0 Data in the 1/2 duty mode (2/3="H")
COM1 system data : D0, D2, Da- (Do+2n) ) n=0--61
COM2 system data : D1, D3, Dr- (D1+2n)
Address data : "100" =SEGO--SEG20
"010" = SEG21--SEG41
"001" =SEG42--SEG61
0 Data in the 1/3 duty mode (2/3="L")
COM1 system data : D0, D3, Dir- (Do+3n)
COM2 system data : D1, D4, D7--- (D1+3n) () n=0--61
COM3 system data : D2, D5, Dty- (D2+3n)
Address data : "100" =SEGO--SEG20
"010" = SEG2HSEG41
"001" = SEG42~SEG61
1998-05-15 4/10
TOSHIBA
TC9240F
1) Data Format at 1/3 Duty (186 Segment)
Data Address
Do D1 Dit D3 D4 Ds "ii D60 D61 D62 DesgDes D69 D70 D71
SOC1 SOC2 soc3 s1c1 SIC? s1c3 " S20C1S20C2 S20C3 i? 1 o o
Do D1 Da D3 D4 D5 T, Dec D61 D62 DesgDes D69 D70 D71
S21C1S21C2S21C3S22C1S22C2S22C3 ,',' S41C1S41C2S41C3 i? o 1 o
Do D1 D2 D3 I; D57 Dss D59 DariiDii8 D69 D70 D71
S42CIS42C2 s42c3 S43C1 tt S61C1S61C2 S61C3 li o o 1
2) Data Format at 1/2 Duty (124 Segment)
Data Address
r--"--,
Do D1 D2 D3 D4 D5 2: D39 D40 D41 D42;;044 D45 D46 D47
SOC1 SOC2 s1c1 s1c2 S2C1 S2C2 tt S19C1S20CIS20C2 iiii 1 o o
Do D1 D2 D3 D4 D5 2 D39 D40 D41 D42;;044 D45 D46 D47
S21C1S21C2S22C1S22C2S23CIS23C2 tt S40C2 S41C1S41C2 25 o 1 o
Do D1 D2 D3 T, D37 D38 D39 D407.044 D45 D46 D47
S42C1S42C2$43C1S43C2 " S60 c2 $61C1 S61C2 il,' o o 1
Note) .y.f : 1 or 0
1998-05-15 5/10
TOSHIBA TC9240F
2. LCD Display Timings
1) 1/2 Duty Mode (2/3="H")
VLc1 -
COM2 C
VLC3 -
fosc/UHzl
SEGn VLc1
SEGn VLc1
(Note) When used in the 1/2 bias, supply bias by connecting VLC2 pin and VLC3 pin.
(This also applies to the 1/3 duty mode.)
0 1/3 Bias Operation 0 1/2 Bias Operation
VLC1 Vch VLC3 VLc1 Vch VLC3
VLCD VLCD
1998-05-15 6/10
TOSHIBA
TC9240F
2) 1/3 Duty Mode (2/3 = "L")
fosc/121Hz]
1998-05-15 7/10
TOSHIBA TC9240F
3. Oscillation Circuit
When a resistor and a capacitor are connected to the OSC pin and
oscillation circuit is composed and common signal is generated.
1/4 division of oscillation frequency becomes common frequency. OSC Circuit
Capacitor (C) and resistor (R) are connected as shown in the right-
side figure and the oscillation frequency is expressed by the
following expression : SEL OSC
foscz1.44/C-R (Ta =25°c, VDD=5V) VDD
For instance, when C=0.012/1F, and R=150kQ, fOSC will be about
800Hz and common frequency will be 200Hz. Use the external R C
resistor at 12--220kn. l
However, there is no restriction for the external capacitor C.
4. In Case of Using More Than 2
When more than 2 TC9240F are used simultaneously, common
frequency is generated using one IC in the master mode.
As a result, the slave mode IC performs the simultaneous operation.
1) Processing of Pins at Simultaneous Operation
PIN NAME PIN No. MASTER MODE IN SLAVE MODE IC
SEL 68 "H" (VDD) Level "L'' (GND) Level
OSC 75 Connect External C&R Connect to Master IC : COM-OUT
W 64 Generate SYNC Output Connect to Master IC : ww:
COM-OUT 63 Connect to Slave IC : OSC Open (unused)
COM1 78
COM2 79 Connect to COM Pin of LCD Open (unused)
COM3 80
2) Example of Application Circuit Synchronizing Operation
LCD PANEL
SEGO--SEG61 COM1 SEGO--SEG61
COM-OUT
To Controller
1998-05-15 8/10
TOSHIBA TC9240F
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage VDD -0.3--7.0 V
Input Voltage VIN -0.3--VDD+0.3 V
Power Dissipation PD 300 mW
Operating Temperature Topr -40-85 "C
Storage Temperature Tstg -65--150 ''C
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, VDD--4.r-5.5V, Ta = -40~85°C)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Operating Supply Voltage VDD - - 4.5 5.0 5.5 V
. f05c=1.2kHz, No load,
Operating Supply Current IDD - VDD=5V - 0.3 1.0 mA
"H" Level VIH . . VDDXO.7 -- VDD
- All m ut Ins V
Input Voltage "L'' Level l/IL p p GND ~ vDon.3
"H" Level 'IH CMOS input pins, VIH =VDD -2 - 2
nput Current "L" Level IIL VDD=5V VIL=GND -2 - 2 [a
. H, W pins, VDD=5V,
Pull up Resistance RUp - Ta = 25°C 50 100 200 k0
SEGO--SEG61 VLC1 = VLC2
R . - . .
Output Segment seg Output pms =1/2VDD 0 6 3 0 kft
Resistance C mm n R COM1~COM3 VLC3 =GND 0 5 3 0
o o COM Output pins VDD = 5V - . .
"H" Level I SYNC, COM-OUT v =4.5v -0.2 -0.8 -
Output OH - Output pins, OH mA
Current "L" Level IOL VDD=5V V0L=0.5V 0.2 1.0 -
Oscillation Frequency fOSC - OSC Pin Operation Frequency - 1.2 50 kHz
Max. Clock Frequency fCK 0 ~ 2.0 MHz
Clock P lse Width t 250 - -
U . I CKW Refer to the timing chart as
Data Set Time tset - 250 - -
. below. ns
Data Hold Time tHOLD 250 - -
CE Pulse Width tCEW 250 - -
CE, CK, DATA TIMING
CE _/ " ‘<_7€ - - -
DATA (
tHOLD tCEw
1998-05-15 9/10
TOSHIBA TC9240F
OUTLINE DRAWING
QFP80-P-1420-0.80A Unit : mm
20.0d:0.2
14.0i0.2
18 8220 3
a LuLuLuu3ugL-JkuL.JmLuL.gu...,.--...-s...v-s...--.--
, P _|
‘ 3.05MAX
0.2iO.1
o.15+-%D5
l I 1 .2i0.2
Weight : 1.57g (Typ.)
1998-05-15 10/10
www.ic-phoenix.com
.
