TC9216P ,HIGH SPEED PLL FOR DTST(‘Q716P T(‘Q717P T(‘Q717F"it'-"""'"' "sit'-"-"""' qNIIt'ttilIm-qMqTC9216P, TC9217P, TC9217F are a ..
TC9216P. ,HIGH SPEED PLL FOR DTST(‘Q716P T(‘Q717P T(‘Q717F"it'-"""'"' "sit'-"-"""' qNIIt'ttilIm-qMqTC9216P, TC9217P, TC9217F are a ..
TC9217P ,HIGH SPEED PLL FOR DTST(‘Q716P T(‘Q717P T(‘Q717F"it'-"""'"' "sit'-"-"""' qNIIt'ttilIm-qMqTC9216P, TC9217P, TC9217F are a ..
TC9223F ,PLL FREQUENCY SYNTHESIZER LSI FOR COMMUNICATION USETC9223P/FT(‘Q772P T(‘Q772FPLL FREQUENCY SYNTHESIZER LSI FOR COMMUNICATION USETC9223P, TC9223F are d ..
TC9227P ,HIGH SPEED PLL WITH BUILT-IN PRESCALERTOSHIBA TC9172AP,TC9227,28PT(‘Q177AP T(‘Q777P T(‘Q77RPTC9172AP, TC9227P and TC9228P are high-speed ..
TC9228P ,HIGH SPEED PLL WITH BUILT-IN PRESCALERTOSHIBA TC9172AP,TC9227,28PT(‘Q177AP T(‘Q777P T(‘Q77RPTC9172AP, TC9227P and TC9228P are high-speed ..
TDA7313N ,DIGITAL CONTROLLED STEREO AUDIO PROCESSORWITH LOUDNESSBLOCK DIAGRAM3/14C11 5.6K R2 C17100nF 2.7nFC9 2.2μF100nF 100nFC14 C15OUT(L) IN(L) LOUD(L) BOUT(L) B ..
TDA7313ND ,DIGITAL CONTROLLED STEREO AUDIO PROCESSORWITH LOUDNESSTDA7313N®DIGITAL CONTROLLED STEREO AUDIO PROCESSORWITH LOUDNESSINPUT MULTIPLEXER:- 3 STEREO INPUTS- ..
TDA7313NDTR ,DIGITAL CONTROLLED STEREO AUDIO PROCESSORWITH LOUDNESSELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10K ,RG = 600Ω, a ..
TDA7314 ,DIGITAL CONTROLLED AUDIO PROCESSOR WITH LOUDNESSELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10K , RG =Ω600 , ..
TDA7315 ,DIGITAL CONTROLLED AUDIO PROCESSOR WITH LOUDNESSTDA7315®DIGITAL CONTROLLED AUDIO PROCESSOR1 STEREO INPUTLOUDNESS FUNCTIONVOLUME CONTROL IN 1.25dB S ..
TDA7315D ,DIGITAL CONTROLLED AUDIO PROCESSOR WITH LOUDNESSTDA7315®DIGITAL CONTROLLED AUDIO PROCESSOR1 STEREO INPUTLOUDNESS FUNCTIONVOLUME CONTROL IN 1.25dB S ..
TC9216P-TC9216P.-TC9217P
HIGH SPEED PLL FOR DTS
TOSHIBA
TC9216P,17P/F
TOSHIBA DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC921 6P, TC921] 7P, TC921 7F
HIGH SPEED PLL FOR DTS
TC9216P, TC9217F, TC9217F are a high speed PLL-LSI with
built-in 2 modulus prescaler. Each function is controlled
through 3 serial bus lines and high performance digital
tuning system can be constituted.
FEATURES
Suitable for DTS of Hi-Fi tuner and car stereo
Built-in prescaler, and it can operate 30--140MHz (2
modulus type) at FM band and 0.5~4OMH2 (2 modulus
type or direct frequency dividing type) at AM band.
Built-in 16bit programmable counter, two parallel outputs
phase comparator, crystal oscillator and reference
counter.
Crystal resonator can be used 4.5MHz or 7.2MHz.
15 kinds of reference frequency can be selected.
(when crystal is used 4.5MHz) (Ref=0.5k, 1k, 2.5k, 3k,
3.125k, 3.90625k, 5k, 6.25k, 7.8125k, 9k, 10k, 12.5k, 25k,
50k, 100kHz)
Frequency measurement (HFCIN, LFCIN) of intermediate
frequency etc. and periodic measurement (SCIN) of low
frequency pilot signal etc. are possible by built-in 16bit
universal type frequency counter.
(Note : TC9216P does not have periodic measurement
function.)
Built-in abundant general purpose input/output terminal
and usable for control radio circuit part.
TC9216P
DIP16-P-300-2.54A
TC9217F
DIP20-P-300-2.54A
TC9217F
SOP20-P-300-1.27
Weight
DIP16-P-300-2.54A : 1.0g (Typ.)
DlP20-P-300-2.54A : 1.4g (Typ.)
SOP20-P-300-1.27 0.48g (Typ.)
All of function controls are performed through 3 serial bus lines.
Operating voltage range
1/DD=5.0k0.5V, and it is CMOS structure.
Package is DlP-16pin (TC9216P) and DIP-20 pin (TC9217F) and SOP-20 pin (TC9217F).
2001 -06-1 9
TOSHIBA
TC9216P,17P/F
PIN CONNECTION
TC9216P
XT E 1 16 l VDD
F E 2 15 l DO2/OT-4
DATA E 3 14 , DOI
CLOCK E 4 13 l GND
PERIOD E 5 12 L] FMIN
OT-1 E 6 11 l AMIN
OT-2 r 7 10 l IIO-6/LFCIN
OT-3 r 8 9 , I/O-S
TOP VIEW
DlP-16pin
TC9217P, TC9217F
XT E 1 20 l VDD
F E 2 19 CI D02
DATA t 3 18 a DOI
CLOCK t 4 17 , GND
PERIOD E 5 16 [I FMlN
OT-l li 6 15 [I AMIN
OT-2 r 7 14 u IIO-9/LFCIN
OT-3 t 8 13 [I I/O-8/HFCIN
OT-4 E 9 12 , I/O-7/SCIN
l/0-5 I110 11 l l/0-6
TOP VIEW
DlP-20 pin, SOP-20 pin
2001 -06-1 9
TOSHIBA TC9216P,17P/F
BLOCK DIAGRAM
VDD GND
FML PSC T it
AMP l "
2 MODULUS 4bit SWALLOW POWER ON
FMIN C 1/2 -H I
PRESCALER COUNTER RESET Tl
FMH HF (t RESET
AMIN O-t> 12bit PROGRAMMABLE COUNTER - 8 T2322: {B001
FM MODE LF 'e,
EC Y-- 5 I-, I 4 _.. 12 t,4
o TRI-STATE DO2
5 REFERENCE COUNTER is) MAX - E8 -t)
U BUFFER (D02 -OT-4)
XT o- a , 15 t
1ms OSC 4 l OT-4
- 24bit REGISTER UNLOCK
i g f l/0-5
DATA F-os 's 2 [E -
C 24bit SHIFT REGISTER fu' g l/O 6
h f £95 _
CLOCK C) (y J,, t _
- ADDRESS 5
DECODER I
24 18 f
PERIOD <>—
I/0-9.LFC
24bit REGISTER 'sl C)cc'iCr'Cl,)
4 ‘éa _ L k4 f I/0-8-HFCIN
's 16bit BINARY COUNTER I T 1/4 \I \>(I/o-5)
_ \GATE
OUTPUT PORT cazzk UNIVERSAL COUNTER CONTROL l I/O 7 SC
4H4 - . IN
I l AMP
OT-4 XT 1ms
(Note) 0 Mark terminals are not existence in TC9216P.
Terminal name of TC9216P is shown in parentheses.
Others are common terminals.
3 2001-06-19
TOSHIBA TC9216P,17P/F
PIN FUNCTION
KILL“ SYMBOL PIN NAME FUNCTION AND OPERATION REMARKS
Crystal resonator of 7.2MHz
1 XT Crystal Oscillator or 4.5-MH2 shall be connected VDD
- Terminal to this terminal to generate -
2 XT reference frequency and XT _T
internal clock.
3 DATA aerial Data Input/ Serial I/O port. .
utput Serial data transfer IS VDD VDD
performed between controller F-
. and these terminals to control C l
4 CLOCK Clock Signal Input universal counter and I/O F
port, and sets frequency
5 PERIOD Period Signal Input dividing nuy?trs and DATA CLOCK, PERIOD
frequency dividing mode.
6 OT-1 These terminals are CMOS
structure and used as output VDD
7 OT-2 of control signal etc.
General Purpose " "
Output Port They are set to L level at j-
8 OT-3 power "ON".
9 (OT-4 of TC9216P can be used
(-) OT-4 by switching D02.)
These terminals are CMOS
10 structure and can be used V
(9) l/O-5 freely as input or output. DD
General Purpose I/O It becomes input port at '-
11 Port power "ON". -
(-) I/O-6 (Exclusive terminal of I/O
port is only I/O-S in
TC9216P.)
This terminal is general
purpose I/O port. It can be VDD
also used as signal input -
General Purpose I/O terminal which performs
12 l/O-7. Port/Universal periodic measurement of low { -
(-) SCIN Counter Periodic frequency signal by program
Measurement Input control.
(Note)lt is set input mode of
I/O port at power
4 2001-06-19
TOSHIBA TC9216P,17P/F
2) SYMBOL PIN NAME FUNCTION AND OPERATION REMARKS
These terminals are general
purpose I/O ports. They can
be also used as input
terminals for frequency
13 I/O-8. measurement of universal
counter by program control. VDD
(-) HFCIN . -
Frequency measurement IS
General Purpose I/O . . . "
. available for intermediate
port/ Universal -
frequency measurement etc. "
Counter Frequency . . . .
It IS with built-in amp. and
l/O-9 . Measurement Input .
14 LFC can operate small amplitude
(10) (I/(IDIEIG- signal with capacitor coupling.
(TC9216P does not have HFCIN
LFCIN) .
input.)
(Note)lt is set input mode of
I/O port at power
15 The local oscillator signal of tt,
(11) AMIN each FM/AM band is input to $013
Programmable these terminals. It is with C) l"
16 Counter Input built-in amp. and can operate Lia:
(12) FMIN small amplitude signal with E'-
capacitor coupling.
These terminals are tristate
18 DOI outputs of phase comparator. VDD
(14) Phase Comparator DOI and D02 are parallel '-
Output (General output. (D02 of TC9216P can
19 (DO2. Purpose Output Port) be also used as general '-
(15) purpose output port by
program control.)
GND Power supply voltage of
( 3) owar Supp y 5.0V* 10% is applied to this -
20 Terminal .
(16) VDD terminal.
(*) No.1--8 pins are common terminals of TC9216P, TC9217P, TC9217F.
(*) Terminal name and number of TC9216P are shown in parentheses.
2001 -06-1 9
TOSHIBA TC9216P,17P/F
OPERATING DESCRIPTION
CD Serial I/O port
Each function is controlled by the data setting to a pair of 24bit registers, total of 48 bits. Each
data of these registers is exchanged with controller side by 3 terminals of DATA, CLOCK and
PERIOD through serial port.
Address 8 bits and data 24 bits, total of 32 bits, are transferred in serial at the same time.
Since all functions are controlled in the unit of register, so here explanations of address 8 bits and
each register function are described chiefly. These registers are constituted in unit of 24 bits and
selected by address of 8 bits. Address assignment table of each register is shown as the allocation
of register in next page.
REGISTER ADDRESS CONSTITUTION OF 24BIT NUMgIER OF
Setting of PLL frequency dividing number. 16
Selection of reference frequency. 4
Input DOH Setting of PLL input and operation mode. 2
Register-1 Selection of crystal oscillation frequency. 1
Out-control OC. 1
(Total of 24)
Control of universal counter (Control of 9
PLL lock detection bit is included.)
In-put D2H Test bit 1
Register-2 I/O port control 5
Output data 9
(Total of 24)
D1H Data of Register-1 24
(OC-- 1) (Mode B) (Total of 24)
Output Count data of universal counter 18
Register D1H PLL lock detection data 2
(CC = 0) Unused 4
(Mode A) (Total of 24)
Data of Register-il 19
[23:3 D3H Input data 5
(Total of 24)
Input data is latched to register-1 or -2 at the fall timing of PERIOD signal and each function is
operated.
Each output data is latched to output register in parallel at the fall timing of the 9th of CLOCK
signal and output from DATA terminal serially. Serial data of DATA, CLOCK and PERIOD is
synchronized with crystal oscillation clock and taken into the internal circuit of LSI. By this reason if
crystal oscillation is stopped, serial data can not be input.
(Note) When power is turned on, some internal circuits have undefined states to set internal
circuit states, execute a dummy data transfer at least once before performing regular data
transfer.
6 2001-06-19
2001 -06-1 9
ALLOCATION OF REGISTER
| l MseI
Address = DOH Po
PIIPZIPB P4 P5
PalP7IPaIP9IP1oIPnIP12 P13
P15 Ro I R1 I R2 I R3 FM IMode osc oc
18351533 mduI
Programmable Counter Data
Crystal Out-
Selectian Control
Reference
Code Data
Programmable
Counter Mode
Address=DZH Go I G1
CMO I cm I CM2
(51") I (9?) I (5?) I(EE) I (53)
(9 II? (J)
(8?) I (8%)
O1I02I03I04
Gate Time
Selection
HFC START
('1) ”C RESETFEST
Counterinput Start Test
Control bit
Counter Mode
Selection
II 0 Port Control
Output Port Data
Address: D1H
and 0C: "0'
foIf1If2
f3If4If5If5 f7|fslf9If1o
1‘11 I M I 1‘13 I fit;
f15 IOVERIBUSY BLE ng,‘ "0" ["0" I "0" "0"
(Mode A)
Universal Counter Data
Lock Detection Data Unused
Address = 03H
TEST (E3, I (SE,
(51) I (E?) I (8%)
01 I 02 I 03 I 04 (13) I (13) (15) I (I3) I (I3)
Go I G1 IcmoIcnvn Icmz
SC HFC . .
('2) (*2) ”C I 0
"w.tiirti )ndmo
Gate Time
Selection
Counter Mode Unused Test
Selection
Counter Input
Control
| I 0 Port Control
Output Port Data IIO Port Input Data
"' Usually 0C: "1"
Address: D1H
and 0C: "1'
Po I P1 I P2 I P3 P4 P5 P5
P7IP8IP9IP10
P11 IP12 P13
FM IMode osc oc*
P15 RolR1lR2|R3
(Mode 8)
Programmable Counter Data
At POWER 0N RESET operation, each data of input register is set as shown below.
Address=DOH I *4
*4 I 14
I4 I '4 R4 I ’4 .4
Crystal Out-
Selection Control
Reference
Code Data
Programmable
Counter Mode
I I MSBI
'4|*4|*4|‘4I*4|*4l'4I’4l‘4l‘4I‘4I*4lII1I°I°|
Address = DZH
"tsr.iiat, 1ndu|
|°|°I°I°l°|°|°
I°|°I°|°
o|ooooo
(Note) *1 : Don’t care in TC9216P.
*2 : Data is set to "D" in TC9216P.
*3 : Bit name of TC9216P is shown in parentheses.
*4 : don’t care
*5 : TEST bit is set to ”0".
1021 6P.TC921 7P] F - 7
TOSHIBA
TC9216P,17P/F
TOSHIBA TC9216P,17P/F
O Serial transmission format
Period signal should be changed to "I"
START during this period for start timing.
PERIOD t2 t2 / t2 t1 t1
/ The 9th of the fall timing
CLOCK tii-h-u-u-u-u-u-if-ii-of"-"-')]-
DATA |%7/// MSB f,",i,s'9ii,e - //%W
Address 8 bits Data 24 bits
Min. 0 Serial transmission format consists of address 8 bits and data 24 bits as mentioned
t1: 1.0ps above. Address of DOH--D3H is used in this LSI.
t2 2 0.3ps
C) Crystal resonator connecting terminal (XT, W)
It can generate the clock signal necessary for inside operation of LSI by connecting crystal
resonator and capacitors as shown in Fig.1.
Crystal resonator can be selected either 4.5MHz or 7.2MH2.
Serial Data "OSC" bit should be set to "o" at 4.5MH2 selection.
Serial Data "OSC" bit should be set to "I" at 7.2MHz selection.
-tyx: DIVIDER
C; X'tal y C=30pFTyp.
8 2001-06-19
TOSHIBA
C) Programmable counter
Programmable counter part consists of 1/2 prescaler, 2 modulus prescaler and 4 bits + 12 bits
programmable binary counter.
1. Setting of programmable counter
16 bits data of frequency dividing number and 2 bits of frequency dividing mode is set to
programmable counter.
Setting of frequency dividing mode
TC9216P,17P/F
Input terminal and frequency dividing mode (pulse swallow mode or direct frequency
dividing mode) shall be selected by FM and MODE bit.
Since 4 kinds of modes are prepared as shown below, so it shall be selected according
to the frequency band used.
FRE UENCY DIVIDING EXAMPLE OF INPUT INPUT FREQUENCY
MODE MODE FM Q MODE RECEIVING FREQUENCY TERMINAL DIVIDING
BAND RANGE NUMBER
LF 0 o :2: frequency dividing LW, MW, SWL 0.5-- 10MH2 AMIN n
HF 1 0 SW... 2-- 40MHz AMIN n
FML o 1 Pulse swallow mode FM 30-- 140MHz FMIN n
FMH 1 1 1/2 + pulse swallow mode FM 50-- 140MHz FMIN Tn
(Note) n represents programmed numeral value.
(2) Setting of frequency dividing number
Frequency dividing number of programmable counter is set to PO~P15 bits in binary.
It Pulse swallow mode (16 bits)
P14 P13 P12 P11 P10
P9 P8 P7
P6 P5 P4
Setting range of frequency dividing number (Pulse swallow mode) : n =210H--FFFFH
(528-65535)
(Note)
1/2 + pulse swallow mode.
0 Direct frequency dividing mode (12 bits)
Actual dividing number becomes the double of programmed numeral value in
P14 P13 P12 P11 P10
P9 P8 P7
P133";
Unrelated
Setting range of frequency dividing number (Direct frequency dividing mode) :
n =10H-- FFFH (16--4095)
Data of P0~P3 is unrelated and P4 bit becomes LSB at direct frequency dividing mode.
2001 -06-1 9
TOSHIBA TC9216P,17P/F
2. Circuit construction of prescaler and programmable counter
Circuit construction at pulse swallow mode
P0--P3
_ PSC l-l
, -------------------------.------ "I 4bit SWALLOW CONTER J
l FMH l
FMIN C 1/2 I
I 2 MODULUS I PRESET
: PRESCALER l
l l 12bit PROGRAMMABLE COUNTER TO PHASE
I I COMPARATOR
L -_-_--_---_----_------ .1
PRESCALER UNIT Pp-pls
It consists of 2 modulus prescaler, 4bit swallow counter and 12bit programmable
counter. 1/2 prescaler is added to the front stage of 2 modulus prescaler at FMIN
(FMH mode).
Circuit construction at direct frequency dividing mode
PRESET
AIVIIN 12bit PROGRAMMABLE COUNTER TO PAHASE COMPARATOR
Pp-pls
Prescaler unit becomes unused at direct frequency dividing mode and 12bit
programmable counter is only used.
Each input of FMIN/AMIN has built-in amp. and can operate small amplitude signal
with capacitor coupling.
10 2001-06-19
TOSHIBA TC9216P,17P/F
C) Reference divider (Frequency divider for reference frequency)
Reference divider unit consists of crystal oscillator and counter. Crystal resonator can be selected
either 4.5MHz or 7.2MHz and 15 kinds (max.) of reference frequencies are generated.
1. Setting of reference frequency
Reference frequency is setting by R0~R3 bits.
R3 R2 R1 R0 REFERENCE FREQUENCY R3 R2 R1 R0 REFERENCE FREQUENCY
0 0 0 0 0.5kHz 1 0 0 0 .)if7.8125KHz
0 0 0 1 1kHz 1 0 0 1 9kHz
0 O 1 0 2.5kHz 1 0 1 0 10kHz
0 0 1 1 3kHz 1 0 1 1 12.5kHz
0 1 0 0 3.125kHz 1 1 0 0 25kHz
0 1 0 1 .)if3.90625KHz 1 1 0 1 50kHz
0 1 1 0 5kHz 1 1 1 0 100kHz
0 1 1 1 6.25kHz 1 1 1 1 -
.yd. Mark frequencies are only available at 4.5MHz crystal resonator used.
Crystal oscillation frequency is selected by crystal select bit (OSC).
OSC=''0" ...... 4.5MHz
OSC="1" ...... 7.2MHz
(Note) OSC bit is set "0" (4.5MHz) when power supply is "ON".
11 2001-06-19
TOSHIBA TC9216P,17P/F
C) Phase comparator
Phase comparator compares reference frequency signal supplied from reference frequency divider
and programmable counter frequency dividing output. It outputs the observational error and
controls VCO through low-pass filter to make frequency and phase difference between these two
signals accord.
Filter constant can be designed suitably for every band of FM/AM because Tri-state buffer DOI
and D02 terminals are output from phase comparator in parallel.
REFERENCE FREQUENCY SIGNAL
PHASE . DOI A FM
PROGRAMMABLE s COMPARATOR . T VCO
COUNTER OUTPUT
L.P.F Vcc
TO VARICAP OF VCO
R_!|_!|_!|_!l_
sinnrn raw
DO " 'i------,--'--)-..,,
HIGH LEVEL
LOW LEVEL FL0ATING STANDARD EXAMPLE OF LOW-PASS FILTER
Tr1 : 25C1815 CONSTANT
Tr2 : 2SK246 (REFERENCE VALUES AT FM BAND)
C=0.33,uF
R1 =10kQ
R2 --8.2kQ
R3 =3300
RL=10kQ
DO Output Timing Chart Example of Active Low-Pass Filter Circuit
DO output timing chart and an example of active Iow-pass filter circuit through the darlington
connection of FET and transistor are shown in the above diagram.
Besides, the filter circuit shown in the above diagram is one of example for reference and so,
an actual circuit shall be examined and designed according to the receiving band constitution of
the system and required characteristics.
(Note) D02 terminal of TC9216P can be switched and used as OT-4 terminal by program
control.
12 2001-06-19
TOSHIBA TC9216P,17P/F
C) Unlock detection bit
This bit is to detect the lock condition of PLL system. Phase error pulses are output to unlock
F/F from phase comparator at timing of reference frequency period in the PLL unlocked state,
that is, when reference frequency does not accord with programmable counter frequency
dividing output (unlock condition). The unlock F/F is set by these pulses. And whenever START/
RESET bit (unlock reset bit) of register-il is set to "I", unlock F/F is reset. Lock condition can be
detected by access of unlock detection bit after resetting the unlock F/F. It is necessary to access
the unlock detection bit (UNLOCK) after having a time more than reference period after
resetting the unlock F/F because error pulses are input at reference period. If this time was
shorter, the correct lock condition can not be detected. Therefore, the test enable F/F is
provided.
This F/F is reset whenever unlock reset bit is set to "I", and it is set to "1" at the unlock
detection timing. That is, the unlock condition can be detected correctly when this test enable
bit (ENABLE) is set to "I''.
REFERENCE FREQUENCY
PROG RAMMABLE COUNTER OUTPUT
-___ _____L.
DO OUTPUT I I U
PHASE ERROR
LOCK DETECTION STROBE
EXECUTION OF UNLOCK RESET
UNLOCK DETECTION bit
TEST ENABLE bit
13 2001-06-19
TOSHIBA TC9216P,17P/F
C) Universal frequency counter
Universal frequency counter is used as frequency calculation of FM/AM band intermediate
frequency (IF) for auto stop signal detection at auto search tuning, etc.
Two types of measurement mode are available by use of universal counter. One is the frequency
measurement mode (HFCIN, LFCIN Input) that counts the input pulses enter the universal counter
in a constant time (gate-time), and the other is the period measurement mode (SClN Input) that
counts the reference clock pulses (period measurement pulses) enter the universal counter in a
period of the input pulses. Measurement mode is selected according to the frequency measured.
but in TC9216P SCIN, HFCIN inputs are not provided and period measurement mode is not
available. Besides, each terminal can be also used as I/O port.
1. Universal counter control bit
C) Go, G1 bit ................. Gate-time of universal counter is selected by these bits.
G1 Git GATE-TIME PERIOD MEASUREMENT PULSE
0 0 1ms 50k(20ps)
0 1 4ms 150k (6.6ps)
1 0 16ms 900k (1.1/15)
1 1 Manual * Crystal oscillator frequency
* Gate-time can be set freely in the manual mode by using time base of controller. (The
gate-time less than 2 cycles of serial transmission format can not be set because it is
controlled by START bit)
© START bit ................. Measurement starts whenever START bit is set to "I".
(Note) In manual mode the count starts when START bit is set to
START is set to "O".
and stops when
(3) CM0, CM1, CM2 bit ........ Each measurement mode of universal counter and input
terminal are selected by these bits. Besides, it also controls
the switching of DO2/OT-4 function in TC9216P.
CM CM CM TC9216P TC9217P'TC9217F
2 1 o $111111?” COUNTER MODE $911111 mimitrm COUNTER MODE
0 0 0 LFCIN LFC Mode D02 LFCIN LFC Mode
0 0 1 LFCIN LFC Mode D02 LFCIN LFC Mode
0 1 0 * * * HFCIN MFC Mode
0 1 1 * * * HFCIN HFC Mode
1 o o LFCIN LFC Mode OT-4 * *
1 o 1 LFCIN LFC Mode OT-4 * *
1 1 o * * * * *
1 1 1 * * * SCIN SC Mode
* : Don't use
14 2001-06-19
TOSHIBA TC9216P,17P/F
MODE INPUT FREQUENCY RANGE
LFC Mode Fre uenc FIN=0.3-- 15MHz
MFC Mode lf/j/ar/ue,':,,',',,,,, FIN-- r- 20MHz
HFC Mode FIN--- r- 60MHz
SC Mode Period Measurement FIN-- --100kHz
(Note) 1/4-prescaler is added to the front stage of the universal counter (16 bits binary
counter) in HFC mode. Therefore, signal input to HFCIN is divided by 4 in the
prescaler and transmitted to the universal counter.
(io LFC, HFC, SC bit ....... Input terminals of universal counter are controlled by these bits.
Switching between universal counter input and I/O port are
controlled by these bits.
DATA TC9217P-TC9217F TC9216P
0 HO Port (I/O-9) l/O Port (l/O-ti)
LFC Frequency Counter Input Frequency Counter Input
(LFCIN) (LFCIN)
0 I/O Port (I/O-8)
HFC Frequency Counter Input
(HFCIN)
0 I/O Port (I/O-7)
SC Period Measurement Input
(SCIN)
Unprepared
2. Universal counter data output register
(D Universal counter calculation data bits (fo~f15)
The calculated result in the universal counter can be read out from output registers of
fir-f15 in binary. In this case, OC bit of input register-1 should be set to "o".
© Universal counter operational detection bit
o OVER .... Universal counter "I'' ... Universal counter over flow condition
over flow bit I . . .
o" Universal counter data normal condition
It BUSY ..... Universal counter I "I" ... Under universal counter calculation
0 eration " . .
p . . 0 Universal counter calculation end
monitor bit
(Note) Refer to the contents of universal counter calculation data bits (fo--f15) after
confirmation of BUSY bit="0" (END of calculation) and OVER bit="0" (Data normal
condtion) at the use of universal counter.
15 2001-06-19
TOSHIBA TC9216P,17P/F
3. Circuit construction of universal counter
Universal counter unit consists of input amp., gate-time control circuit and 16bit binary
counter.
CM0 CM1 CM2
I l I fo-f15 OVER
HFCIN I
16bit BINARY COUNTER OVER FLOW
DETECTOR
LFCIN 4f
PERIOD MEASUREMENT GATE
PULSE - fXT
SCIN GATE-TIME CONTROL CIRCUIT
(CMOS INPUT) l t 1
SC LFC HFC START G0 G2 BUSY
4. Measurement timing of universal counter
PERIOD ENj PERIOD Ci
T1 . T1 -
SET START BIT TO "1" SET START BIT TO "1"
HFClN - -
OR SCIN INPUT J L L
LFCIN l l
BUSY BUSY
BIT - - BIT - -
GATE GATE
I I BINARY I I
BINARY
COUNTER COUNTER
INPUT INPUT
INPUT MEASUREMENT CLOCK PULSE REFERENCE CLOCK PULSE
Frequency Measurement Timing Chart Period Measurement Timing Chart
0
(Note) HFCIN and LFCIN are with built-in amp. and can operate small amplitude signal with
capacitor coupling.
(Note) SCIN signal should be used with logic level because its input is CMOS structure.
(note) Calculation at manual mode is started at rise timing of PERIOD signal end (START bit is
set to "1") and is also finished at the same timing (START bit is set to "0").
16 2001-06-19
TOSHIBA TC9216P,17P/F
C) General purpose input/output port
It has general purpose l/O port controlled through serial port.
. INPUT/OUTPUT
INPUT/OUTPUT TC9217F TC9217F TC9216P CONSTRUCTION
Output Port Exclusive : 4 Exclusive : 3, (Max. :4) CMOS
I/O Port Exclusive : 2, (Max. : 5) Exclusive : 1, (Max. :2) CMOS
General purpose output port (OT-1~OT-4)
The data set to 01--04 bits of input register-il is output in parallel from each exclusive
output port OT-1--OT-4 terminal. TC9216P does not have OT-4 exclusive output port but D02
terminal can be switched and used as OT-4 output port by that CM1 bit is set to "0" and
CM2 bit is set to "I" in input register-2 respectively.
. General purpose I/O port (|/O-5~|/O-9)
Input or output mode of I/O port is set according to the contents of C5--C9 bits in input
register-2.
Set each bit of cr-cg to "o" at input mode setting.
The data input from UO-r- |/O-9 terminals in parallel can be read out from DATA terminal
as serial data of Ir-lg.
Input data is latched to the internal register at the fall timing of the 9th of serial clock.
Set each bit of cr-cg to "I" at output mode setting. The data set to Or-og bits of input
register-it is output from I/O port of l/O-r-l/O-g terminal in parallel respectively.
(Note) Since l/O-r- I/O-9 terminal of TC9217F and I/O-6 of TC9216P are also combined
with input terminal of universal counter, each bit of SC, HFC and LFC of input
register-2 shall be set to "o" at the use of I/O port.
(Note) l/O control port and output port are set to "o" at power "ON".
(General purpose I/O port is set to input mode. General purpose I/O port terminals
combined with universal counter inputs are set to input mode of I/O port and
output condition of general purpose output port is set to "L" level.)
17 2001-06-19
TOSHIBA TC9216P,17P/F
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage VDD -0.3--6.0 V
Input Voltage VIN -0.3--VDD+0.3 V
Power Dissipation PD 300 mW
Operating Temperature Topr -40-85 "C
Storage Temperature Tstg - 65-150 °C
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta = -4tr-85oc, 1/DD=4.5--5.5V)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Operating Power Supply
Voltage VDD 4.5 5.0 5.5 V
Operating Power Supply VDD=5.0V, XT=7.2MHz,
Current IDD - FMIN=140MHz - 15 25 mA
(Operating frequency range)
Crystal Oscillation fXT - Connect crystal resonator to 4.0 - 8.0 MHz
Frequency XT-RT' terminal
FMIN (FMH, FML) fFM - FMH, FML mode, V|N=0.3Vp_p 50 _ 140 MHz
FMIN (FML) fFML - FML mode, VIN =0.4Vp-p 30 .''- 140 MHz
AMIN (HF) fHF - HF mode V|N=0.3Vp-p 2 - 40 MHz
AMIN (LF) fLF - LF mode V|N=0.3Vp_p 0.5 '.'- 10 MHz
LFCIN (LFC) fLFc - LFC mode VIN =0.31/p-p 0.3 - 15 MHz
HFCIN (MFC) fMFc - MFC mode le=0.3vp_p 5 _ 20 MHz
HFCIN (HFC) fHFC - HFC mode VIN --0.3Up-p 5 .''- 60 MHz
VIH =VDDXO.7,
SCIN fsc - V|L=VDDXO.3, - -- 100 kHz
Square wave input
(Operating input amplitude range)
FMH, FML mode ' VDD
FMIN (FMH, FML) l/FM - fIN = 50~140MH2 0.3 -0.5 Vp-p
FMIN (FML) VFML - FML mode hN=30--140MHz 0.4 _ Y3? Vp-p
AMIN (HF) VHF - HF mode hN=2--40MHz 0.3 - 1’ng Vp-p
AMIN (LF) VLF - LF mode f|N=0.5~10MHz 0.3 - YB? Vp-p
LFCIN (LFC) VLFC - LFC mode f|N=0.3~15MHz 0.3 .''- Y3? Vp-p
HFCIN (MFC) VMFC - MFC mode hN=5--20MHz 0.3 -- Y3? Vp-p
HFCIN (HFC) VHFC - HFC mode hN=5--60MHz 0.3 -- Y3? Vp-p
18 2001-06-19
TOSHIBA
TC9216P,17P/F
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta = -40--85''C, VDD-- 5V)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
(OT-1~OT-4)
Output "H" Level IOH 1 - VOH=4.0V -2.0 -4.0 - mA
Current "L" Level IOL 1 - VOL=1.0V 2.0 4.0 -
(DATA, CLOCK, PERIOD, I/O-r-l/O-g)
" " VDD
H Level VIH - - x0.7 VDD
Input Voltage VDD V
"LII L I V - - '
eve IL 0 x0.3
"H" Level IIH - VIH =5V - - 2.0
Input Current "L'' Level IIL - VIL=01/ - - -2.0 PA
" " VOH = 4.0V, Except CLOCK,
H Le el I - -2.0 -4.0 -
Output V OH 4 PERIOD mA
Current " " VOL-- 1.0V, Except CLOCK,
L Level IOL 4 - PERIOD 2.0 4.0 -
(D01, D02)
Output "H" Level IOH 3 - VOH=4.0V -2.0 -4.0 - mA
Current "L'' Level IOL 3 - V0L=1.0V 2.0 4.0 -
DO Tri-State Leakage
Current ITL - VTLH = 5V, VTLL = 0V - - :1 PA
(5t"r)
Output "H" Level '0H 2 - VOH=4.0V -0.1 -0.3 - mA
Current "L" Level IOL 2 - VOL=1.0V 0.1 0.3 -
(Input feedback resistance) * Note : Ta=25°C
FMINI AMINI LFCIN, HFCIN,
Input Feedback Resistance RH - SCIN 250 500 1000 Q
sz - XT-WT 250 500 1250
19 2001-06-19
TOSHIBA TC9216P,17P/F
PACKAGE DIMENSIONS
DIP16-P-300-2.54A Unit : mm
[-1r'-'e1r-nF'--'1i-1l-1ei'-1
6.4:t0.2
V'-''-''''-'''-''
19.75MAX
19.25i0.2
03:51:01
0.735TYP . . i l 0.5i0.1_30'25 (ii)
Weight : 1.0g (Typ.)
20 2001-06-19
TOSHIBA TC9216P,17P/F
PACKAGE DIMENSIONS
DlP20-P-300-2.54A Unit : mm
0—01 5°
Y'"---''--'''-'''''',-?
25.1 MAX
24.6:02 d
3.13:0.3
0.87TYP
Weight : 1.49 (Typ.)
21 2001-06-19
TOSHIBA
PACKAGE DIMENSIONS
SOP20-P-300-1.27
'ihiiripas/s1r------r--""
: 5.3:02
7 3:0 3
lrlhrlrleljljljrL___.._...a._,
0.685TYP =
13.3MAX
0.4 i0.1 *
Weight : 0.48g (Typ.)
ti?, E
tip-dr."
T"",, 1-
TC9216P,17P/F
Unit : mm
(300mil)
(3-15—0255
-. I 0.23:0.2
2001 -06-1 9
TOSHIBA TC9216P,17P/F
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
23 2001-06-19
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