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TC9149TOSHIBAN/a700avaiFor Infrared Ray Remote Control Receiver
TC9149TOSN/a2750avaiFor Infrared Ray Remote Control Receiver
TC9149N/a60avaiFor Infrared Ray Remote Control Receiver
TC9149PTCN/a21avaiFor Infrared Ray Remote Control Receiver
TC9150PN/a19275avaiFor Infrared Ray Remote Control Receiver


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TC9149-TC9149P-TC9150P
For Infrared Ray Remote Control Receiver
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FOR INFRARED RAY REMOTE CONTROL RECEIVER Unit in mm ,'
The IC9149P/TC9150P is LSI designed for use on the 16 9 .,.''"
infrared ray remote control receiver, and when this 1 f
LSI is used in combination with LSI T091481) for trans- a
'.JO-'k-a"EaaG..l%HL-I
mitter, the remote control system can be constructed.
The TC91.k9P is DIP 16 PIN type and is capable of
199m E 7.621025
controlling 10 functions, while the TC9150P is DIP E
24 PIN type and ls capable of controlling 18 functions. l, t
_ I/ l
. -Able to output parallely multiple keying signals a 0~15,
sent from the transmitter i,'', t15d:t11t5 +01
. M I [Luau .uzs-uos
(The TC9149P ls able to output parallely up to
5 functions, while the TC9150P is able to output Lead pitch Its B.51 tttul t;o1ortutee 15 '
1:025 against theoretical center of i
parallely up to 6 functions.) . each lead. that is obtained on the
. basis of No.1 and No.16 leads.
. Output for single pulse, hold pulse and cyclic JEDEC _
pulse are provided. TOSHIBA 3D16A-P
(Cyclic pulse ls available only for TC9150P.) . i
Unit in mm ,
. A single terminal type oscillator by means of
CR is provided. _
. Code detection circuit provided for code check 3
with the transmitter prevents Interferences from Q
various types of machines and apparatus. ussuuuuuuwu H ,
_ _ 5 550m 1'li' 1524::125 ,
_ , . . _ d -l
MAXIMUM RATINGS (Ta=25°c) . _ _ _ . fl J'
CHARACTERISTIC SYMBOL RATING UNIT 'g (151015 2difctt2ti +0: 15°
Supply Voltage VDD 0m 6 V ‘4 1.410.215 -f3f..c.lti.
In ut/Out ut Volta e V ll V -0.3'\.v D+0.3 V Lead pitch is 2.54 and tolerance is
p p g IN, OUT SS D 1025 against theoretical center of
each lead that is obtained on the
Power Dissipation PD 200 mw basis of No.24 leads.
Operating Temperature Topr -20'u 75 "c JEDEC -
Storage Temperature Tstg -.55s125 "c TOSHIBA T 6D21A-P
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T‘I‘I-u -
PIN CONNECTIONS
DIP 16 PIN . _ DIP 24 PIN
mm ll ‘ Irma 0ND
RxIN 15 w osc RxIN
HPI t conmz HPI
sz CODE G RPa
RPS 12 w SP1 BPS l
. HPg Spa . E94 r
HPs tWa HPs
BPS " SP4 PEPe ‘
0P1 _ 10
BLOCK DIAGRAM IO
VDD GND SP9
(16) .. (1)
osc osc t
(15) im)---- UP oouuma Cis? “4(6)
I - U _ F, 155(7)
6 PIN NO. OF T091491?
')s't?-- Jllirli/ly'" V snm momma - itil/l, a M ffuflfgliilsg.
I _ I (io? 0P1
INPUT PULSE . F, 6pm
COUNTER LATCH CIRCUIT Cla? SP9
. 1 V Ll, , G] BPB'
082? 22 CODE - CIO, SP7
CODE CHECK Eggg'uou - _ OUTPUT BUFFER Ft 9176
(13) BI _ CF, SP5“)
L Fr," SP4(9)
F/F 9 SP3 (1o)
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ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta=25°C, VDD=5V)
CHARACTERISTIC SYMBOL C&SUTIT TEST CONDITION MIN. TYP. MAX. UNIT
Operating Supply Voltage VDD - TAa--.Q0m75''C 4.5 5.5 ll
Operating Supply Current IDD - Output without Load - - 1.0 mA
Oscillation Frequency fOSC - Ta---20'u75''c,vmr--h.5s5.5v 27 N 57 kHz
Standard OSC Frequency Sfosc - . '- 38 - kHz
Variance of Oscillation _ = q = a
Frequency by VDD Avrosc -. Ta 25 C, VDD 4.54.5.5V -5 - 5 'r,
Variance of Oscillation ',
Frequency by Temperature ATEOSC - Ta=-30ti,75''c -5 - 5 A
II n . - V = - -
Output Current "H. Level I0H all output, 0H 4V - 1.0 mA
L' Level IOL - all output, VOL=1V 1.0 - - mA
Input Current "H" Level IIH - CODE Terminal, VIH=5.0V -1.o - 1.0 PA
Pull-up Resistor Rup - CODE Terminal . 10 20 40 kn
In ut Circuit Threshold
g VogtaLe VIN - Rx Terminal 2.0 2.5 3.0 v
. Hysteresis Width VHIS - Rx Terminal I'- 0.8 - V
DESCRIPTION OF TERMINALS
PIN N0. ' INPUT/OUTPUT'
16 PIN 24 PIN SYMBOL TERMINAL FUNCTION/QPERATION CONFIGURATION
1 1 GND GND
Receiving Instruction signal with carrier
2 2 RxIN signal signal eliminated Is.input. tlr-ata--
','. 3'u7 - HP1NHP5 Continuous As long as receiving signal is
. . signal input, this output is held at
E - 3a8 “leHP6 Input "H" level.
1 Cyclic When receiving signal is Input,
. - 9'10 CP1'CP2 signal output ls reversed. E/F
output .
8 12 - SP SP _ When receiving signal ls input,
m 1'uti, 5 Ite; shot output is placed at "B" level _
_ - 20 only for a fixed time. (about
IIs SP1'usP10 output 107 msec) .
Transmitter code is compared _ -
with a code set at this terminal
13-14 21.22 CODE Code input and if they agree each other,
l input is accepted.
Built-tn pull-up
resistor
Timing A resistor and a capacitor are
I . . parallely connected between
15 23 OSC osc1llat10n this terminal and GND.
16 24 VDD Power Supply
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V -260- L
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FUNCTI ONAL DESCRI PTI ON
1. OSCI LLATI 0N CI RCUIT
Timing with transmitter signal and Internal operating clock are all
decided by this oscillator.
The oscillator has been so far constructed through a combination of a
linear amplifier by means of C MOS inverter in IC and 455 kHz ceramic resonator;
however, when TC9149P/TC9150P is used, a stable oscillator can be constructed
by parallelly connecting C and R between the oscillator and GND by a single
terminal oscillator'.
R l 391:0. 15%,
c .. 1000pF i5%
(POLYPROPYLENE FILM CAPACITOR SHOULD Nil USED.)
Oscillation frequeney ls about 38 KHz:t _ 5 kHz at R=39k9 and C=lOOOpF.
(Refer to Graph 1 [Oscillation Frequency Characteristic)
2. RECEIVING SIGNAL INP.UT CIRCUIT
Signal received by the light receiving element ls sent through
_ the amplifier to the detector where 38 kHz carrier wave is eliminated and is
Input into the receiving signal input circuit. The receiving signal input
circuit (Rx IN) has a built-in Schmitt_ circuit for shaping receiving signal
waveform to eliminate rounding.
AMP. DET.
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3. RECEIVING SIGNAL CHECK
The receiving signal check ls to check l cycle transmitting signal sent
from the transmitter to determine if It ls normal signal.
12 BITS _ 12 BITS
RECEIVING
3mm SiUUUUUUUUUUh_SititftU3TftrTf
l FIRST DATA l I SECOND DATA
First, the first data ls stored in the Ll-tfits shift register.
Then, when the second data ls put into the shift register, data is forced out
of the shift register by one bit, where the first data has been stored.
Nov, pushed out data and incoming data are checked to seeUf they are same.
If an error is caused in the receiving data.12-bits check, the system ls
reset at that point of time. dmversely, when all receiving data are OK,
output ls raised from "I." level to "H" level.
" READER DATA '1' READER DATA '0'
RECEIVING DATA
01841116 I
SHIFT PULSE - - _ l n fl
OHEXIK PULSE ll f
The status of receiving data, shift pulse and eheck pulse ls shown above.
Shift pulse ls provided in the' data center by. taking frequency margins of
the transmitter and the receiver into consideration.
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TC9149P
T091 SUP
Code Comparison
To prevent Interference with other models, Cl, C2 and C3 code bits are
provided for checking whether the transmitter and receiver codes agree each
other. _ A
Only when both codes agreed, internal latch strobe pulse ls generated
to latch receiving data and output is raised from "L" level to "H" level. .
If both codes do not agree, no latch strobe pulse is generated and output
remains at "L" level.
Code bits used differ depending upon receiver as shown below:
CODE BIT
T09149P . . . . t32 ,cs com: BIT
T09150P . . . . Cl ,c2 CODE am
* CODE BIT 'o' .'o' CANNOT BE USED.
1 . 03 02
4. INITIALIZATION AT TIME OF POWER Gl
In order to initialize the internal status at time of power ON, it ls
necessary to perform the initialization. _ . '
i The initialization is carried out when a capacitor is connected to'
the code bit terminal.
INITIALIZE
RUP "'20kn Crap.)
t3---0.001MP-0.022pf?
* In case of TC9149P,-eonnect a éapacitor to C2 and C3.
* A capacitor for initialization ls unnecessary for the terminal' for which
Code Bit "0" is selected. However, Code Bit "0". "0" cannot be used.
Either one terminal must be set at "H7.
.-.t---.r"r- -.0'tF..iHr"qr......_r'"r_ wuu-u-uu-wm Mwuw-uln - 1.1 -11. 11.1.1.1 pm...» 1.. - -111 " "_..'"" 1.1... L'1l'iW,',lk'ClrCrL"lll't"u".'d = W...
-11.-111.11 ..n..1 .1111....W—m"...m-=m..11..u..11m1..11..1...1«"11::1'..1..o11m.111.a111.111.-.1 1.11.11.11.41... "t"rAveN.rMe.q""rta.qNretrrqttHt-rer"ttMo."..qro.q"- .1..1.1.11 .11..1..11 111.111.. mm“!!-
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L,..-]'-"- T091 4GP,
T091 50P -
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5. EXPLANATION OF OUTPUT PULSE SP, HP, CP
5-1. SP1 - SPlO (Single pulse)
KEY ON I "
.SINGLE- SHOT " 12 BITS _ I12 BITSI
LATCH, .
snow I
PULSE _
SINOLE- SHOT I I ABOUT 107 maec l
OUTPUT
After checking 12-bies receiving data, if data agree and 0K, single
pulse ls output. T e _ _
Output is raised from "L" level to. "H" level and returned again to
"L" level after about 107 msec.
5-2. HPl - HP6 (Holq pulse)
KEY ON J ") _ I
" BITS 12 BITS . 12 BITS 12 BITS
SINGLE -SHOT I I I I I I I I
LATCH,
STROBE . I
PULSE .r
___-._..
SINGLE - {mom I " F
OUTPUT _ L
. V ABOUT 160 msec
Hold pulse ls output by the first latch strqbe pulse after key ON.
Output is kept at "H" level as long as Continuous Signal is Input.
When the key ls released and continuous signal is stopped, about 160
msec later, output is reversed to "L" level by the last latch strobe pulse.
Further, HPl - HP6 are able to parallelly and simu1taneoi1sly max
sex'tet outputs at "H" level by continuous signal sent from the transmitter.
These outputs are optimum as outputs of REC-PALY, REC-PAUSE, and
CUE/REVIEW of a tape deck.
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5-3. CPI, CP2 (Cyclic pulse)
KEY ON . .
12 BITS 12 BITS ' 12 BITS 12 BITS
LATCH STOROBE V
PULSE I
CYCLIC OUTPUT _ l " I
When single-shot signal Is received, cyclic pulse output is reversed.
This cyclic pulse ls used for power ON/OFF, MUTE, etc.
CODE ALLOCATION (KEY No. is of TC9148P)
KEY DATA B I T
di H try 82 K1 K2 Ka ks ks K6 FUNGTI ON " INSTRUCTION
I 1 o 0 1 o o o o o CONTINUOUS SIGNAL HPI
2 1 o o o 1 o o o o ff BPa
G l o 0 o 0 1 0 D o ff HPs
l 1 o o o o o 1 ' o o u HPI
5 1 o o o o o o 1 o n BPS
6 1 o o o o o o o 1 n Bra
'7 o 1 o 1 o o o o o SINGLESHOT SIGNAL SP1
8 o 1 o o 1 o o 0 o ff BPa
9 o 1 o o o 1 o o o n SP3
1 O 0 1 O o 0 O 1 o o tf BPI
1 1 o 1 o o o o o 1 o ft SP5
12 o 1 o o o o o o 1 " SP6
1 3 o o 1 1 o o o T o o 1/ SP7
1 l o o 1 o 1 o o o o ,, spa
15 o o 1 o o 1 o o o u BP9
1 6 o o 1 o o o 1 o o ff arm
17 o o 1 o o o o' 1 o oycmc SIGNAL CPI
1 e o o 1 o o o o o 1 n CP2
Cl - C3 code bits are available in addition to the above data bits for
optional code sélection. _
TC9150P can use all keys, but TC9149P is able to use KEqu.5 and KEY7s11
only for 10 commands.
TOSHIBA, 'iii?iiiiiiiiir: DE i,')-,';':';'.] “103724? 3018053 Ll
T09149P t.V;TrTr- '.-"_"''Lrt.'h'27T'T-2rrr "'"ic/hh--ti
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7. APPLICATION CIRCUITS
l. RECEIVING SECTION
y, I . ' trvay--ov
'sN tttt
mmwsx TA7344P ' d
05 0 Run
O 0 IL DATA
M2lK1itl8AWY000.,Ltd
fo-381rHs'
1d(4-6)-154#H
ZSKJ'IOOR ZSA1015GR ISISBBXZ
2. TC9149P CIRCUIT
VDD 0R CONTROL SIGNAL . Ta(1-3)-1'r.6mrl
L5(1-2)=16£mH
4-6=43t
3-1‘6001:
3-2=--103t;
ZUEW‘0.08¢
T091491“
RxIN HPI 2 3
3. TC9150P CIRCUIT INrDT CONTROL SIGNAL
VDD GR _ couTkOL SIGNAL
3 l 5 6 '7 8
T09150P
3 t 5 6 cpchlsplog
_ . Rx , v
l INPUT CONTROL SIGNAL
* R should be 38ka , 5%.
* C should be polypropylene film capacitor having good temperature
characteristics 1000 pF'iSZ. T
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T69150P
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NOTE FOR APPLICATION CIRCUIT
1. COMBINATION OF TC9148P/Tc9149p CODE BITS.
(EXAMPLE 1) TN CASE coma: 02:1 AND 03:0
(TABLE 1)
TC9168P T091491)
c c c c - - I
1 2 G a CODE T3 TI (com: c1=1.
0 (03) (02) (G1) cz=1. 03:0)
1 T091482?
if,7, 030 d '6
DD 2 3 (CODE 02::1 '
T09119P
The combination of code bits of TC9148P and TC9149P is shown in
Table 1 ,
; To make Code Bit to ''1" on TC9148P, connect diodes to CODE terminal
- from TI'vT3 Terminals. To set Code Bit at "0", open the circuit.
TC9149P hes C2 and C3 code terminals. Code bit of Cl has been pulied
up in IC and Cl ls always kept at "i" status.
Therefore, on Transmitter TC9148P it ls necessary to keep Cl code bit
at "1". _ .
Example 1 ls the external circuit diagram when Code Bit C2=1, and C3=0.
2. COMBINATION OF TC9148P/50P CODE BITS
(TABLE. 2)
T09148P T09150P
Cl C2 08 Cl
-'..B"' "
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TCQ150P
(EXAMPLE 2 ) IN CASE CODE 0 =1 and 0 =0
CODE 2 1
(ca) Coz) (cl)
Tt391ityp
(CODE cl=1,cz=o ,bsui)
(00m: cl=1 ,02-=o)
The combination of Code Bits of TC9148P and TC9150P is shown in
Table 2 .
0n TC9150P, C3 code has been pulled up in IC and always kept at "1"
E - status. Therefore, it ls necessary to keep Code Bit C3 of Transmitter
_'' TC9148P at "I". To keep Code Bit C3 at "1", connect a diode to CODE
Terminal from T3 Terminal.
Example 2 ls an example of the circuit when Code Bit Cl=l and C2=0.
3. If input voltage above VDD + 0.3V may possibly be applied to Rx Input
Terminal (2 PIN), connect resistors of about 10k0 in series to Rx Input
Terminal. (This is to prevent latch-up.)
_ 10kn
RECEIVING SIGNAL ---vvw--C 2pin Rx
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T09149Pi’
TCPP50P_
OSCILLATI 0N FREQUENCY CflAllACTERiST1 CS
fosc - C
VDD=5V
g - n=s9 m.
Pt N, T
g 40 "s,. g
a so . w
700 900 1100 1300
fosc - R
VDD=5V
a N c 000p
a 50 'N.
'i Vi 's t
to " . _ .
E -' '% ty,
g _', 's. 77
A . "cl,
26 34 " 50
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COUNTER
SAUDID DIGITAL "3:rs,rsr,

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