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TDA6800 ,Video modulator circuit
TC90A17F
PAP / PIP / POP Controller for NTCS / PAL Wide RV
TOSHIBA TC90A17F
TENTATIVE TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC90A1 7F
PAP/PIP/POP CONTROLLER FOR NTCS/PAL WIDE TV
The TC90A17F is a PAP (picture and picture)/PlP/POP
control IC with built in ADC and DAC. The control IC can
be used for NTSC/PAL by combining with field memory
and video signal processing IC. This IC is equipped with
various display screen functions and is most suitable as a --------"'ssss,
wide TV additional function controller. _-------""
FEATURES
It Incorporates two 8bit A/D converters, three 8bit D/A
converters, a clamping circuit, and a multiplexer into a
single chip.
0 External field memory and broadcast method QFP100-P-1420-0.65A
2M bit mode : For NTSC only Weight : 1.6g (Typ.)
4M bit mode : For NTSC/PAL
0 Display screen functions
. PAP display : Display on 1/2 of the 16 : 9 screen
(Animation mode and still mode can be set.)
. PIP display : 4 : 3 or 16 : 9 (Animation mode and still mode can be set.)
. POP display : 4 : 3 (The following modes can be set ; 3 screen still mode, 2 screen still
mode with only 1 screen animation mode, and strobe mode)
. Multiple still images : Up to 24 still images can be displayed on one screen by overlapping.
. Channel search : 9 screen search or 12 screen search
(Still mode, strobe mode, and 1 screen animation mode can be set.)
A half screen or a full screen can be displayed.
. Variable setting for frame width and frame color
For frame color, 8 bits are available to indicate brightness ; R-Y or B-Y
can be set in high-order 4 bits. The setting without frame is possible.
OSD function
Built-in horizontal and vertical filters
Micro controller interface : IZC bus
+3.3V single power supply
Package : QFP100-pin
1 2001-06-19
2001 -06-1 9
BLOCK DIAGRAM
(NO NEED ON ZBIT MODE)
2M MEMORY I
(M5M51V8221) g
m OUT .
2M MEMORY i
(M5M51vazz1) E
IN OUT 5
(CHARACTER RAM (256Wx128lT)x2) 6/
(CODE RAM
"“1"” ...... ;
050 8 a
“W“ (30065 3 (3
WDAY WMCK RMCK RDA RMCKI RDAC
7~o WRST 7~o 7~o
WE NY #3)“
r ---------------- - RRST
F—--___-_- ____
Y (2M1Y/C)
AID YIC
DISTRIBUTION
: 3 YIIQ :
v. : :
__ AID MATCHING
FILTER
_______.___J
SUB PICTURE
ODD I EVEN
WHREF C
MAIN PICTURE
u---------d
LINE MEMORV D/A
3 YOUT
a RDER ENERATOR
(512Wx163l‘r) 0 G
O IOUT
3 QOUT
OUTPUT
4M MODE I 2M MODE
WRITE CLOCK
GENERATOR
RHREF C
SELECTION
WRITE SECTION
DECODER
SERIAL CONTROL SIGNAL
DISPLAY MODE
3 TESTO
3 PWRST
SWITCHING SIGNAL
READ CLOCK
GENERATOR
MEMORY RELATED
SIGNAL
READ SECTION
DECODER
—. SERIAL CONTROL SIGNAL
TC90A17F - 2
TOSHIBA
TC90A17F
TOSHIBA TC90A17F
TERMINAL CONNECTION DIAGRAM
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Cr>-cyr-Cy2e>tir-r-r-r-r-r-->7us5
.@®@®®@®®@®®®@@®@®@@
TC90A17F
3:23:22
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WDAYO C
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3 2001-06-19
TC9OA17F
TOSHIBA
‘b - :ll. lVOGDJ.
lanED 11d
:HHHM )DM HunDld
:IVOLZIVJ. "35
CDA ans
:IL LV063.L
dVd/dOd/dld 111:;
Z. (W2)
lZZEA L SWSW
)DINB 5A
1V8 LVOGDL
dSHHH )0! 'DS VGS GAE 0H8
NIO Nll
woa-fi’
.LIODUD 11d
NHZZZ lVl .LnOO
(DA NIVW
.Lndan
‘05 V05
WVXBVIO ~)|3018
WELSAS
TOSHIBA TC90A17F
TERMINAL FUNCTIONS (QFP 100pin)
Kl"? PIN NAME I/O FUNCTION CONDITION
1 DAVDD - DAC VDD 3.3Vk0.3
2 VB1 I DAC Bias
3 DAVSS - DAC l/SS
4 VB2 I DAC Bias
5 ADVSS - ADC VSS
6 VRTY - ADC Y signal reference input (TOP)
7 VRBY - ADC Y signal reference input (BOTTOM)
8 YIN I ADC Y signal input
9 CLMPY - ADC Y signal clamp
10 BIAS - ADC Bias
11 ADVDD - ADC VDD
12 VRTC - ADC Chroma signal reference (TOP)
13 VRBC - ADC Chroma signal reference (BOTTOM)
14 IIN I ADC I signal or R-Y signal input
15 CLMPC - Chroma signal clamp
16 QIN I ADC Q signal or B-Y signal input
17 ADVSS - ADC I/SS
18 VDD - Digital VDD 3.3Vi0.3
19 l/SS - Digital I/SS
20 MOH 0 Memory related signal output enable
21 WVD I Subscreen vertical synchronous signal output (Bus can handle polarity)
22 WHD I Subscreen horizontal synchronous signal output (Bus can handle polarity)
23 VDD - Digital VDD 3.3Vi0.3
24 WCK I Subscreen system clock input
25 WHREF C) Subscreen PLL phase comparison output
26 vss - Digital I/SS
27 WMCK 0 Field memory write clock output
28 VDD - Digital VDD 3.3Vi0.3
29 WIE 0 Field memory input enable
30 WENC o Field memory color write enable 2M mode : open
31 WENY 0 Field memory intensity write enable (.2M mode, for Y and C
signals)
32 WRST C) Field memory write reset
33 WDAC7 O C signal output (Field memory write signal/MSB) 2M mode : open
34 WDAC6 O C signal output (Field memory write signal) 2M mode : open
35 WDAC5 O C signal output (Field memory write signal) 2M mode : open
36 WDAC4 O C signal output (Field memory write signal) 2M mode : open
37 WDAC3 O C signal output (Field memory write signal) 2M mode : open
38 WDAC2 O C signal output (Field memory write signal) 2M mode : open
39 WDAC1 O C signal output (Field memory write signal) 2M mode : open
40 WDACO O C signal output (Field memory write signal/LSB) 2M mode : open
5 2001-06-19
TOSHIBA TC90A17F
my PIN NAME I/O FUNCTION CONDITION
41 I/SS - Digital I/SS
42 WDAY7 O Y signal output (Field memory write signal/MSB)
43 WDAY6 O Y signal output (Field memory write signal)
44 WDAYS O Y signal output (Field memory write signal)
45 WDAY4 O Y signal output (Field memory write signal)
46 WDAY3 O Y signal output (Field memory write signal)
47 WDAY2 C) Y signal output (Field memory write signal)
48 WDAY1 O Y signal output (Field memory write signal)
49 WDAYO O Y signal output (Field memory write signal/LSB)
50 VDD - Digital VDD 3.3Vi0.3
51 RDACO I C signal input (Field memory read signal/LSB) 2M mode : Fixed to L
52 RDAC1 I C signal input (Field memory read signal) 2M mode : Fixed to L
53 RDAC2 I C signal input (Field memory read signal) 2M mode : Fixed to L
54 RDAC3 I C signal input (Field memory read signal) 2M mode : Fixed to L
55 RDAC4 I C signal input (Field memory read signal) 2M mode : Fixed to L
56 RDAC5 I C signal input (Field memory read signal) 2M mode : Fixed to L
57 RDAC6 I C signal input (Field memory read signal) 2M mode : Fixed to L
58 RDAC7 I C signal input (Field memory read signal/MSB) 2M mode : Fixed to L
59 RDAYO I Y signal input (Field memory read signal/LSB)
60 RDAY1 I Y signal input (Field memory read signal)
61 RDAY2 I Y signal input (Field memory read signal)
62 RDAY3 I Y signal input (Field memory read signal)
63 RDAY4 I Y signal input (Field memory read signal)
64 RDAY5 I Y signal input (Field memory read signal)
65 RDAY6 I Y signal input (Field memory read signal)
66 RDAY7 I Y signal input (Field memory read signal/MSB)
67 REN 0 Field memory read enable
68 RRST 0 Field memory read reset
69 RMCK 0 Filed memory read clock output
70 RMCKI I RMCK input (phase matching)
71 YS 0 Main screen/subscreen switching timing signal
output
72 OSD1 O OSD character signal output
73 OSD2 O OSD character color Ys signal output
74 Vss - Digital I/SS
75 RHREF 0 Main screen PLL phase comparison output
76 RCK I Main screen system clock input
77 VDD - Digital VDD 3.3Vi0.3
78 RHD I Main screen horizontal synchronous signal input (Bus can handle polarity)
79 RVD I Main screen vertical synchronous signal input (Bus can handle polarity)
80 SDMON O IZC ilt.JS acknowledgement output/standard
checking signal for micron controller 5V
6 2001-06-19
TOSHIBA TC90A17F
Em PIN NAME I/O FUNCTION CONDITION
81 VDD - Digital VDD 3.3Vi03
82 SCL I " BUS serial clock input
83 SDA I/O " BUS serial data input/acknowledgement output
84 I/SS - Digital I/SS
85 IICNR I " BUS noise removal circuit (ON (H)/OFF (L))
86 TEST4 I Fixed to L
87 TEST3 I Fixed to L
88 TEST2 I Fixed to L
89 TEST1 I Fixed to L
90 TESTO I L : 4M mode, H : 2M mode
91 TIMRST I Fixed to L
92 PWRST I System reset input L : Reset
93 vss - Digital I/SS
94 NC1 -
95 DAVSS - DAC l/SS
96 YOUT O DAC Y signal output
97 DAVDD - DAC VDD
98 IOUT O DAC I signal or R-Y signal output
99 VREF - DAC Reference Reference voltage : 2.3V
100 QOUT C) DAC Q signal or B-Y signal output
2001 -06-1 9
TOSHIBA TC90A17F
DISPLAY SCREEN FUNCTIONS
FUNCTION DISPLAY SCREEN IMAGE
[PAP display screen (animation)]
(using TC9097F)
o 4 : 3 display
1 Main screen-animation image/subscreen- C) C)
animation image
o Full screen display
Main screen-animation image/subscreen-
animation image
[PAP display screen (still image)]
0 4 : 3 display
Main screen-animation image/subscreen-
2 still image C) Still image C)
0 Full screen display
Main screen-animation image/subscreen-
still image
[9-screen search]
0 Main screen
Animation image
0 Subscreen
3 Display of 9-screen channel-select still
image and strobe display
Only one screen displays an animation
image and other screens display
stillimages.
Still image
[PIP display]
0 Main screen
16 : 9 animation image display
0 Subscreen
Display of animation image or still image E l:
4: 3 or 16 : 9 display
[3-screen POP display]
0 Main screen
4 : 3 animation display
5 o Subscreen C)
4 : 3 animation display
Display of still image, strobe, one
animation image
[Multiple still image display]
0 Main screen
16 : 9 animation image display
6 0 Subscreen
Display of one screen of still image a
Up to 24 screens can be fetched.
Frame forward playback is possible.
8 2001-06-19
TOSHIBA TC90A17F
FUNCTION DISPLAY SCREEN IMAGE
[12-screen search]
It Main screen
animation
7 o Subscreen C)
Display of 12 screen channel-select still
image and strobedisplay
Only one animation screen is displayed
and others are still images.
[12-screen search using full screen]
0 Subscreen
Display of 12-screen channel-select still
images and strobedisplay 0
Only one animation image is displayed
and others are still images.
9 2001-06-19
TOSHIBA
TC90A17F
Standard signal input for ADC (luminance signal)
100 (IRE) 228
0.705v
0(IRE) --l. -------------------------- 63
0.275V
1.1V -40(IRE) ------l---- J
amplitude : 1.0Vp_p(100% White)
Standard signal input for ADC (color signal)
- -----------------------_------- 251
1.1V -- - ----
._1 ------------------------
amplitude : 1.0Vp_p
3Fh E- clamp level
88h e-clamp level
2001 -06-1 9
TOSHIBA
TC90A17F
Standard signal output for DAC (luminance signal)
Dec. Hex
255 FFh 3.3V
228 W 100(IRE) 3.19v
63 3Fh O(IRE) ---------------------------- 2.55v
0 ooh 1 2.3V
-40(IRE) ------------ J
amplitude : 0.9Vp_p(100% White)
Standard signal output for DAC (color signal)
Dec. Hex
255 FFh 33v
243 F3h - ----------------------------- 3,25v
128 80h --l - - 2.8V
13 0Dh --1 ------------------ ---- 2.35v
0 00h 2.3V
amplitude : 0-9Vp-p
11 2001-06-19
TOSHIBA TC90A17F
OUTLINE OF Pc BUS CONTROL FORMAT
The Bus control format of TC90A17F complies with the " bus control format of the PHILIPS Company.
Data transfer format
l S l Slave address I 0 l A l SUB address I A l XXXXX l A I XXXXX l A l P l
f 7 bits f 8 bits f 8 bits f 8 bits
MSB MSB MSB MSB S : Start condition
: Stop condition
: Acknowledgement
(1) Start condition and stop condition (2) Bit transfer
SDA must not be changed.
Start condition Stop condition
SDA can be changed
(3) Acknowledgement (4) Slave address
ic..: A6 A5 A4 A3 A2 A1 A0 R/W
SDAfrom E
master 3 i . . . . 0 0 1 o 0 1 1 0
SDA from i' i High impedance 1_/-
SCL from
master
Purchase of TOSHIBA IZC components conveys a license under the Philips " Patent Rights to use
these components in an " system, provided that the system conforms to the " Standard
Specification as defined by Philips.
12 2001-06-19
TOSHIBA TC90A17F
PC-BUS ADDRESS SETTING TABLE
Slave address 26H (00100110)
Subaddress 00H (00000000) to 3FH (00111111)
23'; MSB LSB
RESS 15 14 1 3 1 2 1 1 10 9 8 7 6 5 3 2 1 0
00 YCMF1 YCMFO YCMN C2HFT Y2HFT WiNSEL KMODE YDL3 -r2 -91 -at) KTC KTB KTA
01 KD15 -M4 -o13 -M2 -r11 -910 -99 -e8 -s7 ->6 -95 ->4 -93 -s2 -al -90
02 KD31 -930 -929 -a28 -a27 #26 -s25 -924 -923 -y22 #21 -y20 -919 -91 8 -yl 7 -yl 6
03 HYPH2 -yt --90 MIQPH1 -a0 MOSY7 -o6 -s5 -M -93 -o2 -91 -90
04 MOSIF3 -92 -91 -90 MOSQF3 -e2 -r1 -A) M05183 -92 -9t -90 MOSQB3 -r2 .-91 -90
05 HFRI3 -92 -91 -90 HFRQS -r2 -r1 -90 HFRY7 -Mi -s5 -94 -o3 -92 -91 -90
06 HWNI3 -s2 -M -s0 HWNQ3 -a2 -y1 -A) HWNY7 -s6 -s5 -M -93 -s2 -el -e0
07 RF1115 RF119 -a8 -a7 -96 -95 -M .-e3 --y2 -el -90
08 RF1215 RF129 -98 -97 -a6 -95 -94 -93 -a2 -yl -U)
09 RF1315 RF139 -e8 --y7 -s6 -95 -r4 -o3 -92 -91 -90
0A RF1415 RF149 -98 _ -s6 -r5 -r4 -93 -92 -M -90
OB RF1515 RF159 -atr a7 a6 a5 -94 a3 -92 -91 -A)
0C RF1615 RF169 -s8 -a7 -96 -r5 -o4 -o3 -o2 -al -a0
OD RF1715 RF179 -98 -97 -)6 -e5 -M -y3 -a2 -91 -A)
0E RF1815 RF189 -98 -97 -96 -95 e4 -93 -o2 -a1 -»0
OF RF1915 RF199 -s8 -97 -s6 -s5 -M -93 -r2 -rl ->0
10 RF1A15 RF1A9 -98 -97 -96 -95 -)4 -)3 -92 -y1 -a0
11 RHYSE11 -y10 -o9 -s8 RHWIE1 1 -910 ->9 -98 -97 -96 -95 -M -o3 -r2 -et -9t)
12 -o7 -96 -y5 44 RHWIS1 1 -91 0 -99 -98 -97 -)6 -e5 -M -o3 -y2 -yl -90
13 -93 -r2 -.1 -90 RVWI E9 -Nt -s7 ->6 -e5 _ -s3 ->2 -ol -90
14 RHYSS11 -91 0 -a9 -a8 RVWIS9 a8 -97 -ati -s5 -94 -a3 -s2 a1 -s0
15 -97 46 -t5 -M RHSIZ11 -91 0 -99 -98 -97 -96 -95 -94 -93 -92 -91 -s0
16 -b3 -.2 .-9t -90 RVSIZQ -98 -an -96 -oS -ytt -93 -r2 -yl -o0
17 RRH11 -tlt) -s9 -s8 _ ->6 .-r5 -94 -93 -92 -91 -90
18 RRV9 -98 -o7 -o6 -s5 -e4 -a3 -92 -)1 -s0
19 RWRN9 -98 -a7 -s6 -95 -94 -a3 -o2 -o1 .-y0
1A RWRA9 48 -97 -s6 -e5 -M -s3 -o2 -91 -90
IB RHRFTH RHRF1V RHINV2 PRHPH a10 -b9 -s8 -)7 -)6 -o5 -M -e3 -o2 -91 -90
1 C RVPG9 -98 -il -96 -a5 -M -r3 -r2 -91 -o0
1 D NTPAL WCSEL1 WCSELO PAPFIL WHST1O -99 -98 -it -96 -95 -M -93 -e2 -91 -s0
1E WHMOD3 -o2 -M -a0 WCKINV WHED10 -e9 -N? -il -s6 -es -M -o2 -a2 -91 -90
1F WEYlNV WEYDL2 -e1 -A) IENINV KWST10 -99 -98 -a7 -06 -o5 -94 -93 -92 -tl -et)
20 WECINV WECDL2 -l -90 KWED10 -99 -9t? -it -s6 -s5 -M -o3 a2 -al -90
21 WHRFTH WHRFIV WHINVZ MOH WHRST11 -a10 -99 -98 -97 -a6 -s5 -M -r3 -o2 -91 -90
22 WKHYO WHINV1 WVINV WS263 HYJ3 -o2 -91 WFCMP8 -97 ->6 -95 -M -y3 -o2 -91 -M)
23 RKHYO RHINV1 RVINV R5263 HIJ3 -92 -91 RFCMP8 -a7 -a6 -95 -94 -93 -92 -el -90
24 VF347 -946 -945 -944 VFB43 -M2 -o41 -M0 VFB39 -r38 -y37 -a36 VFB35 -t34 -a33 -932
25 VF831 -r30 -a29 -o28 VFB27 -r26 -e25 -924 VFB23 -r22 -e21 -y20 VFB19 -918 -y17 -916
26 VFB15 -e14 -st3 -s12 VF811 -910 -s9 -98 VFB7 -sti -s5 -M VFB3 -92 .-91 -ao
27 FMINT FMON PIP WXMCP2 -91 -'0 WVST8 -97 -Mi -t5 -M -o3 -92 -D1 -90
28 WVMOD3 -o2 -91 -90 WSYILL WXMCPA -93 WVED8 -97 -96 -95 -M -y3 -a2 -yl -90
29 VFTHR WXYFRM MULT1 -90 AUTIIC WXCP6 -95 -94 -93 -92 -tl -s0
2A W9H62 -91 -e0 W9IE9 -98 -it -e6 -95 -M -s3 -s2 -91 --90
28 WINT3 -Y2 -r1 -a0 W9H58 -o7 -a6 -e5 -o4 -a3 -a2 --91 --a0
2C W9M4 -93 -92 -ol -90 W9VS7 -a6 -95 -o4 -93 ~92 -pl -a0
2E RREINV RRSTINV RCKINV RREPH1 -)0 RMUTE VSVOFF PAPSW FRF1 ROEALT RFISW RFIALT
2F RF1 0_7 -Mi ->5 -M -93 -s2 -el -A)
30 OSDYA1 -A) OSDYB1 -a0 OSDXA1 -90 OSDXB1 -90 OSDXC1 -a0 OSDXD1 -M) OSDXE1 -o0
31 OSDDX7 -o6 -o5 -a4 -w3 -o2 -e1 -o0 OSDX7 -96 -e5 -e4 -o3 -e2 -ef -oo
32 OSDDY7 -a6 -95 -M -o3 -a2 -el -A) OS DY7 -e6 -e5 -M -e3 -y2 -91 -r0
34 HYJMON LMRST9 -98 -97 -Mi -95 -o4 -93 -92 -bl -oo
35 CLPST7 a6 -o5 -M -a3 -r2 -rl a0 CLPED7 -e6 -e5 -M -93 -92 -91 -9t)
MV- 3C
3F OKDSE OSDSE OLSEL DN1BYTE OWRSKC OCRW OKRW
TC90A17F -13
13 2001-06-19
TOSHIBA
TC90A17F
DESCRIPTION OF THE CONTENTS OF WRITE IZC-BUS DATA 1
DISPLAY
ADDRESS NAME FUNCTION
YCMF1 Y/C MIX signal (M/N output) polarity switching
(L : Inversion, H : Non-inversion)
YCMFO Y/C MIX signal (pre-multiplier) polarity switching
(L : Inversion, H : Non-inversion)
YCMN Switching to fixed to Y or Y/C MIX (L : Fixed to Y, H : Y/C MIX)
C2HFT Binary interpolation circuit of color signal (I/Q) (L : OFF, H : ON)
00H YZHFT Binary interpolation circuit of brightness signal (Y) (L : OFF, H : ON)
(Horizontal thinning mode : 3/8[5H], 2/5[6H]=H)
W1NSEL Switching of thinning processing circuit
(L : M/N thinning, H : 1/N thinning)
KMODE Horizontal filter coefficient mode switching
(I : L/N processing, H : M/N processing)
YDL3-0 Brightness signal (Y) delay adjustment (0 to 10CK, 600fh units)
KTC-A Filter coefficient count setting (OH = 1, 7H =8)
KD3-0 Horizontal filter 1st coefficient
01H KD7-4 Horizontal filter 2nd coefficient
KD11-8 Horizontal filter 3rd coefficient
KD15-12 Horizontal filter 4th coefficient
KD19-16 Horizontal filter 5th coefficient
KD23-20 Horizontal filter 6th coefficient
02H . . . .
KD27-24 Horizontal filter 7th coefficient
KD31-28 Horizontal filter 8th coefficient
NTPAL NTSC/PAL (L : NTSC, H : PAL)
WCSEL1, 0 HQ inversion (1 =For SEL block, (O=ADIQ for multiplexer)
1DH PAPFIL PAP/filter processing switching (L : PAP, H : Filter processing)
WHST10-0 Specification of Write Enable Horizontal Gate Starting position
(setting an odd number value only)
WHMOD3-0 Setting thinning rate
0H=1/16,1H=1/8, 2H=1/5, 3H=1/4, 4H=1/3, 5H=3/8, 6H=2/5, 7H=1
/2, 8H=3/5, 9H=5/8, AH=2/3, BH=3/4, CH=4/5, DH=7/8, EH=15/16,
1EH FH = 16/ 16
WCKINV Inversion of field memory Write clock polarity (H : Sets inversion)
WHED10-0 Specification of an end position of Write Enable Horizontal Gate (Set an
odd value only)
14 2001-06-19
TOSHIBA
TC90A17F
DESCRIPTION OF THE CONTENTS OF WRITE IZC-BUS DATA 2
£33555 DW‘EY FUNCTION
WEYINV Polarity inversion of brightness field Memory Writer Enable signal (WENY)
(L : Sets non-inversion)
WEYDL2-0 WENY signal delay adjustment (Unit : 1200fh)
OH-- +0,1H= +1, 2H= +2, 3H= +3, 4H= +4, 5H= +6, 6H= -1, 7H= -2
1FH (Set OH = +0)
IENINV Polarity inversion of field memory Input Enable signal
(L : Non-inversion, H : Inversion)
(Set according to the memory specification (fixed after determination))
KWST10-0 Specification of HFIL operation gate (WKWHY) start position
(set an odd number only)
WECINV Polarity inversion of color field memory Write Enable signal (WENC)
(L : Sets non-inversion)
20H WECDL2-0 WENY signal delay adjustment (unit : W2CK)
KWED10-O 0H= +0,1H= +1, 2H= +2, 3H= +3, 4H= +4, 5H= +6, 6H= -1, 7H= -2
Specification of end position of HFIL operation gate (WKWHT) (Set an odd
value only)
WHRFTH PLL control signal (WHREF) forced output (H : Forced output)
WHRFIV WHREF polarity inversion (L : Non-inversion, H : Inversion)
21H WHINV2 HD polarity inversion of WHREF output control
(L : Non-inversion, H : Inversion)
MOH Field memory occupation signal (L : Other IC, H : PAP IC)
WHRST11-O Write horizontal phase reference
WKHYO Write forced standard checking
(L : Standard/non-standard, H : Forced standard)
WHINV1 Subscreen-horizontal synchronous signal (WHD) polarity inversion
(L : Non-inversion, H : Inversion)
22H WVINV Subscreen-vertical synchronous signal (WVD) polarity inversion
(L : Non-inversion, H : Inversion)
WS263 Inversion of Write field checking (L : 263, H : 262)
HYJ3-1 Non-standard checking circuit setting value
WFCMP8-0 Write forced non-standard setting value
15 2001-06-19
TOSHIBA
TC90A17F
DESCRIPTION OF THE CONTENTS OF WRITE IZC-BUS DATA 3
ASSEESS D/ll'l-hy FUNCTION
RKHYO Read forced standard checking
(L : Standard/non-standard, H : Forced standard)
RHINV1 Main screen-horizontal synchronous signal (RHD) polarity inversion
(L : Non-inversion, H : Inversion)
23H RVINV Main screen-vertical synchronous signal (RVD) polarity inversion
(L : Non-inversion, H : Inversion)
RS263 Inversion of Read field checking (L : 263, H : 262)
Hl)3-1 Non-standard checking circuit setting value
RFCMP8-0 Read forced non-standard setting value
VFB47-44 Vertical filter 1st coefficient A
24H VFB43-40 Vertical filter 2nd coefficient A
VFB39-36 Vertical filter 3rd coefficient A
VFB35-32 Vertical filter 4th coefficient A
VFB31-32 Vertical filter 5th coefficient A
25H VFB27-24 Vertical filter 6th coefficient A
VFB23-20 Vertical filter 7th coefficient A
VFB19-16 Vertical filter 8th coefficient A
VFB15-12 Vertical filter 9th coefficient A
VFB11-08 Vertical filter 10th coefficient A
26H VFB07-04 Vertical filter 11th coefficient A/1st coefficient B (VFB 7, 6), 2nd coefficient
B (VFB 5, 4)
VFBO3-00 Vertical filter 3rd coefficient B (VFB 3, 2), 4th coefficient B (VFB 1, 0)
FMINT Field memory initialization ON/OFF (for control by micro controller only)
(H : ON)
FMON Fixed to H
27H . .
PIP Handles PIP display (frame display) (H : PIP)
WXMCP2-0 Setting horizontal block cycle of strobe display mode (0H : 1 to 7H : 8)
WVST8-0 Specification of start position of Write Enable Vertical Gate
WVMOD3-0 Vertical thinning rate setting
0H=1/16,1H=1/8, 2H=1/5, 3H=1/4, 4H=1/3, 5H=3/8, 6H=2/5, 7H=1
/2, 8H=3/5, 9H=5/8, AH=2/3, BH=3/4, CH=4/5, DH=7/8, EH=15/16,
FH = 16/ 16
28H WSTILL Field memory Write Halt (still regeneration) (H : Write Halt)
(Changing parameters after halt operation)
WXMCP4, 3 Setting vertical block cycle setting of a strobe display mode
(0H:1to3H:4)
WVED8-0 Specification of end position of Write Enable Vertical Gate
16 2001-06-19
TOSHIBA TC90A17F
DESCRIPTION OF THE CONTENTS OF WRITE IZC-BUS DATA 4
SUB- DISPLAY
ADDRESS NAME FUNCTION
VFTHR Vertical filter ON/OFF (L : ON, H : OFF)
WKYFRM Write forced frame processing (L : Normal, H : Forced frame)
MULT1, 0 Memory control signal mode switching
29H (00H : PAP, 11H : Multiple search, strobe)
AUTIIC Switching split display Write position specification mode
(L : Bus setting, H : Automatic setting)
WXCP6-0 Specification of memory write interval (2, 4, 6, 8, to 512 fields)
W9HB2-0 Split screen control-setting the number of horizontal blocks
(number of horizontal bIocks-1)
2AH . . . . .
W9IE9-0 Split screen control-setting horizontal input enable period
Number of block picture elements x (number of horizontal blocks-1))
2BH WINT3-0 Setting field memory initialization level (SEL block)
W9HS8-0 Split screen control-setting the number of block picture elements-3
W9M4-3 Split screen control-specification of Write position
(vertical, 0-o3 : Top-obo-) (AUTllC=L)
W9M2-0 Split screen control-specification of Write position
2CH (horizontal, 0-97 : Left-it) (AUTllC=L)
W9VS7-0 Split screen control-setting the number of block lines
(number of block lines-I)
[Note : Subaddress 2CH is for transmission only in multiple search Write
processing]
34H HYJMON Fixed to L
LMRST9-0 Rest phase of vertical filter line memory
35H CLPST7-0 Specification of clamp pulse start position
CLPED7-0 Specification of clamp pulse stop position
17 2001-06-19
TOSHIBA
TC90A17F
DESCRIPTION OF THE CONTENTS OF READ IZC-BUS DATA 5
ASSEESS D/ll'l-hy FUNCTION
03H HYPH2-0 Read Y signal phase adjustment
HIQPH10 Read I and QY signal phase adjustment
HFR13-0 Frame I signal level
05H HFRQ3-0 Frame Q signal level
HFRY7-0 Frame Y signal level
HWNl3-0 I signal clamp level
06H HWNQ3-0 Q signal clamp level
HWNY7-0 Y signal clamp level
07H RF1115 1st horizontal frame ON/OFF (0 : ON)
RF11 (9-0) 1st horizontal frame vertical phase
08H RF1215 2nd horizontal frame ON/OFF (0 : ON)
RF12(9-O) 2nd horizontal frame vertical phase
09H RF1315 3rd horizontal frame ON/OFF (0 : ON)
RFI3(9-0) 3rd horizontal frame vertical phase
OAH RF1415 4th horizontal frame ON/OFF (0 : ON)
RF14(9-0) 4th horizontal frame vertical phase
OBH RF1515 5th horizontal frame ON/OFF (0 : ON)
RF15(9-0) 5th horizontal frame vertical phase
OCH RF1615 1st vertical frame ON/OFF (0 : ON)
RF16(9-0) 1st vertical frame horizontal phase
ODH RF1715 2nd vertical frame ON/OFF (0 : ON)
RF17(9-0) 2nd vertical frame horizontal phase
OEH RF1815 3rd vertical frame ON/OFF (0 : ON)
RFI8(9-0) 3rd vertical frame horizontal frame
OFH RF1915 4th vertical frame ON/OFF (0 : ON)
RF19(9-0) 4th vertical frame horizontal phase
10H RF1A15 5th vertical frame ON/OFF (O : ON)
RF1A(9-0) 5th vertical frame horizontal phase
11H RHYSE11-8 YS signal horizontal end phase (MSB)
RHWIE11-0 Clamp window horizontal start phase
12H RHYSE7-4 YS signal horizontal end phase
RHWlS11-0 Clamp window horizontal start phase
13H RHYSE3-0 YS signal horizontal end phase (LSB)
RVWIE9-0 Clamp window vertical end phase
14H RHYSS11-8 YS signal horizontal start phase (MSB)
RVWIS9-0 Clamp window vertical start phase
15H RHYSSO7-4 YS signal horizontal start phase
RHSlZ11-0 Horizontal display size (number of horizontal picture elements-?)
16H RHYSSO3-0 YS signal horizontal start phase (LSB)
RVSIZ9-0 Vertical display size (number of lines)
18 2001-06-19
TOSHIBA TC90A17F
DESCRIPTION OF THE CONTENTS OF READ IZC-BUS DATA 6
ASSSéss D1531? FUNCTION
17H RRF11-0 Horizontal display start phase
18H RRV9-0 Vertical display start phase
19H RWRN9-0 Field memory Write/Read phase setting value 1
1AH RWRA9-0 Field memory Write/Read phase setting value 2
RHRFTH RHREF output control forced output mode setting (L : Normal, H : Forced
output)
1BH RHRFIV RHREF output polarity inversion (L : Non-inversion, H : Inversion)
RHINV2 RHREF output control HD polarity inversion (L : Non-inversion, H : Inversion)
PRHP11-0 Read processing, horizontal reference (PLL counter value decoding)
RVPG9-0 Read processing, vertical reference
1CH (input VD : vertical counter, reading initial value)
RREINV Polarity inversion of field memory Read Enable (RRE) signal
(L : Non-inversion, H : Inversion)
RRSTINV Polarity inversion of field memory Read Reset (RRST) signal
(L : Non-inversion, H : Inversion)
RCKINV Polarity inversion of field memory Read Clock (RCK) signal
(L : Non-inversion, H : Inversion)
2EH RREPH1-0 RRE signal phase adjustment
RMUTE Read, Image muting (L : Without muting, H : Muting)
YSVOFF YS signal vertical ON/OFF (L : ON, H : OFF)
PAPSW ON in PAP mode (L : ON, H : OFF)
FRFI Forced single field display ON/OFF (L : OFF, H : ON)
ROEALT ODD/EVNE inversion (L : Normal, H : Inversion)
RFISW Fixed to H
RFIALT Fixed to L
2FH RF10 (7-4) Horizontal frame thickness adjustment (thick-afine, fine-athick)
RF10 (3-0) Vertical frame thickness adjustment (thick-afine, fine-athick)
19 2001-06-19
TOSHIBA
DESCRIPTION OF THE CONTENTS OF READ PC-BUS DATA 6
(contents supplement)
1. Frame display (see Figure I)
(1) Up to five of each vertical and horizontal frames can
be displayed in any positions.
(2) Any vertical and horizontal frames can be erased.
(3) Y signals can be set in 8-bit precision and I and Q
signals can be set in 4-bit precision.
(4) The frame thickness can be set in 4-bit precision.
(5) Use the 1st and 5th vertical and horizontal frames for
one-screen display such as PIP.
2. Display of a clamp window (see Figures 2 and 3)
(1) A clamp window can be set in any position with any
(2) Clamp level variable range of the shaded section
Y signal : OH to FFH
l and Q signals: 78H to 87H
3. YS signal (See Figure 3)
(1) Set horizontal timing of YS signals according to the
horizontal start position RHYSS and horizontal end
position RHYSE.
(2) For vertical timing, the vertical start position RVWIS
and vertical end position RVWIE of the clamp
window are also used.
(3)When YS signal vertical ON/OFF (YSVOFF) is set to
OFF, the is also set to the YS signal level.
4. Read phase adjustment
4M mode
The Y signal comprises 8 steps and the C signal
comprises 4 steps in 26ns units.
5. PAPSW signal
To set double-screen display (PAP), set the signal to 0.
6. FRFI signal
To set forced single display, set the signal to 1.
TC90A17F
Vertical frame
1st 2nd 3rd 4th 5th
Horizontal 3rd
Figure 1
Figure 2
RHYSS RHYSE
Figure 3
2001 -06-1 9
TOSHIBA TC90A17F
DESCRIPTION OF THE CONTENTS OF READ IZC-BUS DATA 7 (OSD related data 1)
£33555 D1531? FUNCTION
03H MOSY7-O Brigtness level setting of OSD display character
MOSIF3-0 Setting I level of OSD display character color 1 (OCOLR=0)
04H MOSQF3-0 Setting Q level of OSD display character color 1 (OCOLR=0)
MOSIB3-0 Setting I level of OSD display character color 2 (OCOLR= 1)
MOSQB3-0 Setting Q level of OSD display character color 2 (OCOLR= 1)
OSDYA1-0 Screen start position micro adjustment A (vertical)
OSDYB1-0 Screen start position micro adjustment B (vertical)
OSDXA1-O Screen start position micro adjustment A (horizontal)
30H OSDXB1-0 Screen start position micro adjustment B (horizontal)
OSDXC1-0 Screen start position micro adjustment C (horizontal)
OSDXD1-0 Screen start position micro adjustment D (horizontal)
OSDXEI-0 Screen start position micro adjustment E (horizontal)
31H OSDDX7-0 Adjustment of width for OSD display (horizontal)
OSDX7-0 Screen display start position (horizontal)
32H OSDDY7-0 Adjustment of width for OSD display (vertical)
OSDY7-0 Screen display start position (vertical)
OKDSE Character shadow selection (L : 1 dot, H : 2 dots)
OSDSE Character display (L : OFF, H : ON)
OLSEL Screen display selection (L : Display mode 1, H : Display mode 2)*
3FH ON1BYTE 1-byte Write selection (L : Normal, H : 1-byte Write)
OWRSKC Write RAM selection (L : Character, H : Code)
OCRW Code RAM Write ON/OFF (L : ON, H : OFF)
OKRW Character RAM Write ON/OFF (L : ON, H : OFF)
* : See Page 22
21 2001-06-19
TOSHIBA
. Display mode 1
DESCRIPTION OF THE CONTENTS OF READ IZC-BUS DATA 8 (OSC related data 2)
TC90A17F
00|o1|02|03|04
05|06|07|08|09
OAIOBIOCIODIOE
0F|10|11|12|13
14|15|16|17|18
19|1A|1B|1C|1D
20|21|22|23|24
25l26|27|28|29
ZAIZBIZCIZDIZE
2Fl30l31|32l33
34|35|36|37|38
39|3A|3B|3cl30
40|41|42|43|44
45|46|47|43|49
4A|43|4c|4D|4E
4F|50151|52|53
sol ssl ssl srl 58
59|5AI5B|5CISD
(Note 1) OSD display possible up to a vertical maximum 3 blocks x horizontal maximum 6
blocks.
(Note 2) The digits in one screen indicate the code RAM address.
2. Display mode 2
00|o1|02|03|04
05|06|07|08|09
OAIOBIOCIODIOE
0Fl1OI11I12|13
18l19l1A|1B|1c
1DI1EI1FI20I21
22|23I24I25l26
27I28|29|2A|23
30|31|32|33|34
35|36|37|38|39
3A|3B|3C|3D|3E
3F loo lal |42 |43
48|49|4A|4B|4c
oDlolFls0ls1
52|53|54155156
57IS8IS9I5AISB
(Note 1) OSD display possible up to a vertical maximum 4 blocks x horizontal maximum 4
blocks.
(Note 2) The digits in one screen indicate the code RAM address.
3. Example of code data
J___1L
Character color : 1bit Code data : 5 bits
22 2001-06-19
TOSHIBA TC90A17F
DESCRIPTION OF THE CONTENTS OF READ IZC-BUS DATA 8 (OSC related data 3)
Example of character data creation
12 blocks
m Unable to use
IE,02, F0 oc. 01, C0
73, 86, 18 3C, 03, C0
S' 61, 86, 18 0C, 00, C0
.o 61, 86, 18 0C, 00, C0
T" 61, 86, 18 0C, 00, C0
61, 86, 18 0C, 00, C0
61, 87, 38 0C, 00, C0
J_ 3F, 01, EO 3F, 03, F0
02 hex
1E, 03, F0 1E, 03, F0
63, 04, 18 73, 06, 18
41,80,18 41,80,18
01, 80, 30 03, 01, E0
06, 00, C0 1F, 00, 38
18, 03, 00 01, 84,18
20, 06, 00 61, 87, 38
7F, 87, F8 03, 01, E0
04 (hex) 05 (hex)
07, 00, 70 7F, 87, F8
0F, 00, F0 60, 06, 00
1B, 01, BO 60, 06, 00
13, 03, 30 6E, 07, F0
33, 06, 30 73, 80, 18
63,07, F8 01, 80, 18
7F, 80, 30 61, 87, 30
03, 00, 30 3F, 01, E0
23 2001-06-19
TOSHIBA TC90A17F
MAXIMUM RATINGS (VSS=0V, Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Power Supply Voltage VSS, VDD Vss--vss+4.0 V
Input Voltage VIN - 0.3~VDD +0.3 V
Power Dissipation PD (Note) 1430 mW
Storage Temperature Tstg - 55--125 "C
(Note) When using the controller under the temperature Ta=25°C
or higher, reduce the acceptable loss by 14.3mW per 1°C.
POWER CONSUMPTION TEMPERATURE DROP CURVE (when substrate is installed)
"ii'" I
Js I55 70I 160 1ls
OPERATION TEMPERATURE (°C)
RECOMMENDED OPERATING RANGE (VSS=0V)
CHARACTERISTIC SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Power Supply Voltage VDD - 3.0 3.3 3.6 V
Input Voltage VIN - 0 - VDD V
Operation Temperature Topr - - 20 - 70 °C
2001 -06-1 9
TOSHIBA TC90A17F
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
(Operation conditions : VD_D=3.0~3.6V, V|\|=0~VD_D, Ta = -20~70°C, 1/ss=0U)
TEST APPLICABLE
CHARACTERISTIC SYMBOL gm} CONDITION MIN. TYP. MAX. UNIT TERMINALS
Current Consumption IDD1 - NTSC 180 mA
High Level CMOS Input v - x0.8 V ( )
Input Voltage Shumitt IH VDD (*2)
Trigger Input X0-8
Low Level CMOS Input v - x0.2 v ( )
Input Voltage shumitt IL VDD (*2)
Trigger Input x0.2
High Level IIH V|N=VDD -10 10
- A *3
Input Current Low Level 'IL VIN=VSS -10 10 /1 ( )
High Level VOH1 lOHI=4mA 2.4 ( 4)
o t t v It VOH2 IOH2=8mA 2.4 v (*5)
u pu o age Low Level VOL1 lOL1=4mA 0.4 (*4)
VOL2 lOL2 = 8mA 0.4 (*5)
1hlmitt.T?y.tr And VH - 0.5 (*2)
Hysteresis Voltage
TEST3--0, TIMRST, PWRST
OSD1, OSD2, RHREF, SDMON, SDA
WMCK, RMCK
WCK, RDAC7--0, RDAY7--0, RMCKI, RCK, SDA, IICNR, TEST3--0, TIMRST, PWRST
WVD, WHD, RHD, RVD, SCL
WVD, WHD, WCK, RDAC7--0, RDAY7--0, RMCKI, RCK, RHD, RVD, SCL, SDA, IICNR,
MOH, WHREF, WIE, WENC, WENY, WRST, WDAC7--0, WDAY7--0, REN, RRST, YS,
2001 -06-1 9
TOSHIBA TC90A17F
AC CHARACTERISTICS
(Operation conditions : VDD-- 3.0~3.6V, VIN --0--VDD, Ta = -20~70°C, Vss=0V)
TEST TEST
CHARACTERISTIC SYMBOL CIR- CONDITION MIN. TYP. MAX. UNIT REMARKS
Smertt.ion Frequency - NTSC mode 20 MHz
Condition
. TSUP1 Operation 5 - -
Input Setup Time TSUP2 - frequency MHz 5 - - ns
. THLD1 Operation 3 - -
Input Hold Time THLD2 - frequency MHz 5 - - ns
Tpd1 5 - 14
Tpd2 4 - 11
Tpd3 6 - 19
Tpd4 6 - 15
Tpd5 6 - 19
Tpd6 6 - 15
Tpd7 6 - 19
Tpd8 6 - 15
Tpd9 7 - 21
Output Propagation Delay Tpd10 - 6 - 16 ns
Time Tpd11 6 - 18
Tpd12 6 - 15
Tpd13 6 - 18
Tpd14 5 - 15
Tpd15 4 - 13
Tpd16 4 - IO
Tpd17 6 - 18
Tpd18 5 - 14
Tpd19 6 - 18
Tpd20 6 - 13
26 2001-06-19
6l'90'l002 LZ
I 3|N\
ELLIEIM
3WLL AV'IEIG lndan ’8 EIWIJ. G'IOH°dn.LES
:I/JVOBDJ. VHIHSOL
TOSHIBA TC90A17F
ADC CHARACTERISTICS
(Operation conditions : VDD = 3.3V, Ta = - 20~70°C, l/SS = 0V)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Non-linear Error ILE - i1 LSB
Differential Non-Iiner Error DLE - $0.5 LSB
Analog Input FULL SCA VIFS - 2.2 V
Voltage ZERO SCA VIZS - 1.1
CLAMPING AND MULTIPLEXER
(Operation conditions : VDD=3.3V, Ta = -20--70oc, Vss=0V)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Clamping Y - 63 LSB
Clamping C - 136 LSB
Multiplexer - 5 MHz
DAC CHARACTERISTICS
(Operation conditions : VDD=3.3V, Ta = -20--70oc, VSS=0V)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Non-linear Error ILE - i1 LSB
Differential Non-Iinear Error DLE - i1 LSB
Analog Output FULL SCA VIFS - VDD V
Voltage ZERO SCA VIZS - VREF
28 2001-06-19
TOSHIBA TC90A17F
PACKAGE DIMENSIONS
QFP100-P-1420-0.65A Unit : mm
23.8:e0.3
20.0i0.2
0.825TYP
14.0i0.2
17 Bio 3
0.575TYP 0.3i0.1
kl0.jiliif
50.15 (P.
O T -_-.-
0.8i0.2
Weight : 1.69 (Typ.)
29 2001-06-19
TOSHIBA TC90A17F
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
30 2001-06-19
www.ic-phoenix.com
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