TC8566AF ,FLOPPY DISK CONTROLLERFEATURESSi-Gate CMOS technologySingle Hill power supply100 pin plastic flat packageCompatible FDC w ..
TC8569AF ,FLOPPY DISK CONTROLLERGENERAL DESCRIPTIONTC8569AF is a single chip LSI for Floppy DiskController, which has VFO and other ..
TC8569AF ,FLOPPY DISK CONTROLLERW src-i) I Huavaua unagvén £7 i/Gia'FLOPPY DISK CONTROLLER llTOSHIBA (UC/UP)TC8569AFFloppy Disk Con ..
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TC8566AF
FLOPPY DISK CONTROLLER
FLOPPY DISK CONTROLLER (Ill
TC8566AIF
Floppy Disk Controller
1. INTRODUCTION
TC8566AF is a single chip LSI for
Floppy Disk controller which has VFO
and other circuits with FDC chip for
interfacing a processor to floppy
disk drives.
ertCoestg:tcNmrevVrN-Cc' co
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2. FEATURES
Si-Gate CMOS technology
Single ttill power supply
100 pin plastic flat package
Compatible FDC with TC8565AP
Built-in VCO and data separator
circuit.
16MHz oscillator inverter.
0 Standby function for battery
operation
o 1/0 address decoder include
o Standard(500Kbps) and
O O O O O
Fw-P-h-r-b—b—v—
dmma-mrot—omoouwov‘hwspm
I-unx'n—‘a
Mini(250Kbps) programable 'ii', 55
o FM,MFM recording formats 27 lit
(Specified by command) E? il
o Multi-sector data transfer w m
0 Up to four floppy disk drives
0 MOTOR ENABLE control for 4 drives
0 Direct interface to FDD with CMOS
7A,7ifl - - JIJIL -
“fo'SHIB'A'YUE/U‘P) -iard 1) CI Havana 60257047725 DTOSB
type Interface system
Parallel seek operation up to four
floppy disk drives
Programmable step rate time
Write pre-compensation circuit
Compatible with IBM track formats
Including CRC check function
(X16+X12+x5+1)
o DMA/Non DMA transfer
T08566AF-1
"NH WIN! ”WI
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TOSHIBA (UC/UP) 0L0: 1) ICCI 0007200 0020705 GUI, EITOSEI
lill FLOPPY DISK CONTROLLER
The TC8566AF is an improvement on the TC8566F, The differences between
them are as follows.
o VFO Part
66F l 2 filter switching type,
66AF '. 2 filter switching type or 1 filter non-switching type,
selectively.
0 Address Decoder
66F l Address F0,F1 (Hex) is inhibit.
66AF t Address F0,F1 (Hex) is no selection.
o DMA Terminal Count
66F l DMATC signal is Independent of ENID bit.
66AF , DMATC signal is enabled when ENID bit is "I''.
0 Step Rate Select
66F , Step Rate Time is selected by 2ms for mini-floppy mode
(internal FDC Clock is 4MHz).
66AF .. There is an option for tttini-floppy mode that the FDC
allows the internal Clock to be 8MHz at seek mode. Then
step rate time is programable by lms like standard floppy
o Reset State
66AF t Drive Output Signals, WE, HL, HS, FR, STP, LC and DR
become inactive when the external RESET signal is on a
high level.
0 Relation between Drive Select Signals and Motor Enable Signals
66F : Drive Select Signals are Independent of Motor Enable
Signals.
66AF ' Wen drive select bits of the control register is used
(CDS signal is on a high level), each Drive Select Signal
is enabled by the corresponding Motor Enable Signal.
TC8566AF-2
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FLOPPY DISK CONTROLLER (lil
_iTsim3, (U6}U§344W "
3. FLOPPY DISK SYSTEM
INTERNAL BLOCK DIAGRAM 0F T08566AF
CLOCK GENERATOR
STANDBY
CONTROL
CONTROL REGISTER
WR l TE
PRE-COMPENSATION
c l RCU IT
VFOKST
FLT/TRU
FR/STP
I N T E R F A C E
I /’ (J
INTERFACE
~SRSEL
-VFOEN
-RH/SK
0 SYN)
(3 Ill.
1) D52
o HENZ
(D HEN!
o HELD
C, DSA
l) PSI
TC8566AF-3
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TOSHIBA (UC/UP) 0.111: I) rzrcu:vwiyic, 0132137130 1130 Errosa
IlllFLoPr'Y DISK CONTROLLER .
3.2. APPLICATION OF T08566AF
3.2.1. 2 FILTER SWITCHING TYPE
Wt) FDD
LI WS l
000-001 - MF07 -10X 1000x
000-1107 > M-M -0011 READY
llrTllil ~00 00110 PROTECTED
101 -2s THO S100
-FLT FAULT
Dl4h -m 1000000
000-007 " §TEE
000-1101 - 10 UN Cl,llllliO
000 00 Dlflr'.()TlON
110.11 - 1011 IL.
-DACK2 -DACK2 < Ill, HEAD LOAD
DRQZ _ 0llll2
10 00010 tD G - 0000 301001
D63 001v0 SELECT 4
CTL tD ----_r_r-r-
062 DRIVE SELECT 3
ID _..-...---.-.--
000-001 -cs (1) IM > 001vc SELECT fl
000-001 - -100 (L) D60 Dfllllll SELECT 1
us -lok' l-. HE - 110110 000131.13
L, mmr wm1 ,umm0n0
cs -fi0T 0000 0010
C4 HOTOR ENABLE
HEM a:
31001 0002 =
11001 1115110 =
[Lili-rr--------- SIN cns
, -TEST SIB
VCO EDT
1 -011/30 PSI
LPF2 1001
0000 LHSEL
.-YN1s'.N
l MI -S8SliL I
TC8566AF-4
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FLOPPY DISK CONTROLLER HI]
TOSHIBAU?bé/U;5
3.2.2. 1 FILTER SWITCHING TYPE
MPU T T sr,TTI, poo
VDD IA m ,
020-037 _ D0-D7 -on INDEX
ABU-ABI < _ MI-M -an READY
lhl'k'0 +13 mm PROTECTED
m -2s m SIDE
-m FALLT
Ohh -m mcxoo
mau-nm SIP STEP
AEO-AB? q-- w Uhi cuWAf
on DR DIRECTION
m _ m LL
-0,IG? -mcx2 < Ill, HEAD LOAD
DRQZ mm
1c mum: (0 HS HEAD SELECT
D63 DRIVE SELECT 4
CTL tD 1352 iyTiiiejihtT-i SLUicT 3
920-997 -cs at 061 DRIVE smcf‘z
auwm A -on 0 use mun; SELECT 1
-IOH l- HE " Wm: ENABLE
L, mar um wens um
a -kDT _ READ DATA
C4 140103 mm;
smv m2 '
xou mm '
[F-i'-""-"-""--.'"-"-"-- xn: cos
lllh USA
-SHI;N
_ -TEST Sll8
FOO HDT
-illi/SK fest
HA, "T LPF! M
UT? TRDT
con LHSEL
hi; -SRSEL
T08566AF-5
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TOSl-TI-BA (UC/UP) 00+: J) ICCI 0007200 I3i3i?G'7i3H 207 EITOSEI
illl FLOPPY DISK CONTROLLER
4. PIN DESCRIPTION
4.1. PIN CONFIGURATION
N0. 1/0 NAME N0. Ip'0 NAME N0. I/O NAME
1 o C6 36 I0 VCO 71 0 FR
2 I -IOR 37 0 LPF2 72 0 LC
3 NC 38 O LPFl 73 0 DR
a I -IOW 39 0 CV 74 G VSS
5 I A0 40 I DIf 75 V VDD
6 I A1 41 O FLTl 76 I -IDX
7 I A2 42 0 DOS 77 I -RDY
8 I A3 43 I LOCK 78 NC
9 I A4 44 I -RDT 79 NC
10 I A5 45 O XOUT 80 I -WP
11 I A6 46 I XIN 81 I -2S
12 I A7 47 I -VFOEN 82 I -FLT
13 I -CS 48 1 MIN 83 I -TKO
14 I AEN 49 o MFM 84 o PSI
15 IO D0 50 NC 85 o PSO
16 IO DI 51 NC 86 o DSB
17 10 D2 52 NC 87 0 DSA
18 10 D3 53 I -CL 88 I LA
19 IO D4 54 G VSS 89 NC
20 10 D5 55 0 SYNC so V VDD
21 10 D6 56 o WDTI 91 NC
22 10 D7 57 0 WE 92 I CDS
23 0 DR02 58 0 HS 93 I RESET
24 0 INTRO 59 0 HL 94 I SHB
25 o INT 60 O MEN3 95 I SHA
26 o DRQ 61 o MEN? 96 I -SHEN
27 G VSS 62 O MENl S7 o STNBY
28 G AG M o MENU 98 o WDT
29 NC 64 G VSS 99 O ENID
30 NC 65 V VDD 100 0 C4
31 NC 66 o DM
32 I -DACK2 67 o D82
33 I DMATC 68 0 DS1
34 I CONT 69 o DSO
35 I -TEST 70 0 STP
TCB566AF-6
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*wéHIBA wt/um - -i,Tii: J) E lama; ritfisir:ir/iiyr, mos;
FLOPPY DISK CONTROLLER Ill]
DESCRIPTION OF PIN FUNCTION
[ Il C6 (CONTROL OUT BIT 6) output
Output port of C6 bit in a control register.
T 2] -IOR (IO READ) Input
Low active control signal to transfer data from the FDC to the
Data-bus.
[ 3] NC (NON CONNECT)
T 4] -um (IO WRITE) Input
Lott active control signal to transfer data from the Data-bus to the
5] A0 (ADDRESS 0) Input
6] A1 (ADDRESS I) Input
7] A2 (ADDRESS 2) Input
8] A8 (ADDRESS 3) Input
9] A4 (ADDRESS 4) Input
10] A5 (ADDRESS 5) Input
11] A6 (ADDRESS 6) Input
12] A7 (ADDRESS 7) Input
Address select input.
r—Ir-III—If—Il—H—H—‘H
[ 13] -cs (Chip Select) Input
[ 14] AEN (Address enable) Input
"Low level" on (-csl and [AEN] selects the FDC-II, and allows
[-10R] and [-IOW] to be effective.
15] D0 (DATA 0) Input/Output
16] DI (DATA 1) Input/Output
17] D2 (DATA 2) Input/Output
18] D3 (DATA 3) Input/Output
19] D4 (DATA 4) Input/Output
20] D5 (DATA 5) Input/Output
21] D6 (DATA 6) Input/Output
22] D7 (DATA 7) Input/Output
Bidirectional 8-bit Data Bus.
[ 23] DRG? (DMA REQUEST 2) Output
Request signal for DMA transfer. This signal is the delayed [DRQ]
from internal FDC chip. This signal is disabled to "Low level" with
setting O(zero) on the ENID bit in the CONTROL-REGISTER-O.
( 24] INTRO (INTERRUPT REQUEST) Output
Interrupt request signal for system from internal FDC chip. This
signal is disabled to "LOW level" with setting O(zero) on the ENID
bit in the CONT'R0L-REtuSTER-0.
[ 25] INT (INTERRUPT) Output
Interrupt request signal from internal FDC chip.
TC8566AF-7
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TOSHEEA (UC/UP) - ELIE» 7E! mv/iris:, Cli3i2U'?h1 mas DTOSB
ilil FLOPPY DISK CONTROLLER
[ 26] DRQ (DMA REQUEST) Output
DMA request signal from Internal FDC chip.
[ 27] V38 (GROUND)
Chips ground for digital circuits.
f 28] M (ANALOGUE GROUND)
Analog ground for VCO and PLL circuits.
[ 29-31] NC (NON CONNECT)
[ 32] -DACK2 (DMA ACKNOWLEDGE) Input
Low active DMA cycle executing signal. When the FDC works DMA MODE,
this signal controls DMA 1/0.
[ 33] DMATC (DMA TERMINAL COUNT) Input "
High active DMA transfer terminating signal. When the FDC works DMA
MODE, this signal terminates the DMA transfer.
f 34] CONT (VCO CONTROL INPUT) Input / Analog signal.
Analog voltage control Input for VCO.
f 35] -TEST (CHIP TEST) Input
The Input terminal for LSI test. Internal PULL UP device allows to
"High level" even if open circuits.
[ 36] VCO (VCO TEST) lnput/Output
The input/output terminal for LSI test. To leave open for normal
operation.
[ 37] LPF2 (Low PASS FILTER 2) Output
The charge pump output for external Low Pass Filter. This output
will select after PLL has pulled In the read signal and use low gain
filter.
[ 38] LPF1 (LOW PASS FILTER 1) Output
The charge pump output for external Low Pass Filter. This output
will activate when PLL circuit force to lock tho read signal
(Pull-in mode).
( 39] TRDT (TEST READ DATA) Output
The terminal for test. Use in non-connect.
[ 40] DW (DATA WINDOW) Input
The window(for FDC) signal Input when "External VCO mode" is
selected. If internal VFO will be used, "HIGH or LOW level" should
be applied for safe operation.
[ 41] -RW/SK (READ t WRITE/SEEK) Output
"Low'' shows that read/write mode is selected, and "High" shows that
seek mode is selected.
TC8566AF-8
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Tosrmi/i%.rc%ir) -iT,siii: o" 'E nrcr/iijrc, i:ririsiEii, 8T1 IZITOSEI
FLOPPY DISK CONTROLLERHI]
T 42] TDU (TEST DATA WINDOW) Output
The terminal for test. Use In non-connect.
f 43] LMSEL (LOCK MODE SELECT) Input
This signal decides the operation of the internal VFO circuit.
Pull-up resistor is on-chip. The UFO operates in one filter
non-switching mode when "Low", and operates in two filter (high gain
and low gain filter) switching mode when "High" or open.
l 44] -RDT (READ DATA) Input
The input for the READ DATA from the floppy disk drive. When
Internal VFO is operated, the negative MFM signal is applied. And
when external VFO is used, then applied positive MFM signals.
[ 45] XOUT (XTAL OUT) Output
This output is Inverted signal of [XIN], or connected the crystal
oscillator.
I 46] XIN (XTAL IN) Input
This input connects the crystal oscillator or external clock signal.
In the standard usage, use 16MHz crystal oscillator.
[ 47] -VFOEN (VFO ENABLE) Input
"Low level" on this terminal will select built-in VFO (internal).
Otherwise use external VFO IC.
[ 48] MIN (MINI FLOPPY) Input
”HIGH level" on this terminal will select MINI-FLOPPY MODE and
''Ltm-1evel'' will select STANDARD FLOPPY MODE.
In the MINI-FLOPPY mode, data transfer will perform at 250kbps with
4MHz internal FDC clock which is selected by the clock control
circuit In the LSI.
I 49] MFM (MFM MODE) Output
This terminal output will show the mode of operation of FDC. "HIGH
level" on this terminal shows that the FDC works at MFM mode and
otherwise shows FM mode.
f 50-52] NC
INDIWIHN
T08566AF-9
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IITISSHIBA (UC/UP) EL”: 1) la anwauq 002571.31 '?311 DTOSB}
M FLOPPY DISK CONTROLLER
[ 53] -SRSEL (STEP RATE SELECT) Input
When mini-floppy mode, this signal enables to change the internal
FDC clock in accordance with the FDC operation mode. Pull-up
resistor is on-chip.
MIN. -SRSEL -RW/SK FDC OPERATION CLOCK
Low X X Standard mode
High High or X mini mode
non-connect
High Low Low mini mode
High Low High Standard mode
"Low" enables to select ans step rate time for mini-floppy.
[ 54] VSS (GROUND)
Chips ground for digital circuits.
[ 55] SYNC (READ SYNC) Output
Indicate that FDC read out data from FDD, Signal for external VFO
T 56] WDTI (WRITE DATA 1) Output
Pre-compensated write data.
[ 57] WE (“RITE ENABLE) Output
Write enable signal for FDD.
[ 58] HS (HEAD SELECT) Output
Head select signal when LA=High when LA=Low
High Head o Head 1
Low Head 1 Head 0
( 59] HL (HEAD LOAD) Output
FDD head load signal. Low active when LA=Low.
T 60] MENS (MOTOR ENABLE 3) Output
Motor enable for drive M.
( 61] MEN? (MOTOR ENABLE 3) Output
Motor enable for drive #2.
t 62] MENI (MOTOR ENABLE 3) Output
Motor enable for drive #1.
I 63] MENU (MOTOR ENABLE 3) Output
Motor enable for drive #0.
[ 64] V88 (GROUND)
Chips ground for digital circuits.
TC8566AF-1O
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- "sa/ii-: 5 "E3 t:iuc"ririi!v:iuoisiEi/iairlirzFis3-
FLOPPY DISK CONTROLLER Ill]
Tosri:ri3AVchho-,
T 65] VDD (+5V POWER SUPPLY)
[ 66] D83 (DRIVE SELECT 3) Output
Drive select for drive tto.
T 67] DS2 (DRIVE SELECT 2) Output
Drive select for drive #2.
I 68] DSI (DRIVE SELECT 1) Output
Drive select for drive #1.
f 69] DSO (DRIVE SELECT 0) Output
Drive select for drive iN.
[ 70] STP (STEP PULSE) Output
Decoded step pulse signal, connected disk drives.
f 71] FR (FAULT RESET) Output
Decoded fault reset signal, usually used In 8-inch STANDARD FDD.
f 72] LC (LOW CURRNET) Output
Decoded Low current signal, indicates the Head position more inside
than the 43rd track.
T 73] DR (DIRECTION) Output
Decoded direction signal for head seek.
when LA=high LA=low
low Inner seek outer seek
high outer seek Inner seek
I 'ral V88 (GROUND)
Chips ground for digital circuits.
[ 75] VDD (Hill POWER SUPPLY)
I 76] -IDX (INDEX) Input
Index pulse Input from FDD system Interface.
T 77] -RDY (READY) Input
Drive ready signal from FDD system Interface. iiiititit
t 78] NC
I 79] NC
[ 80] --wp (WRITE PROTECT) Input
Write protected Indicate signal from FOO system Interface.
I 81] -28 (2 SIDE) Input
Double sided indicate signal from FDD system interface. Usually use
In the STANDARD tr-inch floppy disk.
TC8566AF-11
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TOSHIBA (UC/UP) ELIE, 1) émevaw Miela'715 sun DTOSB
(ilirLoPrvr DISK CONTROLLER
82] -FLT (FAULT) Input
Fault states Indicate signal from FDD system interface. Usually use
in the STANDARD 8-1nch floppy disk.
83] -TKO (TRACK ZERO) Input
Head position Indicate signal from FDD system Interface. Low level
on this terminal means that the head of FDD is on the TRACK #0
position.
84] PSI (PRE- SHIFT I) Output
85] PSO (PRE- SHIFT 0) Output
Raw signal from internal FDC chip. External pre-compensation circuit
will use this signal as follows
PSO PSI PRE-SHIFT OPERATION
low high Late
low low Normal
high low Early
86] DSB (DRIVE SELECT B) Output
87] USA (DRIVE SELECT A) Output
Undecoded drive select signal on the output of DSS-DSO.
DSB DSA selected drive
low low Drive #0
low high Drive #1
high low Drive #2
high high Drive #3
88] LA (LOW ACTIVE) Input
Physical active level select on the output or FDD system Interface
signal, that is WDTI, WE, HS, HL, MENU - MENS, DSO ... DSO, STP, FR,
LC, and DR. High level on this terminal means that these signal will
low active and can connect to directly FDD which has CMOS type of
Interface specification.
89] NC
90] VDD (+5v POWER SUPPLY)
92] CDS (CONTROL DRIVE SELECT) Input
When this terminal is high level, DSB and DSA bits in a control
register are used as a drive select code. And when CDS ls low level,
U81 and USO outputs from internal FDC are used as a drive select
93] RESET (RESET) Input
Reset control registers, The (-FRS'I'l bit on the control register #0
" also reset, and consequently the Internal FDC block is reset.
T08566AF-12
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Inf o" E17 -crifri'Ey/J, 30727577711757 nu? I:1T0§3
FLOPPY DISK CONTROLLER [H]
TOSHIBA (UC/UP)
[ 94] SHB (SHIFT SELECT B) Input
[ 95] SHA (SHIFT SELECT A) Input
Select Input for phase shift range of the write pre-compensation.
S h 1 f t r a n g e
SHB SHA MIN mode (5.251nch) STD mode (81nch)
low low 125ns 62.5ns
low high 250ns 125.0ns
high low 375ns 187.5ns
high high 500ns 250.0ns
f 96] -SHEN (SHIFT ENABLE) Input
If high level on this terminal, no pre-compensation shifting will be
f 97] STNBY (STANDBY STATE) Output
This signal shows that FDC-II is in a standby mode. In a standby
mode, all internal clock is stopped for save power dissipation and
following signals are inactive states,
won. WE, HS, HL, MENU -MEN3, DSO - Dse, STP, FR, " and DR.
[ 98] WDT (WRITE DATA) Output
Raw signal from internal FDC block. This signal made up of clock
bits and data bits.
T 99] ENID (ENABLE INT and DREQ) Output
Side output of ENID bit in a Control register.
[100] C4 (CONTROL BIT 4) Output
Output of C4 bit in a control register.
TC8566AF-13
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TOSHIBA (UC/UP)
5 DESCRIPTION
but 1)
lil] FLOPPY DISK CONTROLLER
5.1. CONTROL REGISTER AND PERIPHERAL CIRCUITS
5.1.1. REGISTER AND ADDRESS
QU97299 UUEE?L?
Selection
><><><><><><>
><><><><><><
><><><><><><>
><><><><><><><>
><><><><><><><3>
SELECTION
CTL REG. o
CTL REG. 1
FDC STATUS REG.
FDC DATA REG.
SELECTION
High=High Level, Low=Low level, XtDon't care.
CTL REG. 0 l
CTL REG. 1 l
5.1.2. CONDITION OF STANDBY STATE
Control register 0
Control register 1
LSI will enter Into standby mode after several times elapsed, when the
SBM bit In the control register 0 is set to '1' and following conditions
are filled. The waiting time is decided by the state of internal FDC
mode. Usually, thtttt to 8ms In MINI floppy mode and ams to 4ms in STANDARD
floppy mode. Additional condition Is as follows.
0 -FRST bit of control register = 1.
0 Head " unloaded.
o FDC itt in the state that waiting command from the host.
The standby state will show with the output terminal [STNBY], and X'tal
oscillation stops. Standby state allows the drive output signals, W,
HS, FR,STP, LC and DR to he inactive.
LSI will take off from the standby state when one of following condition
is detected.
0 SBM bit is set to 0.
o -FRST bit is set to o,
o FDC receives a command.
TC8566AF-14
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TOSHiBA EUE7UP)‘
5.1.3. CONTROL REGISTER o
This register
terminal will
iid 64 E: s0972us 0025713 PIT EJTOSB
FLOPPY DISK CONTROLLER "H
is 8 bits write only register. High level on the [RESET]
course all bits to O.
BITS SYMBOL NAME MEANINGS
D7 "ENS Motor enable #3 Radial motor on signal for #3 Drive
D6 MEN2 Motor enable #2 Radial motor on signal for " Drive
05 MENI Motor enable #1 Radial motor on signal for #1 Drive
04 MENU Motor enable #0 Radial motor on signal for ito Drive
D3 ENID Enable INT 8 DMA Request INTRO and DRG? are enabled when this
bit is High level.
D2 -FRST Not FDC RST 0 on this bit will reset the internal
FDC block. For normal operation, this
bit should be set to 1.
D1 DSB Drive select B
DO DSA Drive select A 2 bit binary coded Drive select.
input is high level.
This code " effective when the [CDS]
5.1.4 CONTROL REGISTER 1
This register is 4 hits write only register. High level on the [RESET]
terminal will course all bits to 0.
BITS SYMBOL NAME MEANINGS
D7 N86 ENABLE C6 When 1 is applied to this bit during
byte write operation of this register,
the value of C6 becomes to Mi, When 0
is applied to this bit during byte
write operation of this register, the
value of C6 is to be copy of C6.
D6 C6 CONTROL 6 General purpose output port "ml.
D5 ENB4 ENABLE c4 write enable of c4 i.e. cs
D4 OI CONTROL 4 General purpose output port [C4]
D3 ENB2 ENABLE C2 Write enable of C2 i.e. C6
D2 SBM STANDBY when 1 is applied to this bit, FDC
MODE enabled to transfer into stand by mode.
DI ENBO ENABLE C0 write enable of CO i.e. C6
DO FDCTC FDC Terminal FDC terminal count control bit. This
Count bit will be used to terminate data
transfer with Non-DMA mode.
T08566AF-15
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TOSHIBA (UC/UP) EHE D C: 9097399 UUEE7lq ISI, EJTOSB
llll FLOPPY DISK CONTROLLER
5.1.5. THE RELATION BETWEEN ENID, INT, INTRO, DRQ, DR02
Control
Register!) ENID f> D ENID
INT (> CCI INT
FDC -czcy----l>----C] INTRQ
Delay -==cCy----->------Cn DRQ2
cr-- El DRQ
5.1.6. THE RELATION BETWEEN ENID. -DACK2, DMATC, FIWN
Control
Register 0 EN ID
--DAcK2lD-----------l>o Cy, FDC
TC BLOCK
DMATCE]
Control
Register 1 F D c T C
TC8566AF-16
El ll l
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-ni/:i;-i.cri3hjuc%in - - ELIE 1) 1:1 “IBEWELI‘I i3l3ii?la'?ii!rl T78 IZITOSB
FLOPPY DISK CONTROLLER llll
5.2. FDC BLOCK
5.2.1. FDC BLOCK DIAGRAM
DD"? ( _ : tc';',: ( ) REGISTER
SERIAL WE
INTERFACE PSI
DRQ qF--- CONTROLLER RDT
4: 0 DW
-DAC ->c, E -
INT----- a O SYNC
N O VFORST
-IOR->cy m .4
-ioW->c) t .4 ( )
AO---' n: o
tit a:
TC---- 's, - RDY
RST-ir < o m WP/ZS
IL! 0 kl
a: Lu .4 IDX
f t 3 FLT/TKO
-cs t E:
CLK----- - _ USO
c: USl
VDD----- m F, 0 MFM
' D 0.
vSS---ir t-q Ch --RW/SK
D: (- HL
Ct D HS
0 LC/DR
FR/STP
T08566AF-17
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lili FLOPPY DISK CONTROLLER
5.2.2. FDC'S REGISTER AND CPU INTERFACE
FDC has two 8-bit registers accessible by the main system processor. One
is a Main Status Register, and the other is a Data Register. The Main
Status Register indicates the status information of the FDC and is always
accessible.
The Data Register Is used for data transfer between the F00 and the main
processor. Command bytes are written into the Data Register In order to
program the FDC, and also Status bytes are read out of the Data Register
In order to obtain the result after execution of the commands.
Main Status Register may be read and ls used to facilitate the data
transfer between the processor and the FDC. The relationship between Main
Status Register and T-loft/Html and [A0] signals ls shown below.
f-CSI [A0] [~IOR] [-IOW] FUNCTION
H X X x Non Select
L L L L Illegal
L L L H Read Maih Status Register
L L H L Illegal
L H L L Illegal
L H L H Read from Data Register
L H H L Write into Data Register
Each bit in the Main Status Register are defined as Table 5.2.2. The ROM
and D10 bits in the Main Status Register Indicate whether Data Register
is ready or not and In which direction data will be transferred on Data
DI o I l
c-. I OW]
Ll —Ll
[- 10R]
la IBLAII 570 DIG IBIA
Fig.5.2.2. Main Status Register Timing
A: (DIO="Low" and RQMa"HIgh") The processor may write the data In Data
Register.
B: (RQM="Low") Data Register ls not ready.
Ct (D10=''High'' and RQM="High") In data register, data byte which will be
read out by processor is already prepared.
TC8566AF-18
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Table 5.2.2. Main Status Register
BIT SYMBOL NAME MEANING
D7 ROM REQUEST Indicates that Data Register is ready to send
for the data to or to receive the data from the
MASTER processor.
D6 010 DATA Indicates the direction of data transfer between
INPUT/ Data Register and the processor.
OUTPUT When D10 is a "High", transfer is fron Data
Register to the processor. When 010 is a "Low",
transfer from the processor, to Data Register.
Mi NDM Non-DMA Indicates that the FDC " Non-DMA node. It is
node set only during Execution-Phase 1n Non-DMA mode.
D4 CB FDC Indicates that FDC is in Execution-phase of a
BUSY read/write command ' 1n Command-Phase, or In
Result-Phase .
D3 D38 FDD 3 FDD number 3 itt In the Seek mode,
D2 028 FDD 2 FDD number 2 Is in the Seek mode.
D1 013 FDD 1 FDD number 1 is In the Seek node.
D0 DOB FDD 0 FDD number 0 is in the Seek node.
FDC supports fifteen different connands. Each of commands is initiated by
a nulti-byte transfer from the processor, and the result after executing
of the command is a nultl-byte transfer to the processor. Because the
gtulti-byte information ls interchanged between the FDC and the ProcessorI
It is regarded that each command consists of following three phases.
Commands-Phase .. The FDC receives the necessary information to perform
a particular operation free the processor.
Execution-Phase '. The FDC performs the specified operation .
Result-Phaae l After the operation Result Status infernation or
other information Is sent to the processor.
In the Command-Phase or the Result-Phase, the processor must read out the
Main Status Register before each byte of infatuation is written into or
read out from the Data Register.
When each byte of the command and the parameter is written into the FDC,
bit D7 and 06 In the Main Status Register nust be In high level and low
level, respectively.
Because most of the Commands need multiple bytes, the Main Status
Register must be read out before each byte is transferred to the FDC. In
the Result-phase. the bit D7 and D6 In Main Status Register must be both
in high levels before each byte is read out fron the Data Register.
The reading out of the Main Status Register before each byte transfer to
the FDC is necessary only in the Ctmgtand-Phatte and the Result-Phase, but
it is not always necessary in the Execution-Phase.
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When the FDC is In Non-DMA mode, the receipt of each data byte (if the
FDD is now reading out data from the POD) is indicated by the Interrupt
signal.
The generation of the Read signal ([-IOR]=0) will not only output the
data on the data bus but also reset the INT signal. If the processor can
not deal with interrupts fast enough (within iaus for MFM mode.), then it
examines the Main Status Register, and then bit 7 (ROM) functions Just
like the Interrupt signal. Similarly In the Write command, Write signal
resets the Interrupt signal.
If the FDC is in the DMA mode, then the Interrupt signal is not generated
during the Exetoutitm-Phase, When the each data byte is available, the FDC
generates DRQ(DMA request) signal. Then the DMA controller generates both
DMA Acknowledge signal and Read signal ([-DAC]=0 and [-IOR]=0).
In a Read command, when the DMA acknowledge signal becomes low level, the
FDC automatically resets the DRQ. In a Write command, [-Itml is
substituted for [-IOR]. If the Execution-Phase is terminated (Terminal
Count has been inputted), the Interrupt request ls generated. This means
the beginning of the Result-Phase. When the first data byte is read
during the Result-Phase. Interrupt signal is automatically reset. During
the Result-Phase, all data bytes shown in the COMMAND TABLE must be read.
For example, the READ DATA COMMAND has seven data bytes In the Result-
Phase, All seven data bytes must be read out In order to complete the
READ DATA COMMAND. This FDC will not accept the next command until all
these seven data bytes are read out. In the same way, all the data bytes
of the other commands must be read out during the Result-Phase. The Foo
has five Status Registers. The Main Status Register mentioned above can
always be read out by the processor. The Other four Result Status
Register (STO,ST1,ST2,ST3) is available only in the Result-Phase, and
read out only after the termination of the command .
The specified command determines how many the Result Status Registers
will he read. The COMMAND TABLE shows the data bytes that are sent to the
FDC In the thmmand-Phase and read out from the FDC In the Result-phase.
That is, the command code must be sent first, and the other bytes must be
sent in order. So the Command-Phase and the Result-Phase can not be
shorten. When the last data byte in the Command-Phase is sent to the FDC,
the Execution-Phase automatically starts. Similarly, when the last byte
in the Result-Phase is read out, the command is automatically terminated,
and then the FDC is ready for a new command.
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5.2.3. POLLING FEATURE OF THE FDC
After the SPECIFY COMMAND has been sent to the FDC, the drive select
signals , the USI and uso, are automatically In the polling mode.
Between the commands (and between the step pulses In the Seek mode), the
FDC checks the four, FDDs looking for a change of the ready signals from
drive units.
If the Ready signal is changed, then the FDC generates the Interrupt
signal. After the processor has Issued the SENSE INTERRUPT STATUS
COMMAND, the Result Status Register 0 (STD) is read out, and the Not
Ready bit (NR) In STD shows the present status. Because of the polling of
Ready signal between the Commands, the processor can notice which drives
are on line or which drives are off line.
T08566AF-21
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5.2.4. TRACK FORMAT (IBM FORMAT)
lhDEX _J_I_ l I
Gama SYNC Iill cm i' Gapdb
TE" '00' 'N' 'W' SECTOR SEW SECTOR SECTOR 'IT'
FM 1 2 . . ' i" n
x40 x6 x1 x26 t
'4ly '00' 'c2' m 'us' SECTOR SECTOR sacm SWNll '4ry
MFM 1 2 . . ' n
x80 x12 x3 x1 x50
REPEAT ''"ss,.,,
UNTIL .........
, t DAM DATA GAP3
SYNC IDAH C II R ll ceo Cam 3th (DDAH) tl CRC tt
'00' 'FE' 'FF' '00" 'IB' TF'
FM (TC)
x6 x1 x1 x1 x1 x1 x2 x21 yi) xt M
'N' 'ht' Tli' '4E' '00' 'ht' TB' '4E'
MFM ('F8')
x12 " x1 x1 x1 x1 x1 x? x22 x12 " x1 x2
(tl) PROGRAMBLE
MISSING CLOCK PART OF ADDRESS MARK
FM MFM
Data Clock Data Clock
1AM FC D7 C2 14
IDAM FE C7 A1 0A
DAM FB C7 A1 OA
DDAM F8 C7 A1 oh
T08566AF-22
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TOSHIBA (UC/UP) ENE Di I: ciicrFirvri' 002577557 5511.7 Erfiyii,
FLOPPY DISK CONTROLLER (ill
5.2.5. MPH RULES
The data bit is written where the each bit will correspond to the center
of the bit sell with "I". The clock bit is written at the head of the bit
cell with "0" whose previous bit cell has "O".
BIT CELL 1 1 o o 1 0 O 0 1 O o 0
-——— U
———- o
D:DATA BIT
C:CLOCK BIT
Fig.5.2.5. MFR Rules
TCB566AF-23
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(Ill FLOPPY DISK CONTROLLER
5.2.6. COMMAND
(x=Don't care)
READ DATA COMMAND
I) EH QUQ?EHH 002572?
Phase R/W D7 D6 D5 D4 D3 D2 DI D0 Remarks
MT MFM SK o 0 1 1 0 Command code
x x x x It HS DSI DSO
C * ID Information of
H * starting sector
C W R x of command
N * execution
E Data transfer
R R C * ID information
H x of end sector
R x of command
N * execution
WRITE DATA COMMAND
Phase R/w DT Mi D5 D4 D3 D2 D1 D0 Remarks
MT MFM 0 0 0 1 0 1 Command code
x x x x It HS DSI DSO
C * ID Information of
H 1 starting sector
C w R m of command
N * execution
E Data transfer
R R c * ID information
H x of end sector
R t of command
N t execution
TC8566AF-24
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“RITE DELETED DATA COMMAND
Phase R/W D7 D6 D5 D4 D3 D2 DI DO Remarks
MT MFM 0 0 1 0 0 1 Command code
x x x x x HS DSI DSO
C * ID Information of
H * starting sector
C W R t of command
N * execution
E Data transfer
R R C * ID infornation
H t of end sector
R t of command
N * execution
READ DELETED DATA COMMAND
Phase R/W DT D6 D5 D4 D3 D2 DI D0 Remarks
MT MFM SK 0 1 1 0 0 Command code
x It x x x HS DSI DSO
c * ID information of
H x starting sector
c W R t of command
N * execution
E Data transfer
R R C * ID information
H t of end sector
R t of command
N x execution
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READ DIAGNOSTIC COMMAND
Phase R/w D7 D6 05:04 D3 D2 D1 DO Remarks
o MFM o 0 0 o 1 o Command code
x x x x x HS DSI DSO
C * ID information of
H * starting sector
c H R x of command
N . execution
E Data transfer
R R c * ID information
H t of end sector
R t of command
N * execution
READ ID COMMAND
Phase R/if D7 D6 D5 D4 D3 D2 D1 D0 Remarks
C w 0 MFM 0 0 1 0 1 0 Command code
x x It It It HS DSI DSO
E Data transfer
R R C * The first correct
H * ID information
R t read out during
N * Exeteution-Phastt
TC8566AF-26
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FLOPPY DISK CONTROLLER (Ill
FORMAT COHHAND
DI DO Renar
1 1 0 1 Conman code
x HS DSI DSO
Data trans er
* No meaning in
this case
SCAN EQUAL COMMAND
Phase R/W D7 D6 D5 D4 D3 D2 D1 DO Remarks
MT MFM SK 1 0 0 O 1 Command code
x x x x x HS DSI DSO
C * ID information of
H * starting sector
c W R t of command
N * execution
E Data transfer
S'f2 _______
R R C * ID Information E
H * of last compared Miifiiif
R * sector ---'_--'
TC8566AF-27
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1lll FLOPPY DISK CONTROLLER
SCAN LOW nr EQUAL COMMAND
Phase R/w D7 D6 D5 D4 D8 D2 DI DO Remarks
MT MFM SK 1 1 0 0 1 Command code
x x x x x HS DSI DSO
C * ID information of
H ' starting sector
C W R * of command
N * execution
E Data transfer
R R C * ID Information
H * of last
R * compared sector
SCAN HIGH or EQUAL COMMAND
Phase R/W D7 D6 D5 D4 D3 D2 DI DO Remarks
MT MFM SK 1 1 1 0 1 Command code
X x It x x HS DSI DSO
c * ID information of
H * starting sector
C W R * of command
N * execution
E Data transfer
R R C * ID Information
H t of last
R * compared sector
T08566AF-28
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FLOPPY DISK CONTROLLER llli
SEEK COMMAND
Phase R/W D7 D6 Mi D4 D3 D2 DI DO Remarks
0 0 0 0 1 1 1 1 Command code
C W x x x x x x DSI DSO
E Seek
RECALIBRATE CONMAND
Phase R/W D7 06 D5 D4 D8 D2 DI no Renarks
C Ir 0 o 0 0 o 1 1 1 Command code
x x x x x x DSI D30
E Recalibrate
SENSE INTERRUPT STATUS COMMAND
Phase R/W D7 D6 D5 D4 D3 D2 DI DO Remarks
c W 0 0 0 0 1 o 0 0 Command code
R R STO
SPECIFY COMMAND
Phase " D7 D6 D5 IM 03 D2 D1 DO Remarks
o 0 0 0 0 0 1 1 Command code
C W SRT I HUT
HLT I ND
TC8566AF-29
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llll FLOPPY DISK CONTROLLER
SENSE DEVICE STATUS CONHAND
Phase R/w D7 D6 D5 D4 D3 D2 DI DO Remarks
C w 0 0 0 0 0 1 0 0 Command code
x x x x x HS DS1 DSO
R R ST8
INVALID COMMAND
Phase R/W D7 D6 D5 D4 D3 D2 DI D0 Remarks
C w Invalid codes
R R STO S'N=80H
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FLOPPY DISK CONTROLLER lili
Table 5.2.6. Syubols in the COMMAND TABLE
SYMBOL NAME DESCRIPTION
C Cylinder Indicates the cylinder number.
Number
D Data Indicates the data pattern which is going to
be written into data field.
D7-DO Data Bus 8 bit data bus ' D7 is MSB and no is LSB.
DSI,0 Drive Indicates the drive nunber(0,1,2,3).
Select
DTL DATA IF N=00, indicates' the data length per
Length sector which is going to be processed.
EOT' End of Indicates the last Sector of a cylinder.
GPL Gap Indicates the length of Gap 3 (see 5.2.4.
Length Track Format ).
H Head Indicates the logical head address.
Address
HS Head Indicates the physical head address.
Select
HLT Head Indicates the head load tine of FDD defined
Load by Specify Command.
HUT Head Indicates the head unload tine after a read
Unload or write operation has completed which is
Time defined by Specify Connand .
HEM NFM 1f "Lott" ' FM node is selected. If "High",
node MFM node is selected.
MT Hulti If "High" ' multi track operation is to be
Track performed.
N Number N is the code which indicates the nunber of
data bytes written in a sector.
NON New Indicates the new cylinder number to be
Cylinder reached as a result of the seek operation.
Number
ND Non-DMA Indicates the Non-DMA node. Defined by the
Specify Command.
PCN Present Indicates the cylinder number when the Sense
Cylinder Interrupt Status Command has completed.
Number
R Record Indicates the sector number.
R/W Read/ Indicates Whether Read or White.
Stl Sector indicates the number of sector per cylinder. 5222555
SK Skip Indicates the skip of the sector which has --_
DDAM or DAM.
SRT Step Indicates the step rate of FDD which is
Rate defined by Specify Command.
T08566AF-31
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MFLoPPlf DISK CONTROLLER
SYMBOL NAME DESCRIPTION
ST? Step During the Scan operation , " ST? is "I'',
then data In contiguous sector is compared
byte by byte with data sent from the
processor ,and if STP is "a" ,then alternate
sectors are read and compared.
T08566AF-32
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5.2.7. COMMAND DESCRIPTION
During the Command-Phase. the CPU must examine the Main Status Register
before the writing of the each data byte into the Data Register. The D10
and ROM in the Main Status Register must be In a low level and a high
level ' respectively ' before each byte is written into the FDC.
READ DATA COMMAND
The FDC needs nine data bytes in order to execute the READ DATA COMMAND.
After the READ DATA COMMAND has been Issued, the FDC loads the head (if
it is in unload state), and waits the specified head load time . After
the head load tine has passed, the FDC begins to search ID Address Marks
and read ID fields. If ID information stored in the ID Register agrees
with ID information in ID field read from the diskette, then the FDC
outputs data from the data field byte-by-byte to the main system via the
data bus.
After the read operation of the current sector has been conpleted, the
Sector' Number (R) is Incremented by one ' the FDC reads the data fron the
next sector ' and outputs the data on the data bus.
This continuous read function is called a "Multi-Sector Read Operation".
The READ DATA COMMAND may be terminated by receiving a Terminal Count
(TC) signal. If the FDC receives a Tc signal, the FDC stops outputting
data to processor, but continues to read data from the current sector,
and checks the CRC(Cyclic Redundancy Code) bytes, and then terminates the
READ DATA COMMAND at the end of the sector.
The amount of data which can be handled with a single command to the FDC
depends on MrfMtnti-Trraclt), MFM(MFM/FM), and N(Number of bytes/sector).
The Transfer Capacity is shown In Table 5.2.7A. below.
Table 5.2.7A. Transfer Capacity
Maximum Transfer Capacity
" MPH N Bytes/Sector Nunber of Final Sector
Sector
0 0 00 128 26 SIDE O SECTOR 26 or Wr-.:.----'-'------:--:;
1 01 256 SIDE 1 SECTOR 26 8itiiNi
1 0 M 128 52 SIDE 1 SECTOR 26 ----
1 01 256
0 0 01 256 16 SIDE 0 SECTOR 15 or
1 02 512 SIDE 1 SECTOR 15
1 0 01 256 30 SIDE 0 SECTOR 15
1 02 512
o 0 02 512 8 SIDE o SECTOR 8 or
1 03 1024 SIDE 1 SECTOR 8
1 0 02 512 16 SIDE 1 SECTOR 8
1 M 1024
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llll FLOPPY DISK CONTROLLER
This FDC can read out the data from both sides of the diskette by the
Multi-Track function. Data transfer will be performed from the Sector 1
of Side 0 to the last Sector of Side 1 for a particular cylinder at a
time. But this function is effective to only one cylinder of the
diskette.
After the reading out of the last sector, the FDC must receive the
Terminal Count. If the FDC does not receive the Terminal Count signal.
then the FDC sets the EN(end of cylinder) flag of M'I to a high level and
terminates the READ DATA COMMAND (bits 7 and 6 or STO is also set to a
low level and a high level respectively t abnormal termination).
When N=0, DTL defines the data length which the FDC must treat as a
sector. 1F DTL is smaller than the actual data length In a sector, the
data beyond DTL in the sector is not sent to the data bus, but the FDC
reads the whole sector Internally, and then checks CRC bytes. When wo
DTL has no meaning.
Wen the READ DATA COMMAND has been completed , the head is not unloaded
until the Head Unload Time(specified in the Specify Command) has passed.
When the processor issues the next command (a read/write command) before
head is unloaded, the head load time of the command is saved.
If the FDC can not find out the right sector until the FDC detects the
Index Hole twice, the FDC sets the ND(No Data) flag in STI to a high
level, and the READ DATA COMMAND will be abnormal terminated (bit 7 and
bit 6 in STO set to a low level and a high level respectively).
After the reading of the ID field and the data field of the each sector,
the FDC checks the CRC bytes. If a read error (incorrect CRC bytes in the
ID field) is detected, the FDC sets the DE(Data Error) flag of BTI to a
high level, and if data error in the data field is detected ' the DD(Data
Error in Data Field) flag In ST2 is set to a high level, and then the
READ DATA COMMAND is abnormal terminated.
IF the FDC read a Deleted Data Address Mark In the diskette, and SK bit
(05 bit In the Command code)is not set, then the FDC sets CM (Control
Mark) flag to a high level after reading out all the data in the sector,
and terminates the READ DATA COMMAND. When SK-l, the FDC skips the Sector
that has DDAM, and reads out the next sector.
During the'data transfer between the FDC and the processor, the FDC must
receive the service from the processor within 27us in FM mode, and 13 us
in MFM mode. If the FDC does not receive this service, the FDC sets OR
(Over Run) flag to a high level, and terminates the READ DATA COMMAND
(abnormal termination).
If a read (or write) operation is terminated by inputting the Terminal
Count signal, the information of Result-Phase is defined by MT bit and
EOT byte. Table 5.2.78. shows the value for C,H,R and N when the command
is normally terminated.
TC8666AF-34
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TOSHIBA (UC/UP)
Table 5.2.78 ID Infornation at Nornal Ternination
MT EOT Final Transferred Sector ID Information in Result-Phase
c H R N
1A Sector 1 to M at Side 0
OF Sector 1 to 14 at Side 0 NC NC R+1 NC
08 Sector 1 to 7 at Side 0
IA Sector 26 at Side 0
OF Sector 15 at Side 0 C+1 NC R=01 NC
0 M Sector 8 at Side 0
1A Sector 1 to 25 at Side 1
OF Sector 1 to 14 at Side 1 NC NC R+1 NC
08 Sector 1 to 7 at Side 1
1A Sector 26 at Side 1
OF Sector 15 at Side 1 C+1 NC R=01 NC
08 Sector 8 at Side 1
1A Sector 1 to 25 at Side 0
OF Sector 1 to 14 at Side 0 NC NC R+1 NC
08 Sector 1 to 7 at Side 0
1A Sector 26 at Side o
OF Sector 15 at Side 0 NC LSB R201 NC
1 08 Sector 8 at Side o
IA Sector 1 to 25 at Side 1
OF Sector 1 to 14 at Side 1 NC NC R+1 NC
08 Sector 1 to 7 at Side 1
1A Sector 26 at Side 1
OF Sector 15 at Side 1 tHI LSB R=01 NC
08 Sector 8 at Side 1
Notes) NC(No Change): The same value as the one at the
beginning of connand execution.
LSB(Least Significant Bit): The least significant bit of H is
conplenented.
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MUTE DATA COMMAND
The FDC needs nine data bytes in order to execute the WRITE DATA COMMAND.
If the WRITE DATA COMMAND has been Issued, the FDC loads the head (if the
head is In the unload state). After the specified head load waiting
time(defined In the SPECIFY COMMAND) has passed, the FDC begins to read
the ID field. If the sector number stored in ID Register (IDR) matched
with the sector number read from the diskette, then the FDC takes data
from the processor byte-by-byte via the data bus, and outputs to the FDD.
After the writing the data into the current sector, the FDC increments
the sector number stored in R by one, and then the FDC writes the next
data field. The FDC continues this 1tit1ti-Seotots write operation until the
Terminal Count signal is issued. Even if the FDC has received the
Terminal Count signal, the FDC continues writing for the sector, and the
data field will be completed. If the FDC receives the Terminal Count
signal while the FDC ls writing data in data field, then the remained
data field will be filled with 00.
The FDC reads out the each sector of ID field, and checks the CRC bytes.
If the FDC finds out the Read Error in ID field (incorrect CRC bytes),
the FDC sets DE (Data Error) of STI to a high level, and terminates the
WRITE DATA COMMAND(Abnornal termination).
The rules of the WRITE COMMANDS are much similar to the rules of the READ
DATA COMMAND. The following items are same t see the previous section
(5.2.1).
Transfer Capacity
EN flag
Head unload time
ID information at the normal termination
Meaning of MIL when N=0 and when tot 0
During the execution of the WRITE DATA COMMAND, the data transfer between
the processor and the FDC must be performed within 31us in FM mode, and
15us in MFM mode. If it is not performed, the FDC sets OR flag of STI to
a high level, and terminates the command (Abnormal Termination).
“RITE DELETED DATA COMMAND
This command is the same command as the WRITE DATA COMMAND except that
the FDC.writes the DDAM (Deleted Data Address Mark) at the beginning of
the Data Field Instead of the normal DAM (Data Address Mark).
READ DELETED DATA COMMAND
This command is the same as the READ DATA COMMAND except that the FDC
reads the sectors with DDAM instead of those with DAM at the beginning of
a Data Field. if the FDC detects DAM and SK=0 ,then the FDC will read the
whole sector and set on flag in ST2 to a high level and terminate the
command (Normal Termination). 1f the FDC finds out DAM and SK=1 then the
FDC will skip the sector with DAM and read the next sector.
T08566AF-36
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GE o" II! m3'T?iy4''1 UDEE?L|D ?bl: CITOSEI 7
FLOPPY DISK CONTROLLER illl
_riy:ni:rL 7(VUC/UP)
READ DIAGNOSTIC COHMAND
This command is the same as the READ DATA COMMAND except that the FDC
reads all the data Continuously from each sector of a track. Just after
the FDC receives the Index signal, the FDC begins to read out all the
data field on the track as a continuous block. Even " the FDC finds oht
the CRC error in ID or data Field, the FDC continues to read data from
the track. The FDC compares the ID infatuation read out from each sector
with the value stored in IDR, and " there is no comparison, the FDC sets
ND flag to a high level. This conmand has neither the Multi-Track
function nor the skip function.
This comnand will be terminated when EOT number of sectors have been read
out. Wen ID Address Mark on the diskette is not found out until the FDC
finds out the Index Hall twice, MA (Missing Address Mark) In tyn is set
to a high level, and the command is terminated0tbnoraa1 Termination).
READ ID COMMAND
This command is used to inform the processor of the current head point.
The FDC stores the first 1D information to be read out. If the right ID
Address Mark is not found on the diskette until the FDC finds out the
Index Hall twice, the FDC sets MA flag In STI to a high level, and if
there is no ID field without CRC error, ND flag in STI " set to a high
level, and the command is ternainated(Ahnorrta1 Termination).
FORMAT COMMAND
The Fornat Connand allows an entire track to he formatted. After the
Index Hall " detected, the FDC writes data on the Diskette. Gaps,
Address Marks, ID fields and Data fields in IBM System34 (double density)
or IBM Systen3740 (single density) Fornat are recorded. The particular
format " controlled by the values programned In N,SC,GPL and D during
the Counand-Phase. The data byte stored in D is written into the data
field. The data bytes of ID field in each sector is provided by the
processor. That is, the FDC requests four data bytes per sector for c, H,
R and N. This function allows the diskette to be formatted with non-
sequential sector numbers.
After the each sector is formatted, the processor nust send the new Eggggg
values of c,H,R and N to the FDC for the next sector on the track. After iittiiiiiii
a sector is formatted, the contents of the R-register is Incremented by
one. Thus, when the R register " read out during the ResuIt-Phase, it
contains a value of R+1. This incrementing and formatting continues for
the track until the FDC detects the Index Hall for the second tine. When
the FDC finds the Index Hall twice, the command is terninated.
When the FDC received the Fault signal from the FDD at the end of the
write operation, the FDC sets the EC flag in STO to a high level, and
sets bit 7 and bit 6 In STO to a low level and a high level respectively,
and terminates the command. If the Ready signal changes to a low level at
the beginning of the connand execution, then the comnand is terminated.
TC8566AF-37
This Material Copyrighted By Its Respective Manufacturer
TOSHIBA (UC/um bHE o" CCI auqvauq mama]. ma EITOSEI
lllyn-os's'Y DISK CONTROLLER
Table 5.2.70. shows the relationship of N, SC and GPL for various Sector
sizes.
Table 5.2.70. Relationship of Sector Sizes
FORMAT SECTOR SIZE N SC GPL
byte/sector (16) (16) (16) REMARKS
FM 128 00 1A IB IBM Diskette 1
mode 256 01 0F 2A IBM Diskette 2
512 02 08 3A
1024 03 M -
2048 M 02 -
4086 05 01 -
MFM 256 01 1A 36 IBM Diskette 2D
mode 512 02 0F 54
1024 M 08 74 IBM Diskette 2D
2048 04 04 -
4096 05 02 -
8192 06 01 -
SCAN COMMAND
The SCAN COMMANDS allow the data read from the diskette to be compared
with the data sent from the Main System (the processor In Non-DMA node,
and the DMA controller In DAM mode). The FDC compares the data byte-hy-
byte, and searches the sector which meets the cond1t10n(equal, low or
equal, high or equal).
After a entire sector is compared ,if the condition " not met, the
sector number is incremented (R+STP)R), and the scan operation is
continued. The scan operation is continued until the following conditions
occur l
o The conditions tor scan are met (equa1,high or equa1,10w or equal).
o The last sector on the track (EOT) la reached.
o The Terminal Count signal is received.
If the scan equal condition are met, the FDC sets SH(Scan Hit) flag in
ST2 to a high level, and then the SCAN COMMAND ls terminated(Norna1
termination).
If the condition for scan Is not met between the starting sector
(specified by R) and the last sector (EOT) on the same cylinder, the FDC
sets the SN (Scan Not Satisfied) flag in 8T2 to a high level, and then
terminates the command. If the FDC receives the Terminal Count from the
processor or the DMA controller during the scan operation, the FDC
completes the conparison of the data byte in process, and then terminates
the command. TABLE 6 shows the status of bit SN and SH under the scan
conditions.
T08566AF-38
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TOSHIBA (UC/UEf - Th: 717:? tuvrzieVn aih,rru' 35% E/iid/
FLOPPY DISK CONTROLLER Ill]
Table 5.2.70. Scan Status Codes
COMMAND ST2 COMMENTS
SCAN 0 1 DISK " MAIN
EQUAL 1 0 DISK f MAIN
SCAN o 1 DISK I MAIN
LOW or o 0 DISK ( MAIN
EQUAL 1 0 DISK y MAIN
SCAN O 1 DISK I MAIN
HIGH or 0 0 DISK y MAIN
EQUAL 1 0 DISK t MAIN
If the FDC finds out the DDAM on the sector and SK=0, then the FDC
regards the sector as the last sector on the cylinder, and sets the CM
flag In S'f2 to a high level, and terminates the command (Normal
Termination). If SKai, the FDC skips the sector with DDAM, and reads out
the next sector. Then the FDC sets CM flag in ST2 to a high level in
order to show that the DDAM is found out. When either MP or MT "
progranmed, the FDC must read out the last sector on the track.
For example, if STP=02, MT=0 and the sectors are numbered In sequence 1
to 26, and SCAN COMMAND is started from the 21 Sector, then the FDC reads
out the sector 21,23,25 and skips the next sector 26 ' and finds out the
Index Hall before reading the EOT value of 26. This result causes the
abnormal termination of the command. If EOT " set at 25 or the scanning
" started at the sector 20, then the connand will be normal ternination.
During the SCAN COMMAND, it is necessary to transfer the data which will
be compared with the data read out fron the diskette to the FDC by
whether the processor or the DMA controller. " the data are not
transferred within 27us in FM node and 13us 1n MPH mode, the FDC sets the
OR (Over Run) flag In STI, and terminates the command (Abnormal
Termination).
SEEK COMMAND
This command is used to move the Read/tmite Head from cylinder to
cylinder. The FDC compares the PCN which is current head position with
the NCN. If there is a difference, the FDC performs the following
operation.
PCN ( NCN t Direction signal to the FDD is set to a high level, and
the Step Pulses are Issued (Step In).
PCN y NON , Direction signal to the FDD is set to a low level, and
the Step Pulses are issued (Step Out).
TC8566AF-39
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TOSHIBA (UC/UP) bHE J) © “IUCNE'LICI unamua L575 IZITOSE
illi FLOPPY DISK CONTROLLER
The rate of outputting the step pulses is controlled by the SRT (Step
Rate Time) In the SPECIFY COMMAND. The FDC compares NCN with PCN at
outputting the step pulses, and if NCN=PCN, then SE (Seek End ) flag in
STO is set to a low level, and the command is terminated. The FDC is in
FDC Busy state during the Command-Phase of this command, but the FDC is
In Non-Busy state during the Execution-Phase of this command. If the FDC
is In Nan-Busy state, the FDC accepts another SEEK COMMAND. This function
allows the FDC to do the parallel seek operation for up to 4 FDDs at a
If the FDD is In the Not Ready state at the beginning of the Execution-
Phase of this command or during the seek operation, the NR (Not Ready)
flag in STO is set to a high level and the command is terminated.
RECALIBRATE COMMAND
The Read/write Head within the FDD is moved to the Track 0 position under
control of the RECALIBRATE COMMAND. The FDC clears the contents of PCN
register, and checks the Track 0 signal. If the Track 0 signal is In a
low level, the FDC sets the Direction signal to a low level, and issues
the Step Pulses.
When the Track o signal changes to a high level, the FDC sets SE (Seek
End) flag to a high level, and terminates the command. If the Track 0
signal is still low after the FDC has issued the 255 Step Pulses, SE flag
and EC flag In STO are set to both high levels, and the command is
terminated. The RECALIBRATE COMMAND is the same as the SEEK COMMAND about
the function to overlap the operation to multiple F009 and about the loss
of the Ready signal.
SENSE INTERRUPT STATUS COMMAND
The FDC generates the Interrupt signal by the following reasons.
1 The beginning of Result-Phase In the Following commands:
a READ DATA COMMAND
b READ DIAGNOSTIC COMMAND
READ ID COMMAND
READ DELETED DATA COMMAND
WRITE DATA COMMAND
FORMAT COMMAND
WRITE DELETED DATA COMMAND
SCAN COMMANDS
2 The change of Ready line of EDD.
3 At the end of the SEEK 0r RECALIBRATE COMMAND.
4 During the Execution-Phase In the Non-DMA mode,
:raqmmgo
Interrupts caused by reason 1 and 4 occur during the normal command
operation, and the processor can notice the interrupts easily. But the
interrupts caused by the reason 2 and 3 may be identified with the
request of issuing the SENSE INTERRUPT STATUS COMMAND. When this command
is issued, Interrupt signal is reset, and bit 5, bit 6 and bit 7 in STO
indicate the reason of the interrupt.
TC8566AF-40
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Lliiiriy) Hua7aua unab?uu IirfE:r/o:id
FLOPPY DISK CONTROLLER llli
TOSHIBA (UC/UP)
Neither the SEEK nor the RECALIBRATE COMMAND has a Result-Phase.
Therefore, it is necessary to use the SENSE INTERRUPT COMMAND after these
conmands in order to terminate then effectively and confirn the head
position (PCN).
Table 5.2.75. SEEK ' INTERRUPT CODES
INTERRUPT CODE SEEK END
BIT 7 BIT ti BIT 5 MEANING
1 1 0 Changing of the state
of the READY LINE
o o 1 Normal Ternination of the
SEEK and RECALIBRATE COMMAND
o 1 1 Abnormal Termination of the
SEEK and RECALIBRATE COMMAND
SPECIFY COMMAND
This SPECIFY COMMAND initiates the values of three internal timers. The
HUT (Head Unload Time) defines the tine from the end of the Execution-
Phase of the read/write commands to the unloading of the head. This timer
is programmable from 16 to 240 ms at intervals of 16 ms (01:16ns,
02=32ms, ... ,0F=240ns).
The SRT defines the time interval between step pulses. This timer is
programmable from 1 to 16ms In increments of Ins (F=1ns,E=2ms ....
,0=16ms). The HLT defines the time from the rising of the Head Load
signal to the starting of the read/write operation. This timer is
programmable fron 2 to 254 ms in Ittttrettettttt of 2ns (01:2ns, 02x4ns,
03-6ns. . . . ,7F=254ms).
The interval times mentioned above are a direct function of the clock.
The tines indicated above are for a 8MHz clock. If the clock frequency is
4MHz (nini floppy), all the tines are twice as long as the times
indicated above.
The ND bit is a flag to select the DMA operation or Non-DMA operation. If
ND " in a high level then Non-DMA node " selected, and if ND is In a
low level then DMA mode is selected.
TC8566AF-41
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TOST-IEBA (UC/UP) ELIE 1) I: cuvririew/m3iisilyus CITosa
Ill] FLOPPY DISK CONTROLLER
SENSE DEVICE STATUS COMMAND
The processor may use this command whenever It wishes to know the status
of the FDDs. The drive status information is contained in ST3.
INVALID COMMAND
If an invalid command (a command not defined above) is send to the FDC,
the FDC terminates the command. The FDC does not generate the Interrupt
signal during the Result-phase. Bit 6 and bit 7 1n the Main Status
Register set to both high levels Indicates to the processor that the FDC
is in the Result-Phase and that the contents of STD must be read out. 8T0
is set to a 80H showing that an invalid command was received.
The SENSE INTERRUPT STATUS COMMAND must be sent after an interrupt of the
SEEK COMMAND or RECALIBRATE COMMAND has occurred, otherwise the FDC
regards this command as invalid. The users may use this command as a Non-
Op command to place the FDC In a stand-by or non-operation state.
TCB566AF-42
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Tosrr:ridd.sd)Goi
77gut7b r/iupiiG/t, ilrisiud%sVrffGsa'
FLOPPY DISK CONTROLLER (ill
5.2.8. RESULT STATUS REGISTER
RESULT STATUS REGISTER O WN)
SYMBOL
DESCRIPTION
Interrupt
D7:0 and Dean
Normal Termination of Command (NT),
Command was completed and properly
executed.
07:0 and D6=1
Abnormal Termination of Command(AT).
Connand execution was started, but
was not successfully completed.
D731 and 06:0
Connand was Invalid Comnand(lc).
The command which has been issued
was not started.
D7=1 and D6=1
This indicates that the Ready Line
from the FDD was changed.
This flag is set to a '1',when the
SEEK COMMAND was completed.
Equipment
When the FDC received the Fault
signal from the FDD, or when the
Track o signal was not set to a "I''
after 255 step pulses during the
RECALIBRATE COMMAND, this flag is
set to a "C'.
When the FDD is In the Not-Ready
state and a read/write comnand is
Issued, this flag is set. For
example, when a read/write connand
is issued for Side 1 of a single
sided drive, this flag is set.
Address
This flag indicates the state of
the head at Interrupt.
Select
These flags indicate the drive
number at interrupt.
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lil! FLOPPY DISK CONTROLLER
RESULT STATUS REGISTER 1 (STI)
BIT SYMBOL NAME DESCRIPTION
D7 EN End of This flag is set when the FDC tries
Cylinder to access a sector beyond the last
sector of a cylinder.
D5 DE Data This flag is set when the FDC finds
Error the CRC Error either In the ID
field or the data field.
D4 OR Over This flag is set when the FDC does
Run not receive the service from the
main system during data transfers
within a certain tine interval.
D2 ND No o This flag ls set when the FDC can
Data not find out the sector specified
In the IDR during the execution of
following commands:
READ DATA
READ DELETED DATA
WRITE DATA
MUTE DELETED DATA
o This flag is set when the FDC can
not find the ID field without the
CRC error during the execution of
the READ ID COMMAND.
o This flag is set when the
starting sector cannot be found
during the executing the READ
DIAGNOSTIC COMMAND.
DI NR Not This flag is set " the FDC detects
Writable the write protect signal fron the
FDD during the executing following
commands:
WRITE DATA
WRITE DELETED DATA
FORMAT
DO MA Missing o This flag is set if IDAM cannot
Address be found out until the FDC finds
Mark the Index Hall twice.
o This flag is set if the FDC can
not find the DAM or DDAM. The MD
flag of 8T2 is also set In this
TC8566AF-44
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TosH:hasuk/uri,
RESULT STATUS REGISTER 2 (8T2)
GE i -r:fcGciFiG'c/u'ii!iFiuus TE? taross/
FLOPPY DISK CONTROLLER HI]
BIT SYMBOL NAME DESCRIPTION
06 CM Control While executing the READ DATA or
Mark the SCAN COMMAND, this flag is set
when the FDC finds out the sector
with the DDAM. During executing the
READ DELETED DATA COMMAND, this
flag is set when the FDC finds out
the Sector with the DAM.
D5 DD Data This flag is set when the FDC
Error In detects a CRC Error in data field.
D4 NC No This flag is set when the contents
Cylinder of C on the nediun is different
fron that stored in the IDR. This
flag is related with the ND flag.
D3 SH Scan This flag is set if the condition
Equal of "equal" is satisfied during the
Satisfied execution of the SCAN COMMAND.
D2 SN Scan This flag is set if the FDC cannot
Not find out the sector which satisfies
Satisfied the condition during the execution
of the SCAN COMMAND.
DI BC Bad This flag is set if the content of
Cylinder C on the nedium is FF and differs
from that stored In IDR. This bit
is related with the ND bit.
DO MD Missing This flag is set if the FDC cannot
Address find out the DAM or DDAM while the
Mark in data are read from the medium.
T08566AF-45
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Tosr/iil (UC/UP) ELIE 1) III 905734"! DDEEWICI Hn3 CITOSB
m] FLOPPY DISK CONTROLLER
RESULT STATUS REGISTER 3 WN)
BIT SYMBOL NAME DESCRIPTION
D7 FLT Fault This bit indicates the state of the
Fault signal from the FDD.
De HP write This bit indicates the state of the
Protect the write Protect signal from the
D5 ROY Ready This bit indicates the state of the
Ready signal from the FDD.
D4 TKO Track 0 This bit indicates the state of the
Track 0 signal from the FDD.
D3 28 Two This bit Indicates the state of the
Side Two Side signal from the FDD.
D2 HD Head This bit indicates the state of the
Address Head Select signal to the FDD.
DI DSI Drive This bit indicates the state of the
Select 1 Drive Select 1 signal to the POD.
DO DSO Drive This bit Indicates the state of the
Select 0 Drive Select 0 signal to the FDD.
T08566AF-46
This Material Copyrighted By Its Respective Manufacturer
TOSHIBA (UC/UP)
5.3. VFO UNIT
EL”: 1) I: cirrrrac/u:Gri%nai:rs
5.3.1. VFO UNIT BLOCK DIAGRAM
FLOPPY DISK CONTROLLER llll
LPF1 LPF2 CONT
i: fi (i)
FM tye CHARGE PUMP
MIN ' CLOCK vco
16MHz 0-) GEN.
WWW - PHASE
-> DIV
DIGITAL --->t
RDT 9-> ONE
SHOT l
SYNC/GAP SEQUENCER
DETECTER Tinnm
.e Adjust
VFORST‘
Fig.5.3.1. VFO Block Diagran
30w I ND
TC8566AF-47
taroid
Ill! “HIM" Nil WIN”!
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HHFLOPPY DISK CONTROLLER
5.3.2. DESCRIPTION OF EACH BLOCKS.
(1) Time base generator/Divider circuit
This block consists of 16MHz crystal oscillator and divider, It
generates all tining signals for VFO operation. The operation mode
MFM and MIN signals change the divisor of these timings.
STD node (500kbps) MINI mode (250kbps)
node MPH 500 KHz 250 KHz
node FM 250 KHz 125 KHz
(2) SYNC GAP DETECTOR/DIGITAL ONE-SHOT
SYNC pattern detect circuit when the FDC begins the read operation.
SYNC pattern '00' is continuance pulse series whose Interval Is
TSYNC. This circuit Judges to be SYNC the pulse series whose
interval " between TSYNC -25% and TSYNC +25x, and the other pulse
series to be GAP. When 16MHz clock ls applied in [XIN] terminal,
the value of TSYNC, TSYNC +25% and TSYNC -25% are as follows.
STD mode (500kbps) MINI mode (250kbps)
TSYNC 2.0 us 4.0 us
TSYNC +25% 2.5 us 5.0 us
TSYNC -25% 1.5 us 3.0 us
Lower limit for MFM mode and upper limit for FM mode are non-sense
for read/wrlte operation but allow to distinguish 500kbps fron
300Kbps. .
Digital one shot circuit works so as to centering the data pulse
with window clock signal. This circuit use doubled [XIN] clock
(16MHz), so it has 31.25 ns quantitized error.
STD mode (500kbps) MINI mode (250kbps)
node MEN 500 ns 1000 ns
mode FM 1000 ns 2000 ns
(3) VOLTAGE CONTROLLED oscillator (VCO)
This V00 is automatically adjust Its center frequency using PLL
circuit. When 16MHz is used for [XIN] clock, 2MHz " the frequency
at VCONT voltage is 2.5V. The conversion gain via voltage on 1ltXW1l
terminal is as follows.
Kv a 2.5 x 10 6 [ rad/sec Ill
(4) TIMING ADJUSTING CIRCUIT
This circuit regenerates data and clock bit In MFM signal so as to
get best read margin against the peak shift phenonenon in the data
from the F00.
T08566AF-48
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T6SQIBA tifch/j
(5) SEQUENCER
-sra:lizh §3é7auhxnnab7sé H66 EJTOSB
FLOPPY DISK CONTROLLER llll
llF0 start its operation with the starting of read request from the
FDC, The sequencer controls all operation that is, hunting SYNC
pattern, detecting address mark, changing PLL filter constant etc..
T08566AF-49
”INN” IIIHH‘IHIWIWI
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llll FLOPPY DISK CONTROLLER
.3. OPERATION FLOV OF VFO
The operation of the VFO part is explained as the combination of the
control mode of each circuit. The mode of each part which concerns the
UFO operation is as follows.
[Phase Comparator]
One Input of the phase comparator is the window signal which is
the divided signal of the VCO output. The other Input is either the
read data or standardized clock from [XIN] whose frequency is the
same as window signal.
There are things to switch the charge pump outputs and to change the
gain of phase comparator in order to distinguish look state from
unlock state of the V00.
[External Input]
SYNC t Input to indicate that the FDC is in read data.
VFORST t Pulse generated by internal FDC when the FDC becomes
SYNC state, and when the first data byte after sync
detection is not address mark and the FDC begins to
search next sync pattern.
VFO has three transition states as follows.
QF t vco is tracing for basic clock from [XIN] 16MHz with high gain.
QH t UCO is tracing for read data with high gain.
QL t VCO is tracing for read data with low gain.
There is SYNC/GAP detector to control state transition except mentioned
above. This circuit always checks read data pulses. If there is a pulse
without regular Interval time. GAP ls outputted. This output is held for
8 bit tine, SYNCD itt outputted when there is no GAP output during 2 byte
time for FM mode or during 4 byte time for MFM mode. Fig. 5.3.3A. shows
VFO states transition flow. Fig.5.3.aB. shows the timing of VFORST which
the FDC outputs.
TCB566AF-5O
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TOSHIBA fucfkup)’ - - - "iarTilrzitilvi'iiiiPn nugsuiagb rzr/ois/
FLOPPY DISK CONTROLLER (Ill
/ SYNC= 1 vhsnc-- 0
WSYNC= 1
SYNC-l k GAP-O
Fig.5.3.3A. VFO States Transition
|| lIRWIN|||IIUI|WH|
TC8566AF-51
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-TO:idifi3a (UC/UP) ENE 1) I: quqvau‘égunamss vi/caros:,
llllF1-oPPy DISK CONTROLLER
(ii) FDC SYNC SEARCH
SYNC SEARCH
External SYNC ON
VFORSTI
Data/Clock
CHANGE
l_______._
Fig.5.3.3B. VFORST Timing
TCB566AF-52
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FLOPPY DISK CoNTRol-LERM
To-s/HHS/i" ?UCZJPT
5.3.4. FILTER CR CONSTANT 0F VFO
When the VFO is used In 2 filter switching mode, the external components
for the low pass filter are needed as follows.
LPF2 -
R3 Gl c2
Fig.5.3.4. Filter Circuit
Recommended CR constant for MIN and STD node is as follows. The accuracy
of component 13 less than 5 x each.
R1 1 K OHM
R2 68 K OHM
M 15 K OHM
M 1 k OHM
Cl 1000 pF
C2 0.01 uF
Also, when the VFO ls used In 1 filter non-switching mode, the external
components for the low pass filter are needed as follows.
LPFI __AA»____#
CONT I
Fig.5.3.4B. Filter Circuit
T08566AF-53
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TOSiHiIBA tuchnoy sh:-, WIZI Avririev, tl0i?la'iHi'? Tla'l' L:aross,
[HIFLOPPY DISK CONTROLLER
Recommended CR constant for MIN and STD mode is as follows.
R1 7.5KOHM
R4 2.7KOHM
C2 0.01 uF
T08566AF-54
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TOSHIBA (UC/UP) W ELIE D I: Havana 0025753 TH:, IZITOSB
FLOPPY DISK CONTROLLER lill
5.3.5. VFO TIME MARGIN
(1) OUTLINE OF TIME MARGIN
Raw data being read from floppy disk drive have dynamic/static data
rate variations on account of the variation in the rotational speed
of disk (for example, wow flatter). 0n high density recording,
magnetic effects cause read data to move to early or late position,
which is called peak shift. Raw read data are Influenced by the
variation in disk speed on both writing and reading. which is
regarded as low speed variation. The VFO is designed to track this
variation. 0n the other hand, it is necessary to reduce the
variation by peak shift, because its frequency is near the data
transfer frequency.
Example: Waveform In case of data 6DB in HEM mode for mini-floppy
DATA BYTE 6 B 2
i)hThBIT 0 l 1 I 1 l o 1 I 0 I 1 I 1 0 I 0 I 1
" l TE C D D D D D C D
IBU I I l I I I I I
Gus 4us _ Rus 8us Ips Bus Gus
PEAK SHIFT
mo I I I
DATA .
‘5.5us I 5us ' 7.5us : 7.5us . hs I 5.5us _ Bus
F13.5.3.5A. Example of Peak Shift
In the example above, there are +0.5us pulse Jitters by peak shift.
The VFO operates to track the variation in disk rotation but to
ignore the variation of this peak shift, and then generates the
WINDOW signal to sample data accurately. The time margin is the
tolerance for the peak shift. This value in the case of an ideal
VFO is a half of the cycle of the bit transfer rate. It is 2us In
MFM mode for mini-floppy (250Kbps).
T08566AF-55
This Material Copyrighted By Its Respective Manufacturer
TOSHIBA (UC/UP) . ENE I) E 309734“! 002E175“! 6Ele
illl FLOPPY DISK CONTROLLER
(2) MEASUREMENT OF TIME MARGIN
There are many measurement methods of the time margin. we select
the MFM data pattern of the repetition of 603 (hex). Because It
contains many worst-case peak shifted data in MFM mode. The MFM
data pattern of the repetition of 608 is shown below.
6 D B b D B
ol1l1lo1l1lol1 1lol1l1 ol1i1lo1L1lol1 1lol1l1
"S ps I I I I I I I I I I I
- -- - -- - --
The measurement of the time margin is performed as follows. The FDC
reads the sector data generated by the pattern generator whose data
field is the repetition of 6DB above. At this time the data is
shifted like peak shifted data with the blt-shift circuit of MFM
data used in pre-compensation. The time margin of the VFO will be
measured by researching the relation between the amount of peak
shift and the read error rate of the FDC.
[RESULTS]
STD/MIN. MFM/FM TIME MARGIN
MFM 0.76 us
STD FM 1.60 us
MFM 1.68 us
MIN, FM 3.40 us
TCB566AF-56
This Material Copyrighted By Its Respective Manufacturer
-duT:hrTzrciivrizv:, tiioiiirsdisirTi:i"irisi/-
FLOPPY DISK CONTROLLER lill
TOSHIBA (UC/ubi
8. ELECTRICAL CHARACTERISTICS
6.1. ABSOLUTE MAXIMUM RATING
Ws = 0V
ITEM SYMBOL RATING UNIT
Power Supply Voltage VDD -0.5 to +7.0 V
Input Voltage VIN Vss-O.5 to VDD+0.5 V
Operation Tenperature topr -40 to +85 t
Storage Tenperature tstg -65 to 125 t
Output Current IOUTl +2.0 OI) ttA
Output Current IOUT2 +8.0 (et) ttA
Output Current IOUTa +3.0 (*3) nA
Power Dissipation pd 300 "
Comment : " XOUT
t2 ttDTI, WE, HS, HL, HENS - MENO, Dsa - DSO, STP, " and DR.
" Others.
6.2. RECOMMENDED OPERATION CONDITION
Pas = 0V
ITEM SYMBOL MIN. MAX. UNIT
Operation Tenperature topr -40 +85 'te
Power Supply Voltage 1ID0 4.5 5.5 V
Clock Frequency f0 15.5 16.5 MHz
TC8566AF-57
This Material Copyrighted By Its Respective Manufacturer
TOSHIBA (UC/UP)
(lllr'i-or'r'y DISK CONTROLLER
8.3. DC CHARACTERISTICS
VDD=5.0tIO% . VSSIOV
ELIE 1) I: Havana 00213761. wid IZITOSB
Ta=-40 t to ttttit
ITEM SYMSOL MIN. TYP. MAX. UNIT
Hysterlsls (*3) 1IHS3 0.2 V
(mi) VHS4 0.2 V
Input Leakage Current OI) I1H1 3 10 uA
at VIH=VDD (33,34,*5) 11H345 -10 10 uA
Input Leakage Current (*1) llLl -10 -3 uA
at V1L=VSS (*2,**) IILZ -70 -15 uA
(*3,x4,*5) IIL645 -10 10 uA
High Level Input Voltage (BI) VIH1 3.5 VDD V
O2) VIH2 2.2 VDD V
"3,mi) V1H84 2.4 VDD v
(ati) VIH5 2.2 VDD v
Low Level Input Voltage (*1) VILI 0 1.5 V
(*2) VIL2 o 0.8 V
(*3,*4) VIL84 o 0.58 V
(ati) VIL5 o 0.8 ll
High Level Input Current (Mr) lOHl -0.5 tttA
at 1l0iNilDD-0.41l (er) IOH2 -4.0 mA
(st1) [OHS -2.0 mA
Low Level Input Current Ot?) IOL1 0.5 mA
at VOL=0.4V (er) IOL2 6.0 mA
(*8) IOLa 2.0 mA
Power Supply Current 1001 20 30 tttA
Stand-by Current IDD2 50 uA
Comment t " XIN
-T'EST,LOCK,-CL
magnesia
At VDD " 5.0V
TC8566AF-68
-IDX,-RDY,-tfP,-2S,-FLT,-'rK0
Other Inputs and Data Bus
(Input with Pull-up)
(Schimitt Trigger Input)
(Schinltt Trigger Input)
1tDT1,hE,H8,HL,MEN3-0,DS3-0,STP,FR,M,DR
Other Outputs and Data Bus
This Material Copyrighted By Its Respective Manufacturer
"iaui:-s)' WES m:icr/y_dih,rrdii sriFizf/iEi-
FLOPPY DISK CONTROLLER llll
TOSHIBA tuc/ups"
8.4. M CHARACTERISTICS
VDDI5.0:I:10X , VSSIOV Tar-MT to +85°C
ITEM SYMBOL MIN. TYP. MAX. UNIT
AEN Setup tine before -IOR tAENR 0 ns
AEN Hold tine after -IOR tRAEN 0 ns
-CS Setup time before -IOR tSR 0 ns
-CS Hold tine after -IOR tRS 0 ns
Address Setup tine before -IOR tAR 10 ns
Address Hold tine after -IOR ngA 0 ns
Data Delay tine fron -IOR tRD 100 ns
Data Hold time after -IOR tDR 20 100 ns
Pulse Width of -IOR tRR 200 ns
AEN Hold tine before -IOW tAENW 0 ns
AEN Hold tine after -IOH tUAEN 0 ns
-CS Setup tine before -rtm tSW 0 ns
-cs Hold tine after -IOW tHS o ns
Address Setup tine before -IOW tAV 10 us
Address Hold tine after -10tt tWA 10 ns
Data Setup tine before -low tDW 100 ns
Data Hold time after -10w tWD 10 ns
Pulse Width of -10W tww 200 ns
INT Delay tine fron -um (*1) tRl 500 ns
INT Delay tine from -um (*1) tWI 500 ns
INTRO Delay tine fron -10R (*1) tRIR 500 ns
INTRO Delay time fron -10H (*1) tWIR 500 ns
DMA Cycle time (*1) tDRQCY 13 us
DRQ Delay time from .-DACK tACDRQ 200 ns
-10R Delay tine fron DRQ (*1) tDRQR 800 ns
-IOW Delay tine from DRQ (*1) tDRQW 250 ns
~IOR/-10w Delay tine from DRQ tDRQRW 12 us
DNA Cycle time (*1) tDRQZCY 13 us
DRQ2 Delay time from -DACK2 tACDRQZ 200 ns
-10R Delay tine fron DRQ2 tDRO2R 0 ns
-IOW Delay tine from DRQ2 tDRt12R 0 ns
-ioR/-Itm Delay time fron DRG? tDRQ2RN 11 us
Pulse Width of -DACK2 (*1) tAA 250 ns
-DACK2 Setup tine before -IOR tACR o ns
-DACK2 Hold time after -10R tRAC o ns
-DACK2 Setup time before -Itm tACN o ns
-DACK2 Hold tine after -Itm MMC 0 ns
Pulse Width of DMATC (t1) CN 125 ns
DS Setup time before STP (*1) tDSST 21 us
DS Hold time after STP (*1) tSTDS 5 us
DR Setup tine before STP (*1) tDST 1 us
DR Hold time after STP (*1) ttrm 24 us
Pulse Width of STP OI) tSTP 7 us
continue
Tc8566AF-459
This Material Copyrighted By Its Respective Manufacturer
TOSHIBA (UC/UP) _ buE >177: Havana 0025753 253 I:I'r<>83
llll FLOPPY DISK CONTROLLER
se tr t o WDT t
u se W o 1 *1 t 1
Low ve Pulse W t o - tRDDl 130
H Level Pu se W1 o RDT t 130
Pu se W t of FR * tFR 8
se W1 0 -IDX *1 tlDX 250
Comment
The values for 8" mode are in the above list.
The values which are marked (*1) should be doubled for mini-floppy
T08566AF-60
This Material Copyrighted By Its Respective Manufacturer
.¥03HIBA (Ud/UP)
6.4.1. AC TEST INPUT WAVE
Input Terninal Group 1 t
Lhi:Ay" ti 86858;; 8658;88 LTT EJTOSB
FLOPPY DISK CONTROLLER lill
XIN Input
Input Terninal Group 2 ..
3. 51_Vlll)
1. 5V (VIL)
Input with Pull-up Device
Input Terninal Group 3, 4 t
2. 2V (VIH)
o. BV (VIL)
Schmitt trigger
Input Terminal Group 5 t
The other Input and Data Bus
2. AV (VIH) cr
0. 6V (VIL)
cr 2. 2V_(VIH) cc
o, 4V 0. 8V (VIL)
6.4.2. OUTPUT LOAD CIRCUIT
TERMINAL E
50PF 5. 6KQ
T08566AF-61
This Material Copyrighted By Its Respective Manufacturer
TOSHIBA (UC/UP) - “but: D_ tzh' tir/tF/is:, ndéénis’iuaé Iii'rosa
MFI-or''" DISK CONTROLLER
6.4.3. TIMING CHART
(1) Read Operation
AEN " 1]
k-ua-ss e‘mn
SR9 _ RS
A7--AO 2 X
K- Ill tee . Ilk-et
C-""""-
'o D7-DO -ii...r.--.F--..q.-....-..e.-0..r._.eM.F--.F..q.-q.-_--q.
(2) write Operation
AEN \ ll
tsua " e‘musuél
tse A7~AO X X
W D7-DO " K
toe tuna
-IOW xi /
T08566AF-62
This Material Copyrighted By Its Respective Manufacturer
- - - -7 .4141 -
Ll/ri) Er-KG/Ty/n" 8885755 +55 :JTosa
FLOPPY DISK CONTROLLER Ill]
fosH:rid.arr/pj"
(3) Non - DNA Operation
(4) DMA Operation
-DACK2
(5) Terminal Count wave Forn
WWII “INNWWI
"rCXMi66AF-63
This Material Copyrighted By Its Respective Manufacturer
TOSHI-BI-A (UC/UP) sd: 1) I: 808%248 0035785 “ID“! IjTos3
llllFLor'Py DISK CONTROLLER
(6) Seek Operation (CDS = Low)
DSA,DSB t t
I)SST---i> tosr-> <-tsmye,
t --->
---------e,
(La-High)
(7) Write Data Wave Form
WDTI l il001
(La=High)
(8) Read Data Wave Form
--RDT l RDDl '.' ./
(9) Fault Reset wave Form
(La=High)
TC8566AF-64
This Material Copyrighted By Its Respective Manufacturer
TOSHIBA t-uchjso)"
(10) Index Have Forn
bHE D mt: cii:Frhu/crm:a/iriais El/ii;
FLOPPY DISK CONTROLLER ll?
TC8566AF-65
IIHIWIUI HHIHIWIWI
This Material Copyrighted By Its Respective Manufacturer
This Material Copyrighted By Its Respective Manufacturer
TC8566AF-66
F18.5.2.7. Operation Timings of The READ DATA (IMAM)
-——9é——C-Phase—€*%—-———E-Phase—————€K
TOSHIBA (UC/UP)
"""""'''""t
fill FLOPPY DISK CONTROLLER
UlllllJlJlllHHl
.rsrrsr-vr-.sers-rmesrrsr.sre-''-'o'"i'"'mr'''"e"'-mr'"""'""r
STATUS D10
.m..rs.-r--rser_.resr_e.rr"r9'sr'"ir ~~~~ -r.rrmrr%rr-r'-e.re.r'''r.r'''%r'''%r
---:r--7----
k CB———J
E3 9097399 tlt3ii%'?ia'3 P8h EJTOSB
Tosii:riirtr/d/Goj" - "Lilla? 5790-57249 06.3.5770 LITE EGGS?
FLOPPY DISK CONTROLLER lili
7 . PACKAGE DIMENSION
IODPIN FLAT PLASTIC PACKAGE unit: an
zaeias
note l. zootoz
2gE..gpaggggl'l,,
flSZblYP
L I y _ . . V _
Ct l / [lalllllllNlallllllll0mllfllmlllm L
s.-..-""
note 1: Outline dimension of the cold excludes
of the remainder of the mold fragment
and the tdis-bar-cut. However, the
remainder of the mold fragment and
the tie-bar-cut are 0.15m Max in ---_:
each side. . T--
- 81 - :=150
o 1:21: :1:
8 ===== "er-"",
L---,..."
=2: 3::
==l: 3:: C1 eo
12:1: ‘21:: ff ll
=2: 22:: H H
:12: 32:) -
m L___LJ. 2:32:23 S'
3 === ===> f?
a 2:1: ====
R === 3:12:
n) ==== CD in:
d 100:: :2:
"-HE55CeRaE -
1 - so
..- Ir"
l? _....-,.?
a1 sial
2.85+0.8
note 2: Aplly to the flat part of the
I LT 5:}:02 l
Detail flgure of' A
Tt28566AF-67
This Material Copyrighted By Its Respective Manufacturer
www.ic-phoenix.com
.
