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TC58V32AFT
32 Mbit CMOS NAND E2PROM
TOSHIBA TC58V32AFT/ADC
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
32 Mbit (4M M 8bit) CMOS NAND EZPROM
DESCRIPTION
The TC58V32AFT/ADC device is a single volt 32M(34,603,008) bit NAND Electrically Erasable and
Programmable Read Only Memory (NAND EEPROM) organized as 528 bytes X 16 pages X 512 blocks.
The device has a 528 byte static register which allows the rogram and read data to be transferred
between the register and the memory cell array in 528 gyte increments. The erase operation is
im lemented in a sin le block unit (8K bytes + 256 b tes : 528 bytes M 16 a%as).
he TC58V32AFT/ DC is a serial type of memory evice which utilizes t e 0 pins for both address
and datainput/ output as well as command inputs. The erase and program operations are automatically
executed making the device most suitable for applications such as Solid State File Storage, Voice
Recording, Image File Memory for still cameras and other systems which require large density, non-
volatile memory data storage.
FEATURES
0 Organization 0 Power supply
TC58V32AFT : Vcc = 3.0 V to 5.5 V
$33313 cell array 233 § ilk X 8 TC58V32ADC : Vcc = 3.3 V , 0.3 V
Page size 528 bytes 0 Access time .
Block size (8K + 256) bytes Celi array- Register 10 ps max
0 Mode Serlal Read Cycle 50 ns mm
Read 0 Operating current
Reset, Auto page program Read (50nS cycle) 10 mA typ
Auto block erase, Status read Program(ave.) 10 mA typ
0 Mode control Erase(ave.) 10 mA typ
Serial input/output Standby 100 ,uA
Command control It Package
TC58V32AFT :TSOP 11 44/40 - P - 400 - 0.80B
(Weight : 0.48 g Typ.)
PIN ASSIGNMENT (TOP VIEW) TC58V32ADC :FDC - 22A
(Weight: 1.8 g Typ.)
TC58V32AFT
P....-....-...............-. TC58V32ADC
i VssE1 aaClucci, PINASSl_GNMENT
i CLE l: 2 43 CltT g 1 2 3 4 s 6 7 8 9 10 11
ALE I: 3 42 C] It7i Vss CLE ALE E W l/OI l/O2 1/03 1/04 Vss Vss I/O1 tog " port
MNCE 6 _........... 39"ij6 mmm.. ', 'v. 'r. 'r. i, i.' i' j' ::' : / WE Write enable
NC E 7 38 gNC ', . '. '. '. :." .:' f f f / E Read enable
15 I: g :2 Cl 15 'v. l, '. '-.. ':. i.' ..:" i' / / / CLE Command latch enable
NC I: 10 35 Cl NC 'v.. ':, i. i..' ..:' j' / / / ALE Address latch enable
i2 3: '., I. 3. c. '-. E E , .-' / / W Write protect
NC I: 13 32 Cl NC R/E Ready/Busy
NC I: 14 31 Cl NC OP Option Pin
NC I: 15 30 Cl NC
NC I: 16 29 Cl NC LVD Low Voltage Detect
"ite-f. .17. .......... 2.8%.!)[9 ..... Vcc Power supply
" 1 18 27 IIO 8
. . . . . V
a I/O2 II 19 26 31/07 2 . . . ' . . . . . . . SS Ground
g I/O3 l: 20 25 31/06 g 22 21 20 19 18 17 16 15 14 13 12
i I/O4 i: 21 24 C] |/05 i' Vcc E Te R/E OP LVD I/O8 I/O? I/06 IIOS Vcc op : GND Input : 528 Byte/Page Operation
..... yssf. p.?...........?.?.;..].).)..:...:.' Vcc Input : 512Byte/Page Operation
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operatin ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and con itions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1998-06-1 8 1/34
TOSHIBA
BLOCK DIAG RAM
TC58V32AFT/ADC
Vcc GND
(j-lstatus-register l l
I/O1o_ I/O ( l Address register II a = Column buffer
to i i' Control I" ji), 5 Column decoder
I/O tyor-r cnrcwt _ Command register I t? Data register
" I . Sense amp A-
CE o-r , B i
W f R d 5
CLE o-F a f o e E
ALE o-r Logic = antrgl g f ll' f, i.' Memory
W C. control circuit r g g g i.' cell array
E Cr-r f, F .
7P CY-F g
ABSOLUTE MAXIMUM RATINGS
SYMBOL RATING UNIT
TC58V32AFT TC58V32ADC
Vcc Power supply Voltage -0.6 to 6.0 - 0.6to 4.6 V
VIN Input Voltage - 0.6 to 6.0 - 0.6 to 4.6 V
VI/o Input /Output Voltage - 0.6V to Vcc + 0.3V(S 6.0V) - 0.6V to Vcc + 0.3V(S 4.6V) V
PD Power Dissipation 0.5 0.5 W
TSOLDER Soldering Temperature (10s) 260 - "C
TSTG Storage Temperature - 55 to 150 - 20 to 65 ''C
TOPR Operating Temperature Oto 7O Oto 55 "C
CAPACITANCE *(Ta = 25°C, f = 1 MHz)
SYMBOL PARAMETER CONDITION MIN MAX UNIT
Cm Input " = 0V - 10 "
Cour Output VOUT = 0V - 10 "
* This parameter is periodically sampled and is not tested for every component.
1998-06-18 2/34
TOSHIBA TC58V32AFT/ADC
VALID BLOCKS (ll
TC58V32AFT/ADC
SYMBOL PARAMETER UNIT
MIN TYP MAX
NVB Valid Block Number 502 508 512 Blocks
(1) The TC58V32AFT/ADC occasionally contains unusable blocks. Refer to Application Note
(13) toward the end of this document.
DC RECOMMENDED OPERATING CONDITIONS
TC58V32AFT TC58V32ADC
SYMBOL PARAMETER UNIT
MIN MAX MIN MAX
Vcc Power Supply Voltage 3.0 5.5 3.0 3.6 V
" High Level Input Voltage 2.0*1/3.0'2 Vcc + 0.3 2.0 Vcc + 0.3 V
" Low Level Input Voltage - 0.3 *3 0.8 - 0.3 *3 0.8 V
*1 :Vcc = 3.3V 1 0.3V
*2 : Vcc>3.6V
*3 : - 2V (pulse width s 20 ns)
DC CHARACTERISTICS
(TC58V32AFT: Ta = 0° to 70°C, Vcc = 3.0Vto 5.5V
(TC58V32ADC : Ta = 0° to 55 "C, Vcc = 3.3 v i 0.3 V)
Vcc = 3.3V i 0.3V Vcc > 3.6V
SYMBOL PARAMETER CONDITION UNIT
MIN TYP MAX MIN TYP MAX
ll, Input Leak Current VlN = 0V~Vcc - - i 10 - - 1-10 PA
Lo Output Leak Current VouT=th4V--Vcc - - i 10 - - i 10 PA
Iccm Operating Current (Serial Read) :CTe::o|::t=0mA, _ 10 20 - 15 30 mA
lccos Operating Current (Command Input) tcyde= 50 ns - 10 20 - 15 30 mA
lcco4 Operating Current (Data Input) tcycle= 50 ns - 10 20 - 15 30 mA
Iccos Operating Current (Address Input) tcyde= 50 ns - 10 20 - 15 30 mA
'cco7 Programming Current - - 10 20 - 15 30 mA
lccog Erasing Current - - 10 20 - 15 30 mA
Iccs1 Standby Current E: VIH - - 1 - - 1 mA
lccsz Standby Current E = Vcc - 0.2 V - - 100 - - 100 PA
VOH High Level Output Voltage [OH = -400 pzA 2.4 - - 2.4 - - V
VOL Low Level Output Voltage loc--- 2.1 mA - - 0.4 - - 0.4 V
Ioc(R/iT) Output Current of (MT) Pin VOL-- 0.4V - 8 - - 8 - mA
1998-06-1 8 3/34
TOSHIBA TC58V32AFT/ADC
AC CHARACTERISTICS AND OPERATING CONDITIONS
(TC58V32AFT: Ta = 0° to 70°C, Vcc = 3.0Vto 5.5V)
(TC58V32ADC : Ta=0° to 55°C, Vcc=3.3V l 0.3V)
SYMBOL PARAMETER MIN MAX UNIT NOTE
tCLs CLE Set-Up Time 0 - ns
tcLH CLE Hold Time 10 - ns
tcs E Set-Up Time 0 - ns
to: E Hold Time 10 - ns
twp Write Pulse Width 25 - ns
tALs ALE Set-Up Time 0 - ns
tALH ALE Hold Time 10 - ns
tDs Data Set-Up Time 20 - ns
tDH Data Hold Time 10 - ns
twc Write Cycle Time 50 - ns
tWH W High Hold Time 15 - ns
tww W High to W Low 100 - ns
tRR Ready to M Falling Edge 20 - ns
tRp Read Pulse Width 35 - ns
tRc Read Cycle Time 50 - ns
tREA E Access Time (Serial Data Access) - 35 ns
mm 3 High Time for the Last Address in Serial Read Cycle 100 - ns (3)
tREAID E Access Time (ID Read) - 35 ns
tOH Data Output Hold Time 10 - ns
tRHZ E High to Output High Impedance - 30 ns
tCHz E High to Output High Impedance -. 20 ns
tREH E High Hold Time 15 - ns
th Output High Impedance to E Rising Edge 0 - ns
tRSTo 'rE Access Time (Status Read) - 35 ns
tcho E Access Time (Status Read) - 45 ns
tRHW E High to m Low 0 - ns
tWHC W High to E Low 30 - ns
tWHR W High to E Low 30 - ns
tAm ALE Low to E Low (ID Read) 100 - ns
tcR E Low to E Low (ID Read) 100 - ns
tR Memory Cell Array to Starting Address - 10 M;
tws m High to Busy - 200 ns
tAR2 ALE Low to E Low (Read Cycle) 50 - ns
tRB E Last Clock Rising Edge to Busy (in Sequential Read) - 200 ns
tcRY E High to Ready (in Case of Interception by E in Read Mode) - 50.rtr(R/iT) ns (2)
tRST Device Resetting Time (Read/Program/Erase) - 6/10/500 pd;
AC TEST CONDITIONS
Input level .' 2.4V/0.4V(Vcc=3.3Vk0.3V)
3.4V/0.4V(Vcc > 3.6V)
Input comparison level : 1.5 V/ 1.5 V
Output data comparison level .' 1.5 V/ 1.5 V
Output load : 1TTL & CL (100 pF)
1998-06-1 8 4/34
TOSHIBA
(1) Transition time (tT) = 5 ns
TC58V32AFT/ADC
(2) CE High to Ready time depends on the pull-up resistor tied to the It/B pin. (Refer to
Application Note (10) toward the end of this document.)
(3) If the delay between "ttrl'?" and tTtf is less than 200 ns and tCEH is greater than or equal to 100 ns,
reading will stop.
If the W-to-CE delay is less than 30 ns, the device will not turn to the Busy state.
tCEH 2 100 ns
* * " or VIL
a / Eiih
© G) : 0 to 30 ns -Y Busy signal is not output.
525 526 527
509 510 511
R/iT I /
PROGRAMMING AND ERASING CHARACTERISTICS
(TC58V32AFT: Ta = 0° to 70°C, Vcc = 3.0Vto 5.5V)
(TC58V32ADC : Ta=0° to 55°C, vcc=3.3v , 0.3V)
SYMBOL PARAMETER MIN TYP MAX UNIT NOTE
tpROG Average Programming Time 300 1000 ps
N Number of Programming Cycles on Same Page 10 (1)
tBERASE Block Erasing Time 2 30 ms
P/E Number of Program/Erase Cycles 1x 106 (2)
(1) Refer to Application Note (11) toward the end of this document.
(2) Refer to Application Note (14) toward the end of this document.
1998-06-1 8 5/34
TOSHIBA TC58V32AFT/ADC
TIMING DIAGRAMS
Latch Timing Diagram for Command/Address /Data
( CLE)
% Set-Up Time Hold Time
tos tDH
l/O1t08
" or VIL
Command Input Cycle Timing Diagram
A tCLs tCLH l
tcs Hm I
"'% twe r
tALS _ tALH
tos tDH
l/01t08 si ie
" or VIL
1998-06-1 8 6/34
TOSHIBA TC58V32AFT/ADC
Address Input Cycle Timing Diagram
CLE sh tCLs
twc twc
tcs - - _
tWH 4 tWH
twe twp twe
m ) l S l y t
' K_] i-)
tALS tALH
tos tDH tos tDH I tos tDH
l/O1to8 Aom7 A9to16 A17t021
Data Input Cycle Timing Diagram
" or "
ALE si\"
twp th tws,
tos tos
tDH E , tDH tDH
V01 to 8 DIN0 DIN1 *DIN 511 iie
*OP = GND input: DIN 527
= Vcc input 2 DIN 511
" or VIL
1998-06-1 8 7/34
TOSHIBA TC58V32AFT/ADC
Serial Read Cycle Timing Diagram
IIO1~8
Status Read Cycle Timing Diagram
tCLs f
l f'" %x 2
ltwp: cl, 4 tcsm _
W " / tWHC tCHZ
tWHR tOH
RE ta l /
DS tDH tRHz
tRSTO Status
l/O, t08 70H* output
R/iT /
* 70H-70 in HEX data
I " or "
1998-06-1 8 8/34
Read Cycle (1) Timing Diagram
CLE tCLH
t t tCEH
a -tih gh Jih V%
- l l l t l I /
U t U) R tCRY
‘ALS tALH tAR2 _ r
ALE / tiiik-
, r tWB tRR tRC
tALH _
ms tDH tDs tDH tos tDH tuy, tDH tREA
l/Ol 00H A0 to A9 to A17 to DOUT DOUT DOUT
t08 A7 A16 A21] N N+1 N+2
Column address
N 1R3)
RIB l, / ** OP = GND input: DOUT 527 l
= Vcc input 2 Dour511
I " or "
Read Cycle (1) Timing Diagram: Interrupted by CE
CLE tCLH
t? tCH
E l ith JA EI f'"
- l l l t l t
WE U i 7 tR tcHz
tms, tALH tAR2 0
l X tou
ALE 2 dii)-
tWB tRR tRc
tALH _
tos tDH ItDS tD ItDS tDH LES) tDH tREA t0
V01 00H A0 to A9 to A17 td DOUT Dom DOUT
to8 A7 A16 A21) N N+1 N+2
Column address
R/iT l l . .
g 7 *** Read Operation usung 00H Command N: 0 to 255
Read Operation using 01H Command N: 256 to 511
I " or "
1998-06-1 8 9/34
TOSHIBA TC58V32AFT/ADC
Read Cycle (2) Timing Diagram
CLE tc S tcm
tcs tCH
m x / I/N/ m
tALs 4 tws, 4 tAt?
tALH f
ALE 7 f" /%‘x
tALH tRC
- l / l / H N /
RE tos tog K K
tDH tDH
tRR _ tREA **
POI A0 to A9 to A17 to \
to 8 01H A7 A16 A21 / OUT
Column address 256+M 256+M+1
RIB " / **OP = GND input: DOUT 527
= Vcc input I DOUT511
I " or "
Read Cycle (3) Timing Diagram
CLE tc s km
tcs tCH .
E l /tiA JI A
tALS tws 1:AR?
ALE tALH f l
7 if" %:
tALH tRC
- l / l / E \ /
RE tos tos K K
tDH tDH
tRR tREA **
I/OI A0 to A9 to A17 to \
to 8 50H A7 A16 A21 / (E)-(E)
Column address 512+M 512+M+1 527
RIB \ / **OP = GND input: DOUT 527
Do not input Vcc
: " or "
TOSHIBA
TC58V32AFT/ADC
Sequential Read (1) Timing Diagram
CLE I N
i.' \ 22 22 22
I/OI : : ,
to 8 /)FT%y AMAPXAéE" X5521” n 'tel 'te2l 0 D a a
Column Page
address address
Page M + 1
access
**OP= GND input: DOUT 527
= Vcc input 1 DOUT 511
: " or "
Sequential Read (2) Timing Diagram
i." \ " n J? n
I/OI A 01H W /,,aati,toxaitso ri: 7to a a a a
to 8 A7 A16 (k21
Column Page
address address
Page M + 1
access
**OP= GND input: DOUT 527
= Vcc input I DOUT511
: " or VIL
1998-06-18 11/34
TOSHIBA TC58V32AFT/ADC
Sequential Read (3) Timing Diagram
n 22 n
n 22 !!
l/OI Aozto AS; to i 7 to
to 8 A 50H W m A16 A21
Column Page 512 512 512 t 512 513 514
address address + + + R
N N+1 N+2
R/E l f l
Page M Page M + 1
access access
**OP= GND input: DOUT 527
= Do not input Vcc
I " or "
1998-06-18 12/34
TOSHIBA TC58V32AFT/ADC
Auto Program Operation Timing Diagram
CLE tCLs t(LHK n / W'" % '
c-E-it-c' di); h' a Fges, EI
WE L] tALS L] tALS
tALH ' ALH _
ALE f l
'rE tDH l tDH l
tos tos
l/OI 80H A0 to A9 to XA17 Ito)-
to 8 A7 A16 A21
*OP= GND input: DIN 527
= Vcc input 1 DIN 511
: " or " : If data is being output, do not allow any input.
Auto Block Erase Timing Diagram
4 / If" Ah/ (_,,diiiiiii7
LCLS F'" % Jh F'"
A9 to A17 to
to 8 60H A16 A21 XF'" Aii)( DOH
Auto Block Erase Erase Start
8 Status
J, 70H
Status Read
Set-Up command command
command
: " or " : If data is being output, do not allow any input.
1998-06-18 13/34
TOSHIBA
ID Read Operation Timing Diagram
TC58V32AFT/ADC
U tALS t _ CR '."
tALH _ d? t
E , AR1
POI 90H d oo ' 98H E5H
to 8 N /
. tREAID tREAID
Address input Maker code Device code
: " or "
1998-06-18 14/34
TOSHIBA
TC58V32AFT/ADC
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information. The
device pin-outs are configured as shown in Figure I.
Command Latch Enable: CLE
The CLE input signal is used to control the acquisition of the operation
mode command into the internal command register. The
command is latched_into the command register from the I/O port on the
rising edge of the WE signal while CLE is high.
Address Latch Enable: ALE
The ALE signal is used to control the acquisition of either address
information or input data into the internal address/dat_aresistor.
Address information is latched on the rising edge of WE if ALE is high.
Input data is latched if ALE is low.
Chip Enable: tTrif
The device goiinto a low poweritandby mode during a Read
operation when CE goes high.LThe CE signal is ignored when the
device is in the Busy state (R/B = L), such as during a Proggam or Erase
operation, arn.LI will not go into Standby mode even if a CE goes high
input. The CE pin must stay low during the Read mode Busy state to
ensure that memory signal array data is correctly transferred to the data
register.
Write Enable: W
The W signal is used to control the acquisition of data from the I/O
Read Enable: RE
The RE si al cgntrols serial data output. Data is available tREA after
the falling e ge of RE.
The internal column address counter is also incremented (Address + 1) on
this falling edge.
I/O Port: I/O 1 to 8
The I/O 1 to 8 pins are used as the port for transferring address,
command and input/output data
to or from the device.
Write Protect: Ttfri
The WP signal is used to protect the device from accidental
programming or erasing. The internal
voltage regulator is reset when WP is low. This signal is usually used for
protecting the data during
the power on/off sequence when input signals are invalid.
Ready/Busx: RI?
The MT output signal is used to indicate the... operating condition of the
device. The R/B signal is in the Busy state (R/B = L) during the Program,
TC58V32AFT
Vss IE 1 44 Clvcc
CLE I: 2 43 cle
ALE l: 3 42 3%
W I: 4 41 Cl R/iT
'.....y7.e...1.C. .5 ............ 4.0.3.09. .....
NC E 6 39 Cl NC
NC I: 7 38 Cl NC
NC I: 8 37 Cl NC
NC I: 9 36 Cl NC
NC E 10 35 Cl NC
NC I: 13 32 Cl NC
NC I: 14 31 Cl NC
NC I: 15 30 Cl NC
NC I: 16 29 Cl NC
.....N.<;..!.I.1.7. .......... 2.8.3.111: .....
1/01 I: 18 27 31/08
1/02 E 19 26 31/07
1/03 I: 20 25 31/06
1/04 I: 21 24 31/05
. .... yss...rC. .2..2. .......... .2..3..;|..\./.C.C.....
TC58V32ADC
1 2 3 4 5 6 7 8 9 10 11
Vss CLE ALE W W 1/01 1/021/03 1/04 Vss Vss
Erttge or Read operations and will return to Ready state . 22: 21 i, 1;, (s, 17 16 (s 14 '12
s?fgh=iRnafot'neryitfion of the operation. The output buffer for this Vcc E E R/E OP LVD l/O8 1/07 l/O6 l/O5 Vcc
Option Pin: OP
The OP signal is used to change the page size. The device is in 528 Figure l. Pinout
byte/page mode when OP = GND, and 512 byte/page mode when OP =
Low Voltage Detect: LVD
The LVD is used to detect the proper supply voltage. By connecting
this pin to VSS through a pull-down resistor, it is possible to distinguish
3.3V product(TC58V32DC) from 5V product(TC5832DC). When 3.3V is
applied as Vcc to pins 12 and 22, a "H" level can be detected on the
system side if the device is a 3.3V product, and "L" level for a 5V
product.
1998-06-18 15/34
TOSHIBA TC58V32AFT/ADC
Schematic Cell Layout and Address Assignment
The Program operation is implemented in a page units while the Erase operation is carried out in
block units.
A page consists of 528 bytes in which 512 bytes are for
main memory and 16 bytes are for redundancy or other
) 16 pages -9 1 block
1 Page = 528 bytes
1 Block = 528 bytes X 16 pages = (8K + 256) bytes
Total Device Density = 528 bytes X 16 pages X 512 blocks
8192 l
512 blocks L -
The address is acquired through the I/O port over
8I/O three consecutive clock cycles, as shown in Table 1.
_______._____ .______.._
Figure 2. Schematic Cell Layout
Table 1. Add ressi ng
I/OI IIO 2 IIO 3 IIO 4 " 5 " 6 " 7 IIO 8
A0 to A7 : column address
First cycle A0 A1 A2 A3 A4 A5 A6 A7 A9 to A21 : page address
A13 to A21: block address
Second cycle A9 A10 A11 A12 A13 A14 A15 A16 (ti to A12 .' NAND address in block)
Third cycle A17 A18 A19 A20 A21 * L * L * L
*: A8 is automatically set to "Low" or "High" by the "00H" command or a "01H" command in device inside.
*: I/O6 to 8 must be set low in the third cycle.
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by the eleven different
command operations shown in T321; _?.......... Addr..:..?...?.?.. input, command input and data input/output are
controlled by the CLE, ALE, CE, WE, RE and WP signals, as shown in Table 2.
Table 2. Logic Table
CLE ALE E W M W
Command Input H L L U H *
Data Input L L L U H *
Address Input L H L _|_/l\_ H *
Serial Data Output L L L H U *
During Programming (Busy) * * * * * H
During Erasing (Busy) * * * * * H
Program, Erase Inhibit * * * * * L
H: vm, L: VILI *: " or VIL
1998-06-18 16/34
TOSHIBA TC58V32AFT/ADC
Table 3. Command table (HEX data)
FIRST CYCLE SECOND CYCLE ACCEPTABLE COMMAND
WHILE BUSY
Serial Data Input 80 -
Read Mode (1) 00 -
Read Mode (2) 01 -
Read Mode (3) 50 -
Reset FF - C)
Auto Program 10 -
Auto Block Erase 60 D0
Status Read 70 - 0
ID Read 90 -
Bit assignment of HEX data
(Example)
Serial data input: 80H
w----'-----------'---,
(1l0l0l0l0l0l0l0l
|/O87 6 5 4 3 2I/o1
Once the device is set to Read mode by the ''00H", "01H" or "50H" command,
additional Read commands are not needed for sequential page Read operations.
Table 4 shows the operation states for Read mode.
Table 4. Read mode operation states
CLE ALE E W E IIO 1 TO l/O8 POWER
Output Select L L L H L Data output Active
Output Deselect L L L H H High impedance Active
Standby L L H H * High impedance Standby
H:V|H L:N/IL *: " or "
1998-06-18 17/34
TOSHIBA TC58V32AFT/ADC
DEVICE OPERATION
Read Mode LI)
Read mode (1) is set by issuing a '00H' command to the command register. Refer to Figure 3
below for timing details and block diagram.
CLE Cl
E_\%%%
mL/UUM
ALE_/—\
Start address input A data transfer operation from thicell array to the
register starts on the rising edge of WE in the third cycle
W 511 or 527 (after the address information has been latched.) The device
' i will be in the Busy state during this transfer period. The E
signal must stay low after the third address input and during
the Busy state.
A “.1 Cell array After the transfer period the device returns to Ready_
' state. Serial data can be output synchronously with the RE
clock from the starting pointer designated in the address
Figure 3. Read mode (1) operation input cycle.
Select page -F s.
Read Mode tLO
CLE I l
E_\ m m Ea
ALE_/—\
Start address input
-25/'zl-511o/5-27, The operation of the device after input of the "01H" command is
. the same as Read Mode(1). To set the starting pointer is to be set
Select page i.' after column address 256, use Read Mode (2).
N -t, 5 “.1 Cell array For a Sequential Read, output of the next page starts from
. Ad column address 0.
Figure 4. Read mode (2)0peration
1998-06-18 18/34
TOSHIBA TC58V32AFT/ADC
Read Mode 131
Read mode (3) has the same timing as Read modes (1) and (2) but is used to access information in
the extra 16-byte redundancy area of the page. The starting pointer is therefore assigned between
bytes 512 and 527.
CLE Cl
EjW/A%%
512 527
I A r i = Addresses bits A0 to A3 are used to set the starting pointer
l for the redundant memory cells, while A4 to A7 are ignored.
Once the "50H" command is set, the pointer moves to the
A A redundant cell locations and only those 16 cells can be
"V "it.f addressed, regardless of the A4 to A7 addresses.
(The ''00H" command is necessary to move the pointer back to
Figure 5. Read mode(3)operation the 0 to 511 main memory cell locations.)
Read mode (3) operation is invalid when OP is at the Vcc level.
1998-06-18 19/34
TOSHIBA TC58V32AFT/ADC
Se uential Read(1)(2)(3)
This mode allows the sequential reading of pages without additional address input.
iiiiji9 "s--------" tit "s---------" ta "s--------" ta
Address input A-F Data output A-F Data output A-F
Busy Busy Busy
0 527 (01H) (50H) 512 527
Sequential Read (1) Sequential Read (2) Sequential Read (3)
Sequential Read modes (1) and (2) output addresses 0 to 527 as shown above while Sequential
Read mode (3) outputs the redundant address locations only. When the pointer reaches the last
address, the device continues to output the data from this address ** on each RT? clock signal.
** OP-- GND : column address 527.
Vcc : column address 511.
1998-06-18 20/34
TOSHIBA TC58V32AFT/ADC
Status Read
The device automatically implements the execution and verification of the Program and Erase
operations. The Status Read function is used to monitor the Ready/Busy status of the device, determine
the pass /fai1 result of a Program or Erase operation, and determine if the device is in Suspend or
Protect mode. The device status is output through the I/O port using the "rt""t"f" clock after a "70H"
command input. The resulting information is outlined in Table 5.
Table 5. Status output table
STATUS OUTPUT
I/OI Pass/Fail Pass : 'o' Fail : 'l' . . .
I/O2 Notused 'ty whT:,'l',aess2viirie,t;uil,otLR1,aidsyosrt1ytevfid
l/O3 Not used '0'
I/O4 Not used '0'
HO 5 Not used '0'
I/O6 Not used '0'
I/O? Ready/Busy Ready : 'I' Busy : '0'
l/O8 Write protect Protect :'0' Not Protect : 'I'
An application example with multiple devices is shown in Figure 6.
E1 E; E3 CEN CE +1
Device Device Device Device Device
1 2 3 N N+1
" l 70H ) g ' ( 70H} J '
“Status on Istatus on
Device 1 Device N
Figure 6. Status read timing application example
SYSTEM DESIGN NOTE : If the R/IT pin signals of multiple devices are common-wired as shown in the
diagram, the Status Read Function can be used to determine the status of each individually selected
1998-06-18 21/34
TOSHIBA TC58V32AFT/ADC
Auto Page Program
The device implements the Automatic Page Program operation after receiving a "10H" Program
command after the address and data have been input. The sequence of command, address and
data input is shown below. (Refer to the detailed timing chart.)
Citi)-,..-.-.-,..-..;'.'''-'';-?.",) Cl,
Data Input Program command Status Read
command Data input command
(tttss o to 527 When OP = GND
p o to 511 When OP = Vcc
R/B t I R/iT automatically returns to Ready after completion.
Data input
Program Read & Verification
I The data is transferred (programmed) from the register to the
Selected selected page on the rising edge of m following the "10H"
page command input. After programming the programmed data is
transferred back to the register to be automatically verified by
the device. If the program does not succeed, the above
ProgramNerify operation is repeated by the device until success is
achieved or until the maximum loop number set in the device is
Figure 7. Auto Page Program operation reached.
Auto Block Erase
The Auto Block Erase operation starts on the rising edge of W after the Erase Execution command
"DOH" which follows the Erase Set-Up command "60H". This two-cycle process for Erase operations
acts as an extra layer of protection from accidental erasure of data due to external noise. The device
automatically executes the Erase and Verify operations.
(Ciiiiy, e---/C'i'i"ip m ttC/iF"'-"
. Fail
Block address . Erase Start Status Read
input: 2cycles command command
R/E I Busy l
1998-06-18 22/34
TOSHIBA TC58V32AFT/ADC
The Reset mode stops all operations. For example, in the case of a Program or Erase
operation the regulated voltage is discharged to 0 volts and the device will go into Wait state.
The address and data registers are set as follows after a Reset:
. Address Register : All "o"
. Data Register : All "I''
. Operation Mode : Wait State
The response after an "FFH" Reset command is input during each operation is as follows:
Ci) If the Reset (FFH) command is input during programming :
Figure 8.
(80> 'lo', 'FF', foo',
. Register set
Internal Vpp -l-t,rssssf'c.)i' .3
R/iT " i.'. tRST (max 10/15) I
© If the Reset (FFH) command is input during erasing : Figure 9.
, D0 , , Ct , 00
Internal Erase _l-i'sss----,..,....., . Register set .
5 :A-F:
voltage 2 . .
_ -! i4 tRST (max 500rs) _
R/B , 7
© If the reset(FFH) command is input durinq a Read operation :
Figure 10.
Cii2 FF CiD-
mg l i..' I
iA-F.'
tRST (max 6/15)
© If the Status Read command (70H) is input after a Reset .'
Figure 11.
tlu,,; 'ue,,..)-----------,
l I/O status : Pass/ Fail -9 Pass
4 - : Ready/ Busy -9 Ready
However, the following operation is prohibited. If the following operation is executed, set up
for address and data register can not be guaranteed. (the Register may not be reset correctly)
CD 070 4 l/Ostatus : Pass/Fail-is
- E : Ready/Busy-s Ready
RIB i g , cfrrrrzzzzz==--
(6 If the Reset command is input in succession : Figure 12.
(1) (2) (3)
, 10 E , FF E , FF k FF
'sl2..9 kd.'.,.,-" 'ut,
R/E ( I
The second command is invalid, but the third CD command is
1998-06-18 23/34
TOSHIBA TC58V32AFT/ADC
ID Read
The TC58V32AFT/ADC contains ID codes to identify the device type and the manufacturer. The ID
codes are read out using the following timing conditions:
CLE l I
tREAID
90H 00 98H E5H
ID read command Address Maker code Device code
Figure 13. ID read timing
Table 6. Code table
" 8 " 7 l/O 6 l/O 5 I/O 4 I/O 3 I/O 2 I/O 1 HEX DATA
Maker code 1 0 0 1 1 0 0 0 98H
Device code 1 1 1 0 0 1 0 1 E5H
For the access time of tREAID, tCR and tAm (refer to the AC Characteristics.)
1998-06-18 24/34
TOSHIBA TC58V32AFT/ADC
APPLICATION NOTES AND COMMENTS
(1) Prohibition of unspecified commands
The operation commands are listed in Table 3. Data input as a command other than the
specified commands in Table 3 is prohibited. Stored data may be corrupted if an unspecified
command is entered during the command cycle.
(2) Pointer control for '00H', '01H', '50H'
The device has three read modes which set the destination of the pointer. Table 7 shows the
destination of the pointer, and figure 20 shows the block diagram of their operations.
. . . O 255 256 511 512 527
Table 7. Pointer Destination
READ MODE COMMAND POINTER iii ..................... lll ........................ iii ..... l
(1) 00H 0 to 255 3 I /
(2) 01H 256 to 511 o\°c
(3) 50H 512 to 527 00H -r
01H -F Pointer control
50H -F
Figure 14. Pointer control
The pointer is set to region 'A' by the '00H' command, to region 'B' by the 'OI' command,
and to region 'C' by the '50H' command.
(Example)
The '00H' command needs to be input to set the pointer back to region 'A' when the pointer
points to region 'C.
H ( H ',
Add Start point Add Start point Add Start point
A area A area C area
5 H l H \
0 , 00 ,
Add Start point Add Start point Add Start point
C area C area A area
"'e""s--'-.'"'-'"'- ‘V‘ .
Add Start point Add Start point
B area A area
For programming into region 'C' only, set the start point to region 'C' with the '50H' command.
p''irr'rr'3N f''1TCS
(50H) ‘80H, 't 10H ,
Add DIN
Programming into region C only
Start point
C area
, 80H _ ' q
Add DIN . . .
l Programming Into region B and C
Start point
B area
Figure 15. Example of Pointer Setting
1998-06-18 25/34
TOSHIBA TC58V32AFT/ADC
(3) Acceptable commands after serial input command '80H'
Once the serial input command ('80H') is input, do not input any command other than the
program execution command ('10H') or the reset eommand('FFH').
(80) CFC,
vi-a-l-CI-CI-CI-l :
's--------"
Address input
R/iT -
Figure 16.
If a command other than '10H' or 'FFH' is input, the program operation is not performed.
0 , XX ' , 10 k . .
8 VCD/ 'sdiL'.9 In case of this operation, the FFH command
Other command Programming will not be executed. is needed.
(4) Status read during the read operation
p'''C'CP'h i [A]
Command CD \22/ i
a -I Cl i.' i.'
m Ll l-n-l \_I \_/ \;_I 'i'
MT l 'i." / i.' ':':
R-E , : : ......
Status read l_l L/N/r
N address command input ms, ['_'-']
Status read Status output
Figure 17.
The device status can be read out by inputting the status read command "NH' during the read mode.
Once the device is set to the status read mode after "NH' command input, the device does not return to
the read mode.
Therefore, a status read during the read operation is prohibited.
However, when the read command '00H' is input during [A], the status mode is reset, and the device
returns to the read mode. In this case, the data output starts from address N without address input.
(5) Auto program failure
fC,tss Fail p"''.','".',"', fT>,
80 10 70 VD 80 10
(CiiD,, s--rsl.S9 lu'.'.'--'"--, s-lui,'.."
Address Data Address Data
M input N input
When the programming result for page address M is Tail', try to program the
page to address N in another block. Because the previous input data is lost, the same
sequence of '80H' command, address and data input is necessary.
Figure 18.
1998-06-18 26/34
TOSHIBA TC58V32AFT/ADC
(6) R/tT .' Termination for the Ready/ Busy pin(R/tT)
A pull-up resistor needs to be used for termination because the It/B buffer consists of an open
drain circuit.
l Vcc R
Device R/B
' 1 CL
Figure 19.
This data may vary by device.
We recommend that you use this data as a
reference when selecting a resistor value. 0
1 kn 2kn 3kn 4kn
(7) Status after Power On
Although the device is set to the read mode after power- up, the following sequence is needed
because each input signal may not be stable at power on.
Power on ( FF ', ( oo ',
Reset Read mode(1)
Figure 20.
(8) Power On/ Off Sequence:
The TtTri signal is useful for protecting against data corruption at power on/off.
The following
timing is necessary .'
i' i..' (g) .
don't ik...:''" i
care . g
E, m, T i i'
CLE, ALE i 5 " i
- VIL i' i.' VIL
WP L Operation _;
Figure 21. Power On/Off Sequence
1998-06-18 27/34
TOSHIBA TC58V32AFT/ADC
(9) Setup for Tirt5 Signal
The erase and program operations are compulsively reset when WP goes low. The following
conditions must be met:
Progxam
W _'_l—I_|—
ip'CCC'N p"'C7,sh
DIN I II 80 ' , 10 ,
R/E :E,: I
100ns min
Program Prohibition
DIN l II 80 , , 10 ,
R/IT I (
100ns min
WE I l I l
pC.CPh
DIN I , 60 ,
100 ns min
Erase Prohibition
p'",'.:".'.?')
W _1 M
ip''''7,Th
DIN I II 60 ,
R/E _ el
100ns min
1998-06-18 28/34
TOSHIBA TC58V32AFT/ADC
(10) In the case that 4 address cycles are input
Although the device may acquire the fourth address, it is ignored inside the chip.
Read operation
ALE / )
"s-CD-t H H A-
OOH, 01H or 50H Address input ignored
R/IT \
Internal read operation starts when WE in the third cycle goes high.
Figure 22.
Proggam ogeration
Data input
Address input
wo-er-ily-t H H l" H H Y--
"------------"
ignored
Figure 23.
1998-06-18 29/34
TOSHIBA TC58V32AFT/ADC
(11) Divided program in the same page (Partial page program)
The device allows a page to be divided into 10 segments (maximum) with each page segment
programmed individually as follows:
The first programming
Column A Col
Page N Data Pattern)
The second programming
Page N Data Pattern 2
The third programming
Column E Column F
Page N Data Pattern?
Result
Column A Column B ColumnC ColumnD ColumnE ColumnF
Page N Data Pattern1 (Datapattern2, ',' Data Pattern3
Figure 24.
Note: The input data for unprogrammed or previously programmed page segments must be '1'.
(Le. Mask all page bytes outside the segment to be programmed with 'I' data.)
(12) Notification for TTfif Signal
The internal column address counter is incremented synchronously with the "t'1'i''tl" clock in the read
mode. Therefore, once the device is set into the read mode by the '00H', '01H' or '50H' command,
the internal column address counter is incremented by the RE clock independent of (before or after)
the address input. Assuming that the TtTi-f clocks are inputted before address input and the pointer
reaches the last column address, internal read operation (array-' register) will occur and the device
will be in the busy state. (Refer to Figure 25)
Address input
00H/01H
l/O
t( >< F/ l
Figure 25.
Therefore, "rt-lil'" clocks must occur after the address input.
1998-06-18 30/34
TOSHIBA TC58V32AFT/ADC
(13) Invalid block (bad block)
The device contains unusable blocks. Therefore, the following issues must be recongnized:
Check if the device has any bad blocks after device installation
into the system. Do not try to access bad blocks. A bad block
- Bad Block does not affect the performance of good blocks becasue it is isolated
from the bit line by the select gate.
The number of valid blocks is as follows:
MIN TYP MAX UNIT
_ Bad Block
Valid (Good) Block Number 502 508 512 Block
Figure. 26 Figure 28 shows the bad block test flow.
(14) Failure Phenomena for Program and Erase Operations.
The device may fail during program or erase operation.
The following possible failure modes should be considered when inplementing a highly reliable
system.
FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE
Block Erase Failure Status Read after Erase -9 Block Replacement
Page Program Failure Status Read after Prog. -9 Block Replacement
Single Bit* Program Failure (1) Block Verify after Prog. -9 Retry
'1'-r'0' (2) ECC
* : (1) or (2)
o ECC : Error Correcting code - Hamming Code etc.
Example .' 1 bit correction & 2bit detection.
0 Block Replacement
Program
error occurs
When an error happens in Block A, try to
Buffer
memory
reprogram the data into another (Block B) by
) Block A loading from an external buffer. Then, prevent
further system accesses to Block A ( by creating
a 'bad block' table or an another appropriate
) Block B scheme.)
Figure. 27
When an error occurs for an erase operation, prevent future accesses to this bad block
(again by creating a table within the system or other appropriate scheme).
1998-06-18 31/34
TOSHIBA TC58V32AFT/ADC
BAD BLOCK TEST FLOW
C : Checker board pattern
T: : Invert checker board pattern
Blank check : 1 Block read (FFH)
Test Start
Block No = 1
Block No = 1
C- Patt Proc
Read(00H) Fail
BNO. = BNo.+1l-
Fail No
Erase Bad
Pass . Block BNO. = 512
/C- Patt Prog Yes
Read(00H) Fail
Block Fail
B No. = 512 No
Figure 28.
ATTENTION
(1) Avoid bending or subjecting the card to sudden impact.
(2) Avoid touching the connectors so as to avoid damage from static electricity.
This card should be kept in the antistatic film case when not in use.
(3) Toshiba cannot accept, and hereby disclaims liability for, any damage to the card including data
corruption that may occur because of mishandling.
1998-06-18 32/34
TOSHIBA TC58V32AFT/ADC
PACKAGE DIMENSIONS
Plastic TSOP
TSOP ll 44/40 - P - 400 - 0.80B
UNITS : mm
44 35 32 23
?HHHHHHHHHH HHHHHHHHHHW d d
10.16i0.1
11 76:0 2
_i?"i,ll"1'it HHHHHHHHHHJ , L "sl
1 10 13 22
0.805TYP “0.31-0.05m
L 18.81MAX
L 18.41i0.1 $1 g 48.
, O N 95
l T, F, m
_ajirtjri-
01i0 05
1998-06-18 33/34
TOSHIBA TC58V32AFT/ADC
PACKAGE DIMENSIONS
FDC -22A
UNITS: mm
37 0:01
h5.0:0.1
2-A.2MIN g Jlht.,1..g3, Fa
k - _ .. Apt,
fit DI-Ilil
r/rrrrrrrreirrrrr
t' 44 Anna
/\__,/‘\
_.-.-"
TSi] [2.251
Contact area (2 : 1)
E: Write protect area
F: The distance between the surface of D and all contact areas is less than 0.1 mm.
G: Index area
1998-06-18 34/34
www.ic-phoenix.com
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