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TC5832FT
32 MBIT (4M X 8 BITS) CMOS NAND E2PROM
TOSHIBA TC5832FT
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
32 MBIT (4M x 8BITS) CMOS NAND EZPROM
DESCRIPTION
The TC5832FT device is a single 5.0-volt 33 M (34,603,008) bit NAND Electrically Erasable and
Programmable Read Only Memory (NAND EEPROM) organized as 528 byte X 16 pages X 512 blocks.
The device has a 528-byte, static register which allows the program and read data to be transferred
between the register and the memory cell array in 528-byte increments. The Erase operation is
im lemented in a single block unit (8 Kbytes + 256 bytes: 528b1ytes M 16Eages).
he TC5832FT is a serial type of memory device which uti izes the 0 pins for both address and
data input/output as well as command inputs. The Erase and Program operations are automatically
executed, making the device most suitable for applications such as solid state file storage, voice
recording, image file memory for still cameras and other systems which require high-density, and non-
volatile memory data storage.
FEATURES
0 Organization 0 Power supply
Memory cell array 528 M 8 K M 8 VCC = 5.0V i 0.5V
Register 528 X 8 0 Access time
Page size 528 bytes Cell array- Register 10 ps max
Block size (8K + 256) bytes Serial Read Cycle 50 ns min
tt Mode 0 Operating current
Read, Reset, Auto Page Program Read(50ns cycle) 15mA typ
Auto Block Erase, Suspend/ Resume Program(ave.) 40mA typ
Status Read Erase (ave.) 20 mA typ
0 Mode control Standby 100 PA
Serial input/output 0 Package
Command control 400mi1 TSOP T e11
TC5832FT : TS 11 44/40 - P - 400 - 0.80B
(Weight : 0.48 g Typ.)
PIN ASSIGNMENT (TOP VIEW)
TC5832FT PIN NAMES
............ tyi'''''''''''''"''''',':','"'';)',])'''.':
lie c; fi' 3% I/OI to8 " port
ALE E3 42 DE 2 E Chi E bl
.WE4 412lR/Eé IP nae
i....y7.e..JC.5. .................... 4 .cl...o.e....i m Write Enable
NC I: 6 39 Cl NC -
NC l: 7 38 Cl NC RE Read Enable
HE E g :2 amg CLE Command Latch Enable
NC I: " 2 Cl NC ALE Address Latch Enable
12 33 W Write Protect
NC I: 13 32 Cl NC _
NC I: 14 31 Cl NC R/B Ready/Busy
I: Cl . .
mg :1: 23sh-l,Q op Optionpin
..... NCC1.7............_....2..t.CCl..N.c..... V p s I
i I/OI l: 18 27 Cl I/082 CC ower upply
é um [I 19 26 211/07 5 Vss Ground
l/O3 C20 2521i/062
a l/O4 E 21 24 Cl l/O5 2 OP : GND Input : 528 Byte/Page Operation
i....y.ss.1.p.?. .................. 2 .3...rl.i../.c.c....i Vcc Input : 512Byte/Page Operation
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operatin ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and con itions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1997-08-1 2 1/38
TOSHIBA
BLOCK DIAG RAM
r Status register
Vcc Vss
I/O1o_ ( l Address register II = Column buffer
to i Ilodcrgsiirol I" a 5 Column decoder
I/O tyor-r _ Command register I t? Data register
" . Sense amp
CE o-r , B
W f R d
CLE o-F a f o e
ALE o-r Logic antrpl g f ll' f, Memory
W C. control circuit r g g % cell array
E Cr-r f, f
7P CY-F g
ABSOLUTE MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
Vcc Power supply - 0.6 to 7.0 V
VIN Input Voltage - 0.6 to 7.0 V
Vl/O Input /Output Voltage - 0.6V to Vcc + 0.5V (E 7.0V) V
PD Power Dissipation 0.5 W
TSOLDER Soldering Temperature (10s) 260 ''C
TSTG Storage Temperature - 55 to 150 T
TOPR Operating Temperature 0 to 70 ''C
CAPACITANCE *(Ta = 25°C, f = 1 MHz)
SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT
Cm Input VIN = 0V - 5 10 "
Cour Output VOUT = 0V - 5 10 "
* This parameter is periodically sampled and is not tested for every component.
TC5832FT
1997-08-1 2 2/38
TOSHIBA TC5832FT
VALID BLOCK m
SYMBOL PARAMETER MIN "f),,"' MAX UNIT
NVB Valid Block Number 502 508 512 Blocks
(1) The TC5832FT occasionally contains unusable blocks. Refer to Application Note (17)
toward the end of this document.
DC RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN TYP MAX UNIT
Vcc Power Supply 4.5 5 5.5 V
Ve High Level Input Voltage 2.2 - Vcc + 0.5 V
" Low Level Input Voltage - 0.3* - 0.8 V
* - 2V (pulse width s 20 ns)
DC CHARACTERISTICS (Ta = 0° to 70°C, Vcc = 5.0V i 0.5V)
SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT
IIL Input Leak Current " = 0V to Vcc - - i 10 yA
Lo Output Leak Current VOUT = 0.4V to Vcc - - + 10 ,uA
lccol Operating Current (Serial Read) CE = VIL, Iout = 0mA, tcyde = 50 ns - 15 30 mA
lccog Operating Current (Command Input) tcycle = 50 ns - 15 30 mA
'ccoa Operating Current (Data Input) tcycle = 50 ns - 40 60 mA
Iccos Operating Current (Address Input) tcycle = 50 ns - 15 30 mA
Icco7 Programming Current - - 40 60 mA
lccog Erasing Current - - 20 40 mA
Iccs1 Standby Current E = VIH - - 1 mA
lccsz Standby Current E = Vcc - 0.2V - - 100 yA
VOH High Level Output Voltage IOH = - 400,;A 2.4 - - V
VOL Low Level Output Voltage IOL = 2.1 mA - - 0.4 V
IOL(R/§) Output Current of (R/E) Pin Vor, = 0.4V - 8 - mA
1997-08-1 2 3/38
TOSHIBA
TC5832FT
AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = 0° to 70°C, Vcc = 5.0V i 0.5V) (1)
SYMBOL PARAMETER MIN MAX UNIT NOTE
tcu; CLE Set-Up Time 0 - ns
tcLH CLE Hold Time 10 - ns
tcs E Set-Up Time 0 - ns
tCH E Hold Time 10 - ns
twp Write Pulse Width 25 - ns
tALS ALE Set-Up Time 0 - ns
tALH ALE Hold Time 10 - ns
tos Data Set-Up Time 20 - ns
tDH Data Hold Time 10 - ns
twc Write Cycle Time 50 - ns
tWH m High Hold Time 15 - ns
tww W High to W Low 100 - ns
tRR Ready to E Falling Edge 20 - ns
tRp Read Pulse Width 35 - ns
tRC Read Cycle Time 50 - ns
tREA E Access Time (Serial Data Access) - 35 ns
km E High Time for the Last Address in Serial Read Cycle 100 - ns (3)
tREAID E Access Time (ID Read) - 35 ns
tOH Data Output Hold Time 10 - ns
tRHZ E High to Output High Impedance - 30 ns
tCHz E High to Output High Impedance - 20 ns
tREH E High Hold Time 15 - ns
th Output High Impedance to E Falling Edge 0 - ns
tRSTO E Access Time (Status Read) - 35 ns
tcho E Access Time (Status Read) - 45 ns
tRHW E High to W Low 0 - ns
tWHC W High to E Low 30 - ns
tWHR W High to E Low 30 - ns
tAm ALE Low to E Low (ID Read) 100 - ns
tcR E Low to E Low (ID Read) 100 - ns
tR Memory Cell Array to Starting Address - 10 pd
twe W High to Busy - 200 ns
tAR2 ALE Low to E Low (Read Cycle) 50 - ns
tRB E Last Clock Rising Edge to Busy (in Sequential Read) - 200 ns
tcor E High to Ready (in Case of Interruption by E in Read Mode) - 600 ns (2)
tRST Device Resetting Time (Read/Program/Erase/after Suspend Command) - 6/10/500/5 pd
AC TEST CONDITIONS
Input level : 2.4 V / 0.6 V
Input comparison level : 2.2 V/ 0.8 V
Output data comparison level .' 2.0V/ 0.8V
Output load
1TTL & CL (100 pF)
1997-08-1 2 4/38
TOSHIBA
(1) Transition time (Up) = 5 ns
TC5832FT
(2) The W High to Ready time depends on the pull-up resistor tied to the R/B pin. (Refer to
Application Note (10) toward the end of this document.)
(3) If the delay between IIT?" and CT?" is less than 200 ns and tCEH is greater than or equal to 100 ns,
reading will stop.
If the m-to-CF delay is less than 30 ns, the device will not turn to the Busy state.
tCEH 2 100 ns
* " or "
525 526 527
509 510 511
(b): 0 to 30ns
-9 Busy signal is not output.
PROGRAMMING AND ERASING CHARACTERISTICS (Ta = ty' to 70°C, Vcc = 5.0V , 0.5V)
SYMBOL
PARAMETER MIN TYP MAX UNIT NOTE
tpROG Average Programming Time 300 1500 M;
N Number of Programming Cycles on Same Page 10 (1)
tBERASE Block Erasing Time 6 50 ms
tSR Suspend Input to Ready 0.5 ms
P/E Number of Program/Erase Cycles 1 x 105 (2)
(1) Refer to Application Note (15) toward the end of this document.
(2) Refer to Application Note (18) toward the end of this document.
1997-08-1 2 5/38
TOSHIBA TC5832FT
TIMING DIAGRAMS
Latch Timing Diagram for Command/Address /Data
(iii-i) tii' W
M Set-Up Time Hold Time
tos tDH
l/Ol t
to 8 L
I " or "
Command Input Cycle Timing Diagram
) tCLS tCLH \
ltcs _ CH
6 \ f'?
WE ire/
tALs tALH
ALE fl F"
tos tDH
I " or "
1997-08-1 2 6/38
TOSHIBA
Address Input Cycle Timing Diagram
TC5832FT
tcs '." twc twc
tWH tWH
twp twp twe
m 2 N 2 , l
tALs tALH
ALE I g
tos tDH tos tDH tos tDH
’ - Hr
J- - -
I/O1 to8 tit A0to7 - A9to16 - A17 to 21 V
I " or "
Data Input Cycle Timing Diagram
CLE F"
twp tWH twp twp
tDS tDH tDS tDH tos tDH
- - "'% r -"% r "'% _
J- f- 527
l/01toa DINO F" Ai); DIN1 Eitiiii)irrhN 511
*OP = GND input: DlN 527
= Vcc input : DIN 511
: " or "
1997-08-1 2 7/38
TOSHIBA TC5832FT
Serial Read Cycle Timing Diagram
V01 to 8
Status Read Cycle Timing Diagram
V01 to 8
* 70H-70 in HEX data : " or "
1997-08-1 2 8/38
TOSHIBA
Read Cycle (1) Timing Diagram
TC5832FT
CLE tCLs tCLH
t tcH tCEH
E ltr' dt A 1 A
m , - l sl A d! l sl tR tCRY
tALS t
ALC - tAR2
ALE , Eil
tALH " ' tRR tRC
W L/N/N/I (c)
tos tDH tDS tDH tos tDH tos (ti); _ 4 tREA
V01 "'A0 to A9 to "'A17 to t Dom Do
H UT ..... D -
to 8 00 EY: A7 A16 N A21 t N N +1 N + 2 OUT
Column address t
N*** RB
- -,r-
RIB l / ** OP= GND input: DIN 527 Nu/
I = Vcc input 1 DIN 511
I " or "
Read Cycle (1) Timing Diagram: Interrupted by CE
CLE tr, tCLHS
tcs CH
E 'sir' gh A gh
7 -r - -
WE Li Lil L! Ic,? te tCHZ
tALS tALI-L 'tAit2
ALE v Eih
tALH WB tRR tRC tRHZ
tos tDH fps, th tos tDH tDS tr-
l/O1 00H FAO to A9 to "'A17 tot
to 8 I -'k A7 al A16 ik A213!
Column address
R/E " f
*** Read Operation using 00H Command N: 0 to 255
: " or "
1997-08-12 9/38
TOSHIBA
Sequential Read Timing Diagram
TC5832FT
Column
address
address
0D F)-tt
Page M
access
l-,e-s/
Page M + 1
access
**OP= GND input: Door 527
= Vcc input 1 DOUT 511
I " or "
1997-08-12 10/38
TOSHIBA TC5832FT
Read Cycle (2) Timing Diagram
CLE tcu; tCLH '
-\r* tseg a JI
m m \f\_/’\_/ w
_ tALs " tum 4 ttut2
tALH __
ALE l W" /
tALH tRC
E R / I / \ )
tos tDH tDs tDH -
_ ’ tRR l tREA **
POI -f A0 to A9 to A17 to \ -
Column address 256 + M 256 + M +1
RIB l / **OP=GND input: DOUT 527
=Vcc input 2 DOUT 511
I " or "
Read Cycle (3) Timing Diagram
CLE atas tCLH '
tcs tCH
E -N Wish JI tl
_f. _ - -
WE U icC)c/\)- tse
tALS tum taR2
tALH -
ALE "W"
tao, - tec
RE tos tDs ' / S I l I
tDH tDH
9 = tREA **
l/OI "A0 to A9 to A17 to \ -
to 8 50H ty'" Ad)!':. A7 A16 A21 / DOUT - DOUT (oou4
Column address 512 + M 512 + M +1
MT l zf
k_/ **OP=GND input: Door 527
Do not input Vcc
: " or "
1997-08-12 11/38
TOSHIBA TC5832FT
Auto Program Operation Timing Diagram
CLE tcLs S / W % '
tci tCLH
E 'N - , f'" % til
tCH 33
W Cyl Kim Lr)c/")c/\) W% lc,
ALH |otALs AL
+ tALS
ALE if I
E t t t 1c/-
DS DS t
tor. tDH Dos tDH DS tDH
POI - A0 to A9 to A17 to DIN DIN Status
to 8 80H tN A7 - A16 A21 0 1 Dm: 10H 70H output
*OP=GND input: DlN 527
=Vcc input I DIN 511
: " or " , : If data is being output, do not allow any input.
Auto Block Erase Timing Diagram
EE_JtCLsS / If''" AA/ l_diiiiiiiif
_ tCLs
- tCCH f" Al a f"
m‘UZ” Lt,u,, \JLW Ai')c/
tALS tBERASE
E W" A \ /
I/OI A9 to A17 to
to 8 60H t A16 X A21 )(F" Ai)( DOH 70H outDut
Auto Block Erase Erase Start Status Read
Set-Up command command
command VVVVVVVVV
oooooow
2S?SNSNSN
oooooo
.o.....
NRRRRS6 Cl O
aanaasmm
: If data is being output, do not allow any input.
I " or "
1997-08-12 12/38
TOSHIBA
Suspend/Resume Block Erase Operation Timing Diagram
TC5832FT
- / W" til -f WW)
CLE / i, tl
(ECLS tCLs tcLs ' 4 tCLH
tCL-l tc H )2
a 1 % fl tcs -yt/,',
l4» twp '
tcs twe W"
m N X ?'_\_7_\_/ W % N l
- tALs - - l I
t tALH
tALH - ALH ,3
ALE - R f" % f/Az
o tDH tDH tos t
0 - tDH
l/OI 2 60H A9 to fai5iWi5iW5iiW5ii5iii BOH
to 8 -5. A16 ' t
- tSR. I
CLE WL/ \
l tc.s
CE % tcs t%A a
t -,r- +
d'gEEEir'sscr W/ C/
ll. 4 tALH _
ALE / i 2,
*e / / Riiiiit-tiw 'U/
ll tos
DS tRSTO
(a): Continued
Status
output
I " or "
: If data is being output, do not allow any input.
1997-08-12 13/38
TOSHIBA
TC5832FT
ID Read Operation Timing Diagram
tCLS l
_ tCH JCLS
tcs t cs
E S il S
1Arcri
WE C) tALS C) CR
tALH tcH tAR1
'rii tos sr_m /
l/Ol , L l
to 8 -R, 90H f-CC) l 98H -I 6BH f
5 tREAID tREAID 5
Address input Maker code Device code
: " or "
1997-08-12 14/38
TOSHIBA
TC5832FT
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information. The
device pin-outs are configured as shown in Figure I.
Command Latch Enable: CLE
The CLE input signal is used to control the acquisition of the
operation mode command into the internal command register. The
command is 1atehetripto the command register from the I/O port on the
rising edge of the WE signal while CLE is high.
Address Latch Enable: ALE
The ALE signal is used to control the acquisition of either address
information or input data into the internal address/tutter-register.
Address information is latched on the rising edge of WE if ALE is high.
Input data is latched if ALE is low.
Chip Enable: Cl
The device goginto a low poweritandby mode during a Read
operation when CE goes high. Th_e CE signal is ignored when the
device is in the Busy state (R/B = L), such as during a Proglam or
Erase operation, and will not go into Standby mode even if a CE high
signal is input. The CE signal must stay low during the Read mode
Busy state to ensure that memory signal array data is correctly
transferred to the data register.
Write Enable: Tirtl"
The 1hTtf signal is used to control the acquisition of data from the I/O port.
Read Enable: W
E 1 Ns.p' 44 Eva
l: 2 43 Clc7
I: 3 42 21%
I: 4 41 ENE
I: 5 40 Clop
'tsw TOP "?sp
“v VIEW "v
E 18 27 Cl I/O8
I: 19 26 Cl l/OT
l: 20 25 Cl l/O6
l: 21 24 Cl IIOS
[I 22 23 Clvcc
Figure l. Pinout
The It-E signal controls serial data output. Data is available tREA after the falling edge of W.
The internal column address counter is also incremented (Address + 1) on this falling edge.
I/O Port: I/O 1 to 8
The I/O 1 to 8 pins are used as the port for transferring address, command and input/output data
information to or from the device.
Write Protect: WP
The WP signal is used to proteit the device from accidental programming or erasing. The internal
voltage regulator is reset when WP is low. This signal is usually used for protecting the data during
the power on/off sequence when input signals are invalid.
Ready/Busy: It/g
The R/E output signal is used to indicate the operating condition of the device. The R/E signal is in
the_Busy state (R/B = L) durin the Pro ram, Erase or Read operations and will return to Ready state
(R/B = H) after completion of t e operation. The output buffer for this signal is an open drain.
Option Pin: OP
The OP signal is used to change the page size. The device is in 528 byte/page mode when OP =
GND, and 512 byte/page mode when OP = Vcc.
1997-08-12 15/3
TOSHIBA TC5832FT
Schematic Cell Layout and Address Assignment
The Program operation is implemented in a page units while the Erase operation is carried out in
block units.
A page consists of 528 bytes in which 512 bytes are for
, main memory and 16 bytes are for redundancy or other
) 16 pages -9 1 block
1 Page = 528 bytes
1 Block = 528 bytes M 16 pages = (8 K + 256) bytes
Total Device Density = 528 bytes X 16 pages X 512 blocks
= 33 Mbits (4.125 Mbytes)
8192 l
512 blocks L -
The address is acquired through the I/O port over
three consecutive clock cycles, as shown in Table I.
_______._____ _______4_
Figure 2. Schematic Cell Layout
Table l. Addressing
I/OI IIO 2 IIO 3 IIO 4 " 5 l/O 6 " 7 l/O 8
A0 to A7 : column address
First cycle A0 A1 A2 A3 A4 A5 A6 A7 A9 to A21 2 page address
A13 to A21: block address
Second cycle A9 A10 A11 A12 A13 A14 A15 A16 (ti to A12 : NAND address in block)
Third cycle A17 A18 A19 A20 A21 * L * L * L
*: A8 is initially set to "Low" or "High" by a "00H" Command or a "01H" Command.
*: |/06 to 8 must be set low in the third cycle.
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read, Erase Suspend and Reset are controlled by the
eleven different command operations shown in Table 3. Address input, command input and data
input/output are controlled by the CLE, ALE, CE, W, m and W signals, as shown in Table 2.
Table 2. Logic Table
CLE ALE E W K W
Command Input H L L _|_/l\_ H *
Data Input L L L _|_/i\_ H *
Address Input L H L U H *
Serial Data Output L L L H -TIcl- *
During Programming (Busy) * * * * * H
During Erasing (Busy) * * * * * H
Program, Erase Inhibit * * * * * L
H: VIH, L: VIL: *: " or "
1997-08-12 16/38
TOSHIBA TC5832FT
Table 3. Command table (HEX data)
FIRST CYCLE SECOND CYCLE ACCEPTABLE COMMAND
WHILE BUSY
Serial Data Input 80 -
Read Mode (1) 00 -
Read Mode (2) 01 -
Read Mode (3) 50 -
Reset FF - CD
Auto Program 10 -
Auto Block Erase 60 D0
Suspend In Erasing BO - O
Resume D0 -
Status Read 70 - C)
ID Read 90 -
Bit assignment of HEX data
(Example)
Serial data input: 80H
A \f A \
|1|0|0|0|0l0|0l0|
I/08765432I/o1
Once the device is set to Read mode by the ''00H", "01H" or "50H" command,
additional Read commands are not needed for sequential page Read operations.
Table 4 shows the operation states for Read mode.
Table 4. Read mode operation states
CLE ALE E W E I/OI TO l/O8 POWER
Output Select L L L H L Data output Active
Output Deselect L L L H H High impedance Active
Standby L L H H * High impedance Standby
HIVIH LZV|L *: " or "
1997-08-12 17/38
TOSHIBA TC5832FT
DEVICE OPERATION
Read Mode LI)
Read mode (1) is set by issuing a '00H' command to the command register. Refer to Figure 3
below for timing details and a block diagram.
CLE Cl
E_\%%%
mL/UUM
ALE_/—\
Start address input A data transfer operation from thicell array to the
register starts on the rising edge of WE in the third cycle.
W 511 or 527 (after the address information has been latched.) The device
' i will be in the Busy state during this transfer period. The E
signal must stay low after the third address input and during
Busy state.
A _, Cell array After the transfer period the device returns to Ready_
state. Serial data can be output synchronously with the RE
clock from the starting pointer designated in the address
Figure 3. Read mode (1) operation input cycle.
Select page -F s.
Read Mode tLO
E_\ m m Ea
m LI LI LI lf
Start address input
-25/'zl-511o/5-27, The operation of the device after input of the "01H" command is
. the same as Read Mode(1). If the starting pointer is to be set after
Select page i.' column address 256, use Read Mode (2).
N -t, 5 Ad Cell array However, for a Sequential Read, output of the next page starts
. A" from column address 0.
Figure 4. Read mode (2)0peration
1997-08-12 18/38
TOSHIBA TC5832FT
Read Mode 131
Read mode (3) has the same timing as Read modes (1) and (2) but is used to access information in
the extra 16-byte redundancy area of the page. The starting pointer is therefore assigned between
bytes 512 and 527.
CLE Cl
EjW/A%%
IIO (50HF()-(l CHD-CHD- ........
A0 to A3
512 527
I A V A" 1 = Addresses A0 to A3 are used to set the starting pointer for
g the redundant memory cells, while A4 to A7 are ignored.
Once the "50H" command is set, the pointer moves to the
A A redundant cell locations and only those 16 cells can be
"V "ity' addressed, regardless of the A4 to A7 addresses. (The "00H"
command is necessary to move the pointer back to the 0 to
Figure 5. Read mode(3)operation 511 main memory cell locations.)
Read mode (3) operation is invalid when OP is at the Vcc level.
Se uential Read(1)(2)(3)
This mode allows the sequential reading of pages without additional address input.
ii'jiy 's----------" tit _----------" tR 's-s,,------' tR
1CstE Address input 4—, Data output A-F Data output A-F
Busy Busy Busy
0 527 (01H) (50H) 512 527
Sequential Read (1) Sequential Read (2) Sequential Read (3)
Sequential Read modes (1) and (2) output addresses 0 to 527 as shown above while Sequential
Read mode (3) outputs the redundant address locations only. When the pointer reaches the last
address, the device continues to output the data from this address ** on each TTIT clock signal.
** OP-- GND : column address 527.
Vcc : column address 511.
1997-08-12 19/38
TOSHIBA TC5832FT
Status Read
The device automatically implements the execution and verification of the Program and Erase
operations. The Status Read function is used to monitor the Ready/Busy status of the device, determine
the pass /fai1 result of a Program or Erase operation, and determine if the device is in Suspend or
Protect mode. The device status is output through the I/O port using the "rt""t"f" clock after a "70H"
command input. The resulting information is outlined in Table 5.
Table 5. Status output table
STATUS OUTPUT
I/OI Pass/Fail Pass : "0" Fail : "1"
I/O2 Not used "O" The Pass/Fail status on I/OI is only valid
l/O3 Not used "O" when the device is in the Ready state.
I/O4 Not used "0"
HO 5 Not used "0"
I/O6 Suspend Suspended: "l" Not Suspended: "o''
I/O? Ready/Busy Ready : "1" Busy : "0"
l/O8 Write protect Protect :"0" Not Protect : "1"
An application example with multiple devices is shown in Figure 6.
E1 E; E3 CEN CE +1
Device Device Device Device Device
1 2 3 N N+1
" l 70H ) g ' ( 70H} J '
“Status on Istatus on
Device 1 Device N
Figure 6. Status read timing application example
SYSTEM DESIGN NOTE : If the R/IT pin signals of multiple devices are common-wired as shown in the
diagram, the Status Read Function can be used to determine the status of each individually selected device.
1997-08-12 20/38
TOSHIBA TC5832FT
Auto Page Program
The device implements the Automatic Page Program operation after receiving a "10H" Program
command after the address and data have been input. The sequence of command, address and
data input is shown below. (Refer to the detailed timing chart.)
Data Input Program command Status Read
command Address Data input command
0 to 527 When OP = GND
0 to 511 When OP = Vcc
I MT automatically returns to Ready after completion.
Data in ut
p Program Read &Verification The data is transferred (programmed) from the register to the
I I selected page on the rising edge of WE following the "10H"
Selected command input. After programming the programmed data is
page transferred back to the register to be automatically verified by
the device. If the program does not succeed, the above
Program/Verify operation is repeated by the device until success is
achieved or until the maximum loop number set in the device is
reached.
Figure 7. Auto Page Program operation
Auto Block Erase
The Auto Block Erase operation starts on the rising edge of WE after the Erase Execution command
"DOH" which follows the Erase Set-Up command "60H". This two-cycle process for Erase operations
acts as an extra layer of protection from accidental erasure of data due to external noise. The device
automatically executes the Erase and Verify operations.
Ciiiir, ---dCiiii,)
_Block address l Erase Start Status Read
Input: 2cycles command command
R/E I Busy I
Suspend / Resume
The device has the ability to suspend the Erase operation to allow Program or Read
operations to be performed on the device. The block diagram and command sequence for this operation
are shown below. (Refer to the detailed timing chart)
Resume command input
Select Suspend command Resume the Erase
block input operation
-tr -tr
Suspend the
Erase operation
........... .w:'firirii, we...--.--------"'"
"s-----------"
Block address input Suspend operation
R/g I I W MN Figure 8. Suspend/Resume Operation
The C52sc,(,;ii2,ee,restee:,e cycle can be repeated up to 20 times duringa Block Erase operation.
After t e Resume command has been input, the Erase operation continues from
the point at which it left off and does not have to be restarted.
1997-08-12 21/38
TOSHIBA TC5832FT
The Reset mode stops all operations. For example, in the case of a Program or Erase
operation the regulated voltage is discharged to 0 volts and the device will go into Wait state.
The address and data registers are set as follows after a Reset:
. Address Register .' All "o''
. Data Register .' All "I"
. Operation Mode : Wait State
The response after an "FFH" Reset command input during each operation is as follows:
When a Reset (FFH) command is input during programming Figure 9.
p"'7.","N p''''',C,Csh p'CC."PN
(80) ‘10, ‘FF, ‘oo,
. Register set
Internal "li'i'_'itsss.,LiF'''"''-'"'"cr.
- 'i' tRST (max IOM;) i
R/B ( "re""-""''''';
When a Reset (FFH) command is input during erasing Figure 10.
( D0 ' ( FF ', CD-
Internal Erase :
voltage '_l-tisss-----,-s.,
':.' i." Register set i.'
MT l i' ii"''"-'"'""""-)
tRST (max 500/15)
When a Reset (FFH) command is input during a Read operation Figure 11.
ms l i,' I
"ir-e.'
. tRST :
(max 6 ps)
When a Reset (FFH) command is input after Suspend Figure 12.
, D0 , , BO ' FF
5 This Reset cancels Suspend status.
Internal Erase
voltage _j-sss, :
It/g I I I I
i tRST i
(max 5 ,us)
1997-08-12 22/38
TOSHIBA TC5832FT
When a Status Read command (70H) is input after a Reset Figure 13.
, 70 U-------, .
v, IIO status 2 Pass/ Fail -ypass
, FF _
u'..'.,.,,?
_- Ready/Busy -aReady
R/B I I
CiiD) (Citi.? , l/O status : Ready/ Busy -9 Busy
R/iT I i' I
When more than one Reset commands are input in succession Figure 14.
(1) (2) (3)
( 10 ', ( FF ) ' FF l CD-
The second CD command is invalid,
but the third Cir) command is valid.
1997-08-12 23/38
TOSHIBA TC5832FT
ID Read
The TC5832 contains ID codes to identify the device type and the manufacturer. The ID codes are
read out using the following timing conditions:
CLE l I
90H 00 98H 6BH
ID read command Address 'oo' Maker code Device code
For the access time of tREAID, tce and tARl refer to AC CHARACTERISTICS.
Figure 15. ID read timing
Table 6. Code table
IIO 8 IIO 7 " 6 IIO 5 IIO 4 IIO 3 IIO 2 IIO 1 HEX DATA
Maker code 1 0 0 1 1 0 O O 98H
Device code 0 1 1 0 1 0 1 1 6BH
1997-08-12 24/38
TOSHIBA TC5832FT
DEVICE PHYSICS
Program Operation
Figure 16 shows the NAND memory cell level details of the programming mechanism. The Program
operation is used to write "o" data into an erased memory cell CI'' data cell) using a tunneling
mechanism. An example Program operation to program "o'' data into TRI and "I'' data into TR2 is as
follows:
(1) A high level is applied to Select line 1 and a low level is applied to Select line 2 so that the
device is connected to the Bit line and disconnected from the ground line.
(2) Vpp (2 20 V) is applied to the selected word line and an inhibit voltage of VPI (sts 10 V) is
applied to the unselected word lines.
(3) 0 volts is applied to the bit line tied to cell transistor TRI and the inhibit voltage VDPI(= 10
V) is applied to the bit line tied to TR2.
(4) Vpp is applied between the control gate and the channel in TR1, as shown in Figure 16, which
causes electrons to be injected from the channel to the floating gate by a tunneling mechanism.
(5) The injected electrons are captured in the floating gate surrounded by an oxide layer and will
remain, even after power is cut off, until they are removed by an Erase operation.
(6) Although 20 volts is applied to the control gate of TR2, the voltage difference between the
control gate and the channel is only 10V because the voltage of the channel is 10 V. Therefore,
tunneling does not take place. (i.e. the electron is not injected into the floating gate.)
(7) Tunneling does not take place in the unselected pages because of the 10V (VPI) applied to
the unselected word lines which makes the voltage difference between the control gate and
channel only 10 volts.
Thus the floating gate of the "o" cell is charged to "Minus" and that of the "I'' cell is charged to
"Plus".
o:/ Bit line VDPI (= 10V) TRI v (= 20V)
Select line 1 t l i
(=10V) VPI Ei E:' (Word line 1) _ ’ 0V
VPI El.” El” (Word line 2) I
VPI Jiy,1 Ji'y,1 (Word line 3) 0V
(as 20V) VPP ll l EH, (Word line 4)
VPI TR1 'ri-ii" TR2 :1: (Word line 5) N
VPI E:' :H (Word line 6)
VPI ll ll (Word line 7) TR2 '
VPI c: C', (Word line 8) VPP (a 20 V)
: |_lll |_lll : ,
:' L,,, 'c, :.' .
.VPI C" C/ (Word line 16) 69636369 . VDPI(z10V)
Select line 2 7;: 7;: g
Select line 1 t t
Figure 16. Program Device Physics
1997-08-12 25/38
TOSHIBA
TC5832FT
Erase Operation
Figure 17 shows the NAND memory cell level details of the Erase mechanism. The Erase operation
is used to turn the "o'' (programmed) cells back to "l" in a block. The captured electrons are pulled
out from the floating gate to the substrate by a tunneling mechanism.
0 volts is applied to the control gate and Vpp (= 20V) is applied to the substrate so that a 20-volt
potential is created and the electrons in the floating gate are pulled out by the tunneling mechanism.
Bit line
Select line
16word lines 0V
(1 block) 0V
I-'open
Select line
Read operation
After programming the state of the memory cell is either "O" Threshold
(minus charge on the floating gate) or "I" (plus charge on the value
floating gate). Each state is indicated as the "threshold voltage
(Vth)" which is a characterization parameter of the MOS +
transistor as shown in Figure 18. The threshold voltage of a
transistor with data "o" is distributed in the "plus" region while a
transistor with data "I'' is distributed in the "minus" region. 0
The distribution band depends on the fluctuation of the transistor.
Figure 17.
VPP (= 20 V)
Vpp (rs 20V)
Erase Device Physics
VPP (= 20 V)
"0" Data cell
Distribution
"1 " Data cell
Distribution
Figure 18. VTH Distribution for "0" and "1" data cells
1997-08-12 26/38
TOSHIBA TC5832FT
Figure 19 shows memory cell level details of the Read operation mechanism:
(1) A high voltage is applied to Select lines 1 and 2 in the block which includes the selected page,
so that the 16 NAND memory cells are connected to the Bit line and ground.
(2) 0 volts is applied to the control gates of the selected page and a high level voltage is applied to
the control gates of the unselected pages.
(3) In Figure 19, transistor TR2 with data "I'' turns on, transistor TR1 with data "o" turns off, and
all other unselected transistors turn on.
(4) The precharged bit line tied to TR2 is discharged through TR2 as cell current flows to ground,
while the precharged bit line tied to TR1 remains high because current does not flow. The sense
amplifiers tied to the bit lines thus sense the voltage levels as "I" and "O" respectively.
- Bit line 's,
Select line 1 f ON t ON
H L,,, ON fl I ll ON
H Ii“ ON |:H ON
H :H ON Ii” ON
Selected page L TR1 E901; THERE“:
H 1iif,iierl " ON
H q",, ON Ii“ ON
H Ii” ON :H ON
H IE“ ON 5” ON
H L,,, ON l-,,, ON
C" A C'
Select line 2 l I
g' ON e-----" gl ON
Cell current
Figure 19. Read Device Physics
1997-08-12 27/38
TOSHIBA TC5832FT
APPLICATION NOTES AND COMMENTS
(1) Prohibition of unspecified commands
The operation commands are listed in Table 3. Data input as a command other than the specified
commands in Table 3 is prohibited. Stored data may be corrupted if an unspecified command is
entered during the command cycle.
(2) Pointer control for "00H", "01H", "50H"
The device has three read modes which set the destination of the pointer. Table 7 shows the
destination of the pointer, and figure 20 shows a block diagram of the modes' operations.
0 255 256 511 512 527
Table 7. Pointer Destination
READ MODE COMMAND POINTER (LU) ..................... lll ........................ (LU; ..... l
(1) 00H 0 to 255 l I /
(2) 01H 256 to 511
(3) 50H 512 to 527 00H -F
01H -F Pointer control
Figure 20. Pointer control
The pointer is set to region "A" by the "00H" command, to region "B" by the "01H"
command, and to region "C" by the "50H" command.
(Example)
The "00H" command needs to be input to set the pointer back to region "A" when the
pointer is in region "C".
"---s.--------" "--s.--------"
"s----------"
Address Start point Address Start point Address DlN Start point
A area C area C area
00H 50H 00H 80H
c-v-Act'.':'; -v-/c-v--N2'.'d?-v--/ c-v-At':'.'.?-,,-." u-v.--'
Address 1 Address + Address + Address DIN
Start point Start point Start point Start point
A area C area A area A area
(CiEi1z:rr---...: 01H l , 80H k
C(tE) "s-----------" s------------).".,';'--------------"
Address Start point Address Start point Address DlN Start point
A area B area A area
To program region "C'' only, set the start point to region "C" using the "50H" command.
If region "C" .only is to be programmed, or if OP-- Vcc, the contents of the data register must
be set to "1"i 1n advance us1ng the "FFH" command.
FFH 50H 80H 10H
V.'.L".,V .
Address DIN Start point
C area
8 H 10H
0 _s'2'.',.'./
Address DIN O to 511
OP = Vcc Start point
A area
Figure 21. Example for Pointer Set
1997-08-12 28/38
TOSHIBA TC5832FT
(3) Acceptable commands after Serial Input command "80H"
Once the Serial Input command ("80H") has been input, do not input any command other than
the Program Execution command ("10H") or the Reset command ("FFH") during programming.
CiiD "sJ.,F..,,,v"
m -Llililit
"-s-----"
Address '.
Internal Vpp input i'
R/E \ I
Figure 22.
If a command other than "10H" or ''FFH" is input, the Program operation is not performed.
80 XX . 10
CiD 'sd22.9 'se.) For this operation,
Other command Programming cannot be executed. the "FFH" command is needed.
(4) Status Read during Read operation
Command CD
c-s-l Cl
W Ll Cl Ul LI
MT l l I
- I ......
RE Address N Status read Cl L/N/T
. ['-_'-'l
command Input K
Status read Status output
Figure 23.
The device status can be read out by inputting the Status Read command "70H" in Read mode.
Once the device has been set to Status Read mode by a "70H" command, the device will not return to
Read mode.
Therefore, Status Read during a Read operation is prohibited.
However, when the Read command "00H" is input during [A], Status mode is reset and then the
device returns to Read mode. In this case, data output starts from address N without the need for
address input.
1997-08-12 29/38
TOSHIBA TC5832FT
(5) Suspend command "BOH"
The following issues need to be observed when the device is interrupted by a "BOH" command
during block erasing.
60 D0 BO 70
_ Recovery'
time (500 trs)
Figure 24.
The device status changes from Busy to Ready when "BOH" is input. However, the following two cases
cannot be distinguished from one another.
- After a "BOW' command input, Busy- Ready
- After an Erase operation is completed with a "DOH" command, Busy- Ready
Therefore, the device status needs to be checked to see whether or not the "BOH" command has been
accepted by issuing a "70H" command after the device goes to Ready.
Ca? The device responds as follows when a "DOH" command (Resume) is input instead of "70H".
- "BOH" has been accepted: Erase operation is executed. (The device is Busy.)
- "B0H" has not been accepted. (Erase operation has been completed)
.' "DOH" command cappot be accepted. (The device is Ready.)
The two cases above can be checked by monitoring the WB signal.
(6) When auto programming fails.
/ h Fail f'''''.':,':"', f''rrm,
80 10 70 VD 80 10
(Ciiiih,, s-Nd:.,',,." lu'.'.'--''--- s-NUI.;
Address Data Address Data
M input N input
If the programming result for page address M is "Fail", do not try to
program the page to address N in another block. Because the previous input
data is lost, the same sequence of "80H" command, address and data input is
necessary.
Figure 25.
1997-08-12 30/38
TOSHIBA TC5832FT
(7) Data transfer
The data in page address M cannot be automatically tranferred to page address N. If the following
sequence is executed, the data will be inverted. (i.e. "l" data will become "O'' and 'O'' will become
(00> f80', flo', '70',
Address Address
M N Program
Inverted data will be transferred.
Figure 26.
(8) Block Erase after Suspend command "BOH"
(60) CDO', CBO', 'tso',
"s-s---' Vl"2,',.,/ Nd2'.V Nd.':.',."
Block l l
address Erase start Suspend
A Block Erase command is prohibited when the device has been suspended by the input of a "BOH"
command during a Block Erase operation. Only a Program or Read operation is allowed during this Erase
Suspend interruption.
(9) Interruption of block erasure
After the input of a"B0H" command, neither a Program nor a Read operation is allowed for the
block which is currently being erased
Block address A Interruption of block A is prohibited.
1997-08-12 31/38
TOSHIBA TC5832FT
(10) MT.. Termination for the Ready/Busy pin (R/IT)
A pull-up resistor must be used for termination because the MT buffer consists of an open drain
circuit.
CC Ready
Vcc R i' . . i.
De ice _ g : . B s . : 5
VI _1_ RIB i i u y y, 2 ..:
" 1 CL 5 i . I
Vcc = 5.0V
Vsns 1.5 ps Ta = 25°C 15 ns
7; t Cr, = 100 PF
Figure 27. t, LO ps 10 ns
This data may vary from device to device. 0.5ps 5 ns
We recommend that you use this data as a 5
reference when selecting a resistor value. 0 I I I I
1 KO 2 KO 3 KO 4 KO
(11) Status after Power On
Although the device is set to Read mode after power-up, the following sequence is needed because
all input signals may not be stable at power on.
Power on ( FF ) ( oo ',
Reset Read mode (1)
Figure 28.
(12) Power On/Off Sequence:
The WP signal is useful for protecting against data corruption at power on/off. The following
timing is necessary:
4.5 V : i tt
4.2V i.. i
i.' i.' I)
0 V . :
: . ((
don't /5
care :
Cg, m, kt' :
DLE, ALE i.' i. "
VIL i i' VIL
W - i Operation
..F.’...
Figure 29. Power On/Off Sequence
1997-08-12 32/38
TOSHIBA TC5832FT
(13) Set-up for 1Trri Signal
The Erase and Program operations are automatically reset when WP goes low. The following
conditions must be met:
Program
m —'_l—I_l—
J'''',C,'.PN f"".C?ss
DIN I l,' 80 ' , 10 ,
MT _ |—
100 ns min
W _'_l—|_|—
I :{ 60 ) ( D0 ',
R/E 'e-w,' |—
100 ns min
1997-08-12 33/38
TOSHIBA TC5832FT
(14) When four address cycles are input
Although the device may acquire the fourth address, it is ignored inside the chip.
Read operation
ALE / )
v-CD-t H H A-
00H, 01H, or 50H Address input ignored
Internal read operation starts when 1TtTif goes high in the third cycle.
Figure 30.
Progamming operation
vo-WHY-ty-tHy-ty-ty-tH)---
's-----------" 's------------------"
Address input i Data input
ignored
Figure 31.
1997-08-12 34/38
TOSHIBA TC5832FT
(15) Number of programming cycle on the same page (Partial Page Program)
A page can be divided into up to 10 segments. Each segment can be programmed individually as
shown below.
The first programming Data pattern1
‘ Data
' pattern 2 "
The second programmin
The tenth programming Data pattern10
Result Data pattern] w........................................................ Data pattern 10
pattern 2
Figure 35.
Note: The input data for unprogrammed or previously programmed page segments must be "I''.
(Le. Set all page bytes outside the segment to be programmed to "1".)
(16) Note regarding the It-E Signal
The internal column address counter is incremented synchronously with the RE clock in Read
mode. Therefore, once the device has been set to Read mode by the ''00H", "01H" or "50H" command,
the internal column address counter is incremented by the W clock independent of the timing of the
address input. If the It-E clocks are input before address input and the pointer reaches the last
column address, an internal read operation (array-' register) will occur and the device will be in the
Busy state. (Refer to Figure 33)
Address input
00H/01H
" _ /50H y I F/ y-l '-
Figure 33.
Hence the R-E clocks must be inputted after address input.
1997-08-12 35/38
TOSHIBA TC5832FT
(17) Invalid block (bad block)
The device contains unusable blocks. Therefore, the following issues must be recongnized:
Check if the device has any bad blocks after device installation
into the system. Do not try to access bad blocks. A bad block
- Bad Block does not affect the performance of good blocks becasue it is isolated
from the bit line by the select gate.
The number of valid blocks is as follows:
MIN TYP MAX UNIT
-F Bad Block
Valid (Good) Block Number 502 508 512 Block
Figure 34. Figure 36 shows the bad block test flow.
(18) Failure Phenomena for Program and Erase Operations.
The device may fail during program or erase operation.
The following possible failure modes should be considered when implementing a highly reliable
system.
FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE
Block Erase Failure Status Read after Erase -9 Block Replacement
Page Program Failure Status Read after Prog. -9 Block Replacement
Single Bit* Program Failure (1) Block Verify after Prog. -9 Retry
'I'-9'0' (2) ECC
* : (1) or (2)
0 ECC : Error Correcting code _ Hamming Code etc.
Example : 1 bit correction & 2bit detection.
0 Block Replacement
Program
error occurs When an error happens in Block A, try to
reprogram the data into another (Block B) by
1 Block A
loading from an external buffer. Then, prevent
Buffer
memory
further system accesses to Block A ( by creating
a 'bad block' table or an another appropriate
) Block B scheme.)
Figure 35.
When an error occurs for an erase operation, prevent future accesses to this bad block
(again by creating a table within the system or other appropriate scheme).
1997-08-12 36/38
TOSHIBA TC5832FT
BAD BLOCK TEST FLOW
f .' Checker board pattern
C : Inverted checker board pattern
Blank Check Pass Blank check : 1 Block read (FFH)
Bad Block
BNo.=Bhlo..r1l-
rau-:-crrjri'rEE2ccz=-N-o
Block No = 1
C-PattProc
Read (00H) Fail
Pass BNO. = BNo.+1li-
Block Fail No
Erase Bad
Pass . Block B No. = 512
6 Page Fail
IC-Patt Prog Yes
Read (00H) Fail
Block Fail
B No. = 512
Test End
Figure 36.
1997-08-12 37/38
TOSHIBA TC5832FT
PACKAGE DIMENSIONS
Plastic TSOP
TSOP ll 44/40 - P - 400 - 0.80B
UNITS : mm
44 35 32 23
?HHHHHHHHHH HHHHHHHHHHW d d
10 16i0 1
_i?"i,ll"1'it HHHHHHHHHHJ
1 10 13 22
0.805TYP “0.31-0.05 EIMG
L 18.81 MAX
' 18.41i0.1 _ st,
1.2MAX
1997-08-12 38/38
www.ic-phoenix.com
.
