TC55VL818FF-83 ,524,288-WORD BY 18-BIT SYNCHRONOUS NO-TURNAROUND STATIC RAMFEATURES • Organized as 524,288 words by 18 bits • Fast cycle time of 12 ns minimum (83 MHz maximum ..
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TC55VL818FF-83
524,288-WORD BY 18-BIT SYNCHRONOUS NO-TURNAROUND STATIC RAM
TC55VL818FF-83 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 99 97 95 93 91 89 87 85 83 81 100 98 96 94 92 90 88 86 84 82 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 32 34 36 38 40 42 44 46 48 50 31 33 35 37 39 41 43 45 47 49
/CE
CE2
/CE
/CK
/OE
ADV
A18 NC NC VDDQ VSSQ NC I/O9 I/O8 I/O7 VSSQ VDDQ I/O6 I/O5 VSS VSS VDD ZZ I/O4 I/O3 VDDQ VSSQ I/O2 I/O1 NC NC VSSQ VDDQ NC NC NC
NC NC NC VDDQ VSSQ NC NC I/O10 I/O11 VSSQ VDDQ I/O12 I/O13 VSS VDD VDD VSS I/O14 I/O15 VDDQ VSSQ I/O16 I/O17 I/O18 NC VSSQ VDDQ NC NC NC
MODA4A3A2A1A0NCNC TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 18-BIT SYNCHRONOUS NO-TURNAROUND STATIC RAM
DESCRIPTION The TC55VL818FF is a synchronous static random access memory (SRAM) organized as 524,288 words by 18 bits.
NtRAMTM (no-turnaround SRAM) offers high bandwidth by eliminating dead cycles during the transition from a
read to a write and vice versa. All inputs except Output Enable OE and the Snooze pin ZZ are synchronized with the rising edge of the CLK input. A Read operation is initiated by the ADV Address Advanced Input signal ; the
input from the address pins and all control pins except the OE and ZZ pins are loaded into the internal registers
on the rising edge of CLK in the cycle in which ADV is asserted. The output data is available in the same clock cycle as that in which ADV is asserted. Write operations are internally self-timed and are initiated by the rising edge of
CLK in the cycle in which ADV is asserted. The input from the address pins and all control pins except the OE
and ZZ pins are loaded into the internal registers on the rising edge of CLK in the cycle in which ADV is asserted. Input data is loaded in the cycle following the cycle in which ADV is asserted. Byte Write Enables ( BW1 to BW2)
allow from one to two Byte Write operations to be performed. A 2-bit burst address counter and control logic are
integrated into this SRAM. The TC55VL818FF uses a single power supply (3.3 V) or dual power supplies (3.3 V for core and 2.5 V for output buffer) and is available in a 100-pin low-profile plastic QFP (LQFP).
FEATURES Organized as 524,288 words by 18 bits • Fast cycle time of 12 ns minimum (83 MHz maximum) • Fast access time of 9 ns maximum (from clock edge to data output) • No-turnaround operation with flow-through data output • 2-bit burst address counter (support for interleaved or linear burst sequences) • Synchronous self-timed Write • Byte Write control • Snooze mode pin (ZZ) for power down • LVTTL-compatible interface • Single power supply (3.3 V) or Dual power supplies (3.3 V for core and 2.5 V for output buffer) • Available in 100-pin LQFP package (LQFP100-P-1420-0.65K ; pitch:0.65 mm, height:1.6 mm, weight:0.56 grams (typical))
PIN ASSIGNMENT (TOP VIEW) PIN NAMES Note : NtRAMTM and No-Turnaround Random Access Memory are
trademarks of Samsung Electronics Co., Ltd..
