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TC55V8128BFT-12 |TC55V8128BFT12TOSHIBAN/a1400avaiTOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
TC55V8128BFT-12 |TC55V8128BFT12TOSN/a15avaiTOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
TC55V8128BJ-10 |TC55V8128BJ10TOSHIBAN/a1400avaiTOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS


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TC55V8128BFT-12-TC55V8128BJ-10
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
TOSHIBA TC55V8128BJ/BFT-10,-12,-15
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
131,072-WORD BY 8-BIT CMOS STATIC RAM
DESCRIPTION
The TC55V8128BJ/BFT is a 1,048,576 bits high speed static random access memory organized as
131,072 words by 8 bits using CMOS technology, and operated from a single 3.3V supply. Toshiba's
CMOS technology and advanced circuit form provide high speed feature.
The TC55V8128BJ/BFT has low power feature with device control using chip enable(CE), and has
output enable(UE) for fast memory access. The TC55V8128BJ/BFT is suitable for use in cache
memory where high speed is required, and high speed strage. All inputs and outputs are directly
LVTTL compatible.
The TC55V8128BJ/BFT is packaged in 32-pin plastic SOJ and TSOP(O.8mm pitch) with 400 mil
width for high density surface assembly.
FEATURES
0 Fast access time .' 0 3.3V single power supply : 3.3Vi0.3V
TC55V8128BJ/BFT-10 10ns(MAX) 0 Fully static operation
TC55V8128BJ/BFT-12 12ns(MAX) o All Inputs and Outputs .' LVTTL compatible
Tc55V8128BJ/BFT-15 15ns(MAX) 0 Output buffer control : W
0 Low power dissipation 0 Package :
Cycle Time 10 12 15 20 ns SOJ32-P-400-1.27A(BJ) (Weight:1.22gm Typ)
Operation (MAX) 200 160 140 120 mA TSOPH 32-P-400-0.80C (BFT) (Weight : 0.34gm Typ)
Standby : 2mA(MAX)
PIN CONNECTION PIN NAMES
A3 L 1 32 ZIA4 A3 I: 1° 32 = A4 l/OI l' l/O8 Data Inputs/Outputs
A2 L 2 31 Cl A5 A2 I: 2 31 = A5 CE Chip Enable Input
A1 I: 3 30 = A6 - .
Il/i , 3238 y2 A_0r= 4 A 29 = A_7 ve Write Enable Input
- A - CE I: 5 E 28 = OE OE Output Enable Input
CE E 5 28 J OE
E l/OI l: 6 LLI 27 = I/O8
I/O2 L 7 - 26 Cl l/O? Vor, :2 8 > 25 2 GND GND Ground
VDD E 8 > 25 II GND GND 1: 9 24 = Von
GND E 9 a. 24 JVDD I/O3 l: 10 t 23 = I/O6
l/O3 L 10 O 23 J l/O6 |/O_4 E 11 F- 22 = I/OS
|/04E11 I- 22 :II/05 WE'=12 v 21=IA8
WEQ VZ1ZIA8 A16=13 20=lA9
L Cl A15 = 14 19 = A10
213:}: 333210 A14=15 18=A11
A14E 15 18 :IA11 A13: 16 17 =A12
A13 E 16 17 Cl A12
(SOJ) (TSOP)
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operatin ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and con itions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1998-06-17 1/10
TOSHIBA
BLOCK DIAGRAM
BUFFER
ROJVADDRES S
BUFFER
TC55V81283J/BFT-10,-12,-15
al MEMORY
U.l CELL ARRAY
gs H VDD
BY', 512x256x8
MCI A-o GND
(1,048,576)
SENSE AMP. 2
COLUMN <
DECODER
COLUMN ADDRESS
BUFFER
A5 A7 A9 All
A6 A8 A10 A12
GENERATOR
MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage - 0.5 to 4.6 V
VlN Input Terminal Voltage - 0.5 * to 4.6 V
VI/o Input/Output Terminal Voltage - 0.5 * to VDD + 0.5** V
PD Power Dissipation 0.85 W
Tsolder Soldering Temperature (10s) 260 °C
Tstrg Storage Temperature - 65 to 150 ''C
Topr Operating Temperature - 10 to 85 ''C
: -1.5V with a pulse width of 20% . tRC min (4ns max)
: VDD+1.5V with a pulse width of 20%.tRC min(4ns max)
1998-06-17 2/10
TOSHIBA
TC55V81283J/BFT-10,-12,-15
DC RECOMMENDED OPERATING CONDITIONS (Ta=0° to 70°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDD Power Supply Voltage 3.0 3.3 3.6 V
" Input High Voltage 2.0 - VDD + 0.3** V
" Input Low Voltage - 0.3 * - 0.8 V
: -1.OV with a
** : VDD+1.0V wit
DC and OPERATING CHARACTERISTICS (Ta = ty' to 70°C, VDD = 3.3V i 0.3V)
ulse width of 20%.tRC min(4ns max)
a pulse width of 20% . tRC min (4ns max)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
I Input Leakage Current V =0 t V 1 1 A
IL (Except A8,WE pin) IN-- o DD M
CE=V orm=v oro-E=V
ILO Output Leakage Current IH IL IH -1 - 1 prA
VOUT = 0 to VDD
"(A8,W) Input Leakage Current VIN=0 to VDD -1 - 10 pA
IOH = - 2mA 2.4 - -
VOH Output High Voltage
lou-- -10OA VDD-0.2 - - V
IOL = 2mA - - 0.4
VOL Output Low Voltage
IOL = 100PA - - 0.2
tcycle =10ns - - 200
E: VIL, Iout = 0mA tcycle =12ns - - 160
IDDO Operating Current mA
Other Inputs = VIH /1hl. tcycle =15ns - - 140
tcycle = 20ns - - 120
|DDS1 E: VIH: Other Inputs = V|H/V”_ - - 20
Standby Current E: VDD - 0.2V mA
IDDS 2 - - 2
Other Inputs = VDD - 0.2V or 0.2V
CAPACITANCE (Ta = 25°C, f = 1.0MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
CIN Input Capacitance V|N=GND 6 pF
CI/o Input/Output Capacitance VI/o = GND 8 pF
NOTE : This parameter is periodically sampled and is not 100% tested.
1998-06-17 3/10
TOSHIBA TC55V8128BJ/BFT-10,-12,-15
OPERATING MODE
MODE E E W I/OI to l/O8 POWER
Read L L H Output boo
Write L X L Input boo
Outputs Disable L H H High Impedance IDDO
Standby H X X High Impedance IDDS
X : H or L
1998-06-17 4/10
TOSHIBA
TC55V81283J/BFT-10,-12,-15
AC CHARACTERISTICS (Ta = 0° to 70°C (1)
READ CYCLE
' VDD = 3.3V i 0.3V)
SYMBOL PARAMETER TC55V8128BJ/BFT-1O TC55V8128BJ/BFT-12 TC55V8128BJ/BFT-15 UNIT
MIN MAX MIN MAX MIN MAX
tRc Read Cycle Time 10 - 12 - 15 -
tACC Address Access Time - 1O - 12 - 15
tco E Access Time - 10 - 12 - 15
toe E Access Time - 5 - 6 - 8
tOH Output Data Hold Time from Address Change 3 - 3 - 3 - ns
tCOE Output Enable Time from tTl? 3 - 3 - 3 -
tOEE Output Enable Time from E 1 - 1 - 1 -
tCOD Output Disable Time from E - 6 - 7 - 8
tooo Output Disable Time from m - 6 - 7 - 8
WRITE CYCLE
TC55V8128BJ/BFT-1O TC55V8128BJ/BFT-12 TC55V8128BJ/BFT-15
SYMBOL PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
twc Write Cycle Time 10 - 12 - 15 -
twp Write Pulse Width 7 - 8 - 9 -
tcw Chip Enable to End of Write 8 - 8 - 12 -
taw Address Valid to End of Write 8 - 8 - 11 -
tAs Address Set Up Time 0 - 0 - 0 -
tWR Write Recovery Time 0 - 0 - O - ns
tos Data Set Up Time 6 - 7 - 8 -
tDH Data Hold Time 0 - 0 - 0 -
toew Output Enable Time from m 1 - 1 - 1 -
toow Output Disable Time from WE - 6 - 7 - 8
AC TEST CONDITIONS F_ig_1 3.3V
Input Pulse Level 3.0V/0.0V
Input Pulse Rise and Fall Time 2ns 1200Q
VG 20 = son l/Opin
Input Timing Measurement 1.5V
Reference Level RL = 500 CL = 5pF 8700
Output Timing Measurement 1.5V CLiam; J;
Reference Level bl-- 1.5V (For tcos, toc, tcoo,
Output Load Fig. 1 toioo, tOEW and toDw)
1998-06-17 5/10
TOSHIBA TC55V8128BJ/BFT-10,-12,-15
TIMING WAVEFORMS
READ CYCLE (2)
ADDRESS X X
tcoo (6)
I,, t0E ’
E \g /
tooo (6)
tOEE (6)
Dout VALID DATA OUT
tcos (6)
WRITE CYCLE 1 (5) (W Controlled)
ADDRESS
High Impedance
Din VALID DATA IN
1998-06-17 6/10
TOSHIBA TC55V8128BJ/BFT-10,-12,-15
WRITE CYCLE 2 (5) (CE- Controlled)
ADDRESS X X
tas twp twit
WE _ y'"
tlt- sl, 'RS, i!
t (6) t00w (6)
High Impedance
tos tDH
Din VALID DATA IN
1998-06-17 7/10
TOSHIBA TC55V8128BJ/BFT-10,-12,-15
NOTE :
1. The operating temperature (Ta) is guaranteed with transverse air flow exceeding 400 linear
feet per minute.
2. W is High for Read Cycle.
3. Assuming that tTE" Low transition occurs coincident with or after ITrtTLow transition, Outputs
remain in a high impedance state.
4. Assuming that CE High transition occurs coincident with or prior tTf1ir High transition,
Outputs remain in a high impedance state.
5. Assuming that "0'T't" is High for Write Cycle, Outputs are in a high impedance state during this
period.
6. These parameters are specified as follows and measured by using the load shown in Fig. I.
(A) tCOE, tOEE, tOEW ...... Output Enable Time
(B) tCOD, tODo, tODW ...... Output Disable Time
(A) (B)
_-- ---
. _t 0.2V
High Impedance i0.2V High Impedance
DOUT -, VALID DATA OUT -
0.2V ' 0.2V
UNKNOWN ' UNKNOWN ,
1998-06-17 8/10
TOSHIBA TC55V8128BJ/BFT-10,-12,-15
PACKAGE DIMENSIONS
Plastic SOJ (SOJ32-P-400-1.27A)
Unitinmm
r-Ir-It-Iron.?).,-?,-?.?.-,,-?,""],"""?!"",
a si t
2 a g.
L.JLuulcltuL.ludulL...lLdultul-lulrut-l
I 21-38MAX
20.96i0.12
l omytls
0.8MIN
Weight : 1.229 (Typ)
1998-06-17 9/10
TOSHIBA TC55V8128BJ/BFT-10,-12,-15
PACKAGE DIMENSIONS
Plastic TSOP (TSOPII 32-P-400-0.80C)
Units in mm
JlfiiiflHlfifigfifHlflUi?
10.16L0‘1
“79:02
1HHH ill HHH " " HH "
0.67TYP = ' 0. 32, 007 Elma
"m 13.74MAX - g Q 'g.
fl E a '
H” 13.34i0.1 ' o. N m _/f''
, r T" '- g
( 3 o' '
"v'' " T0~100
Ejid.1 3 I =
fi 0 5:0 1
C5 o.eio.2
Weight: 0.34 g (typ)
1998-06-1 7 10/10

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