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TC55V16366FF-150
524,288-WORD BY 36-BIT SYNCHRONOUS PIPELINED BURST STATIC RAM
TOSHIBA TC55V16366FF-167,-150,-133
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 36-BIT SYNCHRONOUS PIPELINED BURST STATIC RAM
DESCRIPTION
The TC55V16366FF is a 18,874,368-bit synchronous pipelined burst static random access memory (SRAM)
organized as 524,288 words by 36 bits. It is designed for use as a secondary cache to support microprocessor
units equipped with burst functions. A 2-bit burst acjggess counter and control logic is integrated with a 512 K
X 36 static RAM. All inputs except out ut enable OE are synchronized to the rising edge of the CLK input.
Read operations are initiated by the KDJSP address status processor input or KDSU address status controller
input. Subsequent burst addresses can be generated internally under control of the ADV address advance
input. Write operations are internally self-timed and are initiated by the rising edge of CLK. Byte write
enables (BW1 through BW4) allow one- to four-byte write operations to be performed. The TC55V16366FF
uses dual power supplies (3.3 V for core and 3.3 V/2.5 V for output buffer) and is available in a low-profile 100-
pin plastic QFP (LQFP).
FEATURES
0 Organization as 512K words by 36 bits.
0 Fast cycle time of 6ns per minimum (167MHz maximum)
0 Fast access time of 3.6ns maximum(from clock edge to data output)
0 Pipelined burst operation
0 2-bit burst address counter(inter1eaved or linear burst sequences)
0 Synchronous self-tiid write (global write or byte write)
0 Stop-clock mode for power down
0 Snooze mode pin(ZZ) for power down
0 2cyc1e Enable, 1 cycle Disable
0 LVTTL compatible interface
0 Dual power supply (3.3V for core and 3.3 V/2.5V for output buffer)
0 Available in 100-pin LQFP package(LaFP100-P-1420-0.65B:0.65mm pitch, 1.6mm height, typically 0.91
grams)
PIN ASSIGNMENT (TOP VIEW) PIN NAMES
s;tltnlCuls-lCuCyin m > A0toA18 Address Inputs
fizltflglllélbggéilzfiafifi l/OI to |/O32 Data Inputs/Outputs
9 ' ' ' 3929190898887868584833281 IIO P1 to l/O P4 Parity Inputs/Outputs
'_//fo,o,'11',3Si1,t $8 il§i§ _LLK flofeu.t
VDDQ VDDQ CE, CE2, CE2 Chip Enable
?;(5351 [gi ADSP Address Status Processor Input
”8%? W, K83 ADSC Address Status Controller Input
$9526 9 l/O11 ADV Address Advance Input
‘42)ng [8?] Gi/it Global Write Enable Input
l/O24 --- IIO9 - .
V3.6 " )(scs BWE Byte Write Enable Input
V'gg \Z/ZDD BW1 to BW4 Byte Write Enable Inputs
58%: :2: l/k)') OE Output Enable
vslgg 335%) MODE Mode Select Input
”858 ... 23 I8? 22 Snooze Input
(ii2i' II gg (ill, NU Not Usable Input
V393? (ii: % ygzoo Vor, Power Supply for Core
.5833; ... $3 32 34 36 38 40 42 44 46 48 503% I181” Vss Ground for Core
3Ar%?Ar3Gi?A1,r%9A7,rtl, Vooo Power Supply for Output Buffer
LutrtstrnrNs-CC_tCyt0tsti-rNtraxttnto VSSQ Ground for Output Buffer
Cy<<<<<
fl >><<<<<<<<< NC No Connection
000707EBA2
O TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction
or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizin TOSHIBA
products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a mal unction or
failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent
TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor
Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
0 The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office
equipment, measurina equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for
usage in equipment t at requires extraordinarily high quality and/or reliability or a malfunction or failure of which m.ay cause loss of human life or
bodily injury CUnintended Usage"). Unintended Usage include atomic ener y control instruments, airplane or spaceship instruments, transportation
instruments, traffic signal instruments, combustion control instruments, me ical instruments, all types of safety devices, etc.. Unintended Usage of
TOSHIBA products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade laws.
0 The information contained herein is presented only as a guide for the ap lications of our products. No responsibility is assumed by TOSHIBA
CORPORATION for any infringements of intellectual property or other rights 0 the third parties which may result from its use. No license is granted
b implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
2002-09-04 1/19
TOSHIBA TC55V16366FF-167,-150,-133
BLOCK DIAGRAM
19 19 17 19
Ami?) D Address Q
Register
A1 to A0
ADV Binary Q1 '
Counter and A1
CLK CLR Logic Q0 A0,
BW1 Byte1 Q Byte1
D Write Register Write Driver
.Bytt2 . Q .Bytt2. Memory
D Write Register Write Driver Cell Array
BW3 Byte3 Q Byte3 512Kx36
D Write Register Write Driver (18,874,368)
BW4 Byte4 Q Byte4
D Write Register Write Driver
ttti/ Enable
D Register
Q Q Q D D D D
E Delay Byte 1 Byte 2 Byte 3 Byte 4 Output
Register Input Input Input Input Register
Enable Delay D Q Register Register Register Register Q Q Q Q
CE2 D Register Q D D D D
Output
E Buffer
I/OI to I/O8,
l/O P1
l/O9 to I/O16,
IIO P2
I/OIT to |/024,
l/O25 to l/O32,
l/O P4
2002-09-04 2/19
TOSHIBA
TC55V16366FF-167,-150,-133
PIN DESCRIPTIONS
PIN NUMBER
SYMBOL
DESCRIPTION
37, 36, 35, M, 33, 32,
100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50, 43, 42
A0to A18
(synchronous)
Synchronous Address Inputs
Registered on the rising edge of CLK. Address
inputs must meet the specified setup and hold
times with respect to the CLK rising edge when
the chip is enabled.
93, 94, 95, 96
BW1, BW2, BW3, BW4
(synchronous)
Synchronous Byte Write Enables
These active low inputs control byte write
operations when BWE is low. W controls
POI through l/O8 and |/OP1. m controls
l/O9 through |/O16 and IIO P2. BTW controls
l/O17 through l/O24 and " P3. W controls
I/O25 through l/O32 and IIO P4.
For byte write operations, when any of these
four inputs go Low, all outputs go to high
impedance.
(synchronous)
Synchronous Byte Write Enable
This active low input controls byte write
operations.
(synchronous)
Synchronous Global Write
This active low input controls 32-bit write
operations independent of the BWE and 3W to
W inputs.
Reference Clock
All synchronous input signals are registered on
the rising edge of CLK. Synchronous signal
timings are measured from the rising edge of
CLK. Synchronous input signals must meet the
specified setup and hold times with respect to
the rising edge of CLK.
(synchronous)
Synchronous Burst Advance
This active low signal controls the internal burst
address counter after an external address has
been loaded. When Low, the internal burst
address is advanced. When High, the internal
burst address is not advanced. If a write
operation initiated by ADSP is desired, this
signal must be High to write the loaded address
on the rising edge of the first clock after the
assertion of W.
(synchronous)
Synchronous Address Status Processor
This active low signal controls the burst start by
registering a new external address. The write
enables(W,m, BW1 to W) are ignored at
the assertion of WSP and a read operation is
initiated. Subsequent operations are dependent
on the write enables at the rising edge of the
first clock after the assertion of WSP. This
signal is ignored if E is High.
2002-09-04 3/19
TOSHIBA
TC55V16366FF-167,-150,-133
PIN NUMBER
SYMBOL
DESCRIPTION
(synchronous)
Synchronous Address Status Controller
This active low signal initiates a burst read or
write, depending on the write enables(tiN,
W,W1 to W4), by registering a new
external address.
(synchronous)
Synchronous Chip Enable
This active low signal controls the chip status
(enable or disable) and the internal use of
WSP. It is sampled only when a new external
address is loaded.
(synchronous)
Synchronous Chip Enable
This active low signal controls the chip status
(enable or disable). It is sampled only when a
new external address is loaded. It can be used
for memory expansion.
(synchronous)
Synchronous Chip Enable
This active high signal controls the chip status
(enable or disable). It is sampled only when a
new external address is loaded. It can be used
for memory expansion.
(asynchronous)
Asynchronous Output Enable
This active low signal controls all 32-bit IIO
output buffers. It must be high while write
data is being driven prior to the assertion of
the byte write enables(GW, BWE, BW1 to BW4)
following a read operation.
52, 53, 56, 57, 58, 59,
62, 63, 68, 69, 72, 73,
74, 75, 78, 79, 2, 3, 6,
7, 8, 9, 12, 13, 18, 19,
22, 23, 24, 25, 28, 29
l/OI to |/O32
lnput/ Output
(synchronous)
Synchronous Data Inputs/Outputs
Byte1 is l/Ol to l/O8, Byte2 is I/O9 to I/O16,
Byte3 is |/017 to l/OM, Byte4 is |/025 to |/O32.
51,80,1,30
l/O P1 to IIO P4
lnput/ Output
(synchronous)
Synchronous Parity lnputs/Outputs
IIO P1 is a parity bit for Byte1 as l/O1 to |/O8.
l/O P2 is a parity bit for Byte2 as I/O9 to l/O16.
IIO P3 is a parity bit for Byte3 as |/017 to l/O24.
l/O P4 is a parity bit for Byte4 as l/025 to l/O32.
(asynchronous)
Mode Select
This signal selects the burst sequence. If High or
not connected, the burst sequence defaults to
Interleaved Burst. If Low, the burst sequence is
Linear Burst.
This input is pulled up internally. Do not alter
the input state while the device is operating.
2002-09-04 4/19
TOSHIBA
TC55V16366FF-167,-150,-133
PIN NUMBER
SYMBOL
DESCRIPTION
(asynchronous)
Snooze
This active high signal is used to place the
device into sleep mode (low power standby
mode). When Low or not connected, the
device remains in the active state. When high,
the device goes into a sleep state, and memory
data is retained. After this signal is deasserted,
the device wakes up when a read or write
operation is initiated by WSP or m. If 22
(sleep) mode will not be used, connect this
input to Vss.
(asynchronous)
Not Usable
This signal is used only by the manufacturer.
This signal must be low or not connected. This
input is internally pulled down.
14,16, 39, 66
No Connection
These inputs are not internally connected.
15,41, 65,91
Supply
Power Supply
17, 40, 67, 90
Ground
Ground
4,11, 20, 27, 54, 61,
70, 77
Supply
Output Buffer Power Supply
5,10, 21, 26,55, 60,
Ground
Output Buffer Ground
2002-09-04 5/19
TOSHIBA TC55V16366FF-167,-150,-133
OPERATING MODE
(1) Synchronous Input Truth Table
- - - - - 4 1 ADDRESS 5 2
OPERATION CLK CE CE2 CE2 ADSP ADSC ADV WRITE ZZ USED HO, HO P CURRENT
Begin Burst L-YH L L H L x x x L External
Read Address Dout (n) IDDO1
L -Y H L L H H L x H L
Continue Burst L-y H x x x H H L H L Next Burst
Read 6 Address D0ut(n) |DDO1
L -9 H H x x L H L H L
Suspend Burst L -> H x x x H H H H L Current
Read 6 Burst Dout (n) IDDOZ
L -Y H H x x L H H H L Address
. External
Begin Burst L -9 H L L H H L x L L Address
L -9 H x x x H H H L L Current Din (p) N/A
6 Burst
L -+ H H x x L H H L L Address
Coritinue Burst L-y H x x x H H L L L Next Burst .
Write 6 Address Din (p) N/A
L -9 H H X x L H L L L
Suspend Burst L -9 H x x x H H H L L Current
Write 6 Burst Din (p) N/A
L -r H H x x L H H L L Address
Deselected L -Y H H x x x L x x L
L - H L H x L x x x L
L-YH L x L L x x x L None Hi -Z(p) loose
L -y H L H x H L x x L
L -Y H L x L H L x x L
Snooze L -9 H x x x x x x x H None Hi - z (p) |DD53
Note: 1. ZZ input, although asynchronous, is included in this table.
2. Consumption current does not include output buffer current.
3. H means logical High and L means logical Low. M means Don't Care.
4. 1rrltt?CE = L means any one or more of the byte write enable inputs (BWT, BW2, BW3,
Bird) and BWE are Low, or that W is Low. WRITE = H means W and BW-E are
High, or CTGt is High and WtE is Low and all byte write enable inputs are High.
5. (n) and (p) indicate the cycles affected by the synchronous control inputs. (n) is the
next cycle, (p) is the present cycle.
6. When CE = H, A-DSP is disabled (ADSP = X). ADSP = L to avoid redundancy with
the previous truth table entry when CE = H and ADSP = H.
2002-09-04 6/19
TOSHIBA TC55V16366FF-167,-150,-133
(2) Partial Truth Table for Write Enables (Synchronous Input)
OPERATION CLK W BWE BW1 BW2 BW3 BW4 "ko/f"' "09Vt8 3:315: V01I7IBOPIQOZ4. I/Oziéoplzmz,
L -9 H H H x x x x Dout (n) Dout (n) Dout (n) Dout (n)
Read L -9 H H L H H H H Dout (n) Dout (n) Dout (n) Dout (n)
L x x x x x Din (p) Din (p) Din (p) Din (p)
H L L L L L Din (p) Din (p) Din (p) Din (p)
L H H H Din(p) Hi-Z(p) Hi-Z(p) Hi-Z(p)
H L H H Hi-Z(p) Din(p) Hi-Z(p) Hi-Z(p)
Write L -9 H
H L H H L H Hi-Z(p) Hi-Z(p) Din(p) Hi-Z(p)
H H H L Hi-Z(p) Hi-Z(p) Hi-Z(p) Din(p)
Th_eother 11 combinations of W toB_W are also effective.
w controls l/OI to I/08 and IIO P1. BW2_controls I/09 to |/O16and l/O P2.
BW3 controls I/O17to 1/024 and " P3. BW4 controls 1/025 to l/O32 and IIO P4.
Note .' 1. (n) and (p) indicate the cycles affected by the synchronous control inputs. (n) is the
next cycle, (p) is the present cycle.
(3) Asynchronous Truth Table
OPERATION a ZZ 1/f',,1,tS/e,3,2,',
Read L L Dout
H L Hi - Z
Write x L Din, Hi - Z
Deselected x L Hi - Z
Snooze x H Hi - Z
(4) Interleaved Burst Sequence (MODE Input=NC or VDD)
Bit Order .' A18 A17 ............. A3 A2 A1 A0
The lower 2 bits are internally generated from the external address.
1st Address
2nd Add ress
3rd Address
4th Ad d ress
(External) (Internal) (Internal) (Internal)
XX ...... XXOO XX ...... XX01 XX ...... XX10 XX ...... XX1 1
XX ...... XX01 XX _..... XXOO XX ...... XX1 1 XX ...... XX10
XX ...... XX10 XX ...... XX1 1 XX ...... XXOO XX ...... XXO1
XX ...... XX1 1 XX ...... XX10 XX ...... XXO1 XX ...... XXOO
The burst address wraps around to its initial state.
2002-09-04 7/19
TOSHIBA TC55V16366FF-167,-150,-133
(5) Linear Burst Sequence (MODE Input=Vss)
Bit Order 2 A18 A17 ............. A3 A2 A1 A0
The lower 2 bits are internally generated from the external address.
1st Address 2nd Address 3rd Address 4th Address
(External) (Internal) (Internal) (Internal)
xx ...... xxoo xx ...... XX01 xx ...... XX1 0 XX ...... XX1 1
XX ...... XX01 XX ...... XX10 XX ...... XX1 1 XX ...... XXOO
xx ...... XX10 xx ...... XX1 1 xx ...... xxoo XX ...... XX01
xx ...... XX1 1 xx ...... xxoo XX ...... XX01 XX ...... XX10
The burst address wraps around to its initial state.
(6) Stop-Clock Mode for Power Down
The TC55V16366FF achieves low power standby mode by stopping the clock input.
It can retains all state and data values even though the clock is not running.
To achieve the lowest possible power operation, the following signal states are required.
i) Clock is Low
ii) Control signals are inactive (for example, AD-SP is High)
For the lowest possible power consumption during stop-clock mode, the address inputs should be
driven to MOS level (VIH i VDD - 0.2V or VII, s 0.2 V), and the data inputs should be driven
to MOS low level (VIL s 0.2V).
. Clock restart sequence
The device can be waked up by the first rising edge of the clock signal after having been
in power down mode.
CLK IH IN I” IN IF
ADSP N /
ADV é N /
Data (out) -i-i-4)( Q(A1) ' @(Qw
1)()( 0142)
ADSP CLK Stop Wake up KDSP
Initiates ( Continue ) Initiates )
Burst Read Burst Read Burst Read
i) Stop-Clock Timing for Read Operation
2002-09-04 8/19
TOSHIBA TC55V16366FF-167,-150,-133
Data (in)
Data (out)
CLK Stop Wake up ADSC
Initiates ( Continue ( Initiates
Burst Write Burst Writ Burst Writ
ii) Stop-Clock Timing for Write Operation
CLK 'el V-, P-h P-, 'r-"
I I I I I
I I I I I
I I I I I
l l , l f-h I r-h-
ADSC I t t I t
I 1ci-/ I I I
I I I I I
l I I I l
CE1 l / l l N i l
l E i l l
l l 1 l l
Data (in) -i-i-( " or VIL:Fixed l Y-i-
i i i i i
I I Hi h-Z I I I
Data (out) Data l )(i)( EE) lg ( i E
l : i i (
Continue CLK Stop Wake up
Burst Read (Deselected) (Deselected)
iii) Stop-Clock Timing for Deselect Operation
2002-09-04 9/19
TOSHIBA
TC55V16366FF-167,-150,-133
MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage -0.5 to 4.6 V
VDDQ Output Buffer Power Supply Voltage - 0.5 to VDD V
" Input Terminal Voltage - 0.5 * to 4.6 V
VI/o Input/Output Terminal Voltage -0.5* to VDDQ+0.5** V
PD Power Dissipation 1.6 W
Tsolder Soldering Temperature (10 s) 260 ''C
Tstrg Storage Temperature -65 to 150 ''C
Top, Operating Temperature - 10 to 85 ''C
* .' -1.5V with a pulse width of 20% . tKC min(3ns max)
** : Vmoa+ 1.5V with a pulse width of 20% . tKC min (3ns max)
DC RECOMMENDED OPERATING CONDITIONS (Ta=0~70°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDD Power Supply Voltage 3.135 3.3 3.465
VDDQ Output Buffer Power Supply Voltage 2.375 - 3.465
Input High Voltage for Address and . 1.7 - VDD+0-3
VIH Control pins(except IIO and Mode pin) V
Input High Voltage for IIO pins 1.7 - Vooq+0.3**
V.H1 Input High Voltage for MODE pin Vorr-0.3 VDD VDD+0.3
" Input Low Voltage -0.3* - 0.7
V|L1 Input Low Voltage for MODE and NU pins -th3 0.0 0.3
Note: NU pin must be low or not connected.
* : -1.0V with a pulse width of 20%"KC min(3ns max)
** .' VDDQ+ 1.0V with a pulse width of 20% . tKC min(3ns max)
You must not apply a voltage of more than 0.8V to the NU.
2002-09-04 10/19
TOSHIBA TC55V16366FF-167,-150,-133
DC CHARACTERISTICS(Ta = 0° to 70°C, VDD = 3.3V , 5%, VDDQ = 2.375v to 2.9V or 3.3V i 5%)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
Input Leakage Cu rrent
. v = t v - - tl A
(Except MODE,ZZ, NU pins) IN 0 o DD "
Device Deselected or
ILO Output Leakage Current Output Deselected, - - i1 ,uA
VOUT=0 to VDD
V =V V - . V -l - 1
MODE pin IN DD to DD 0 3
" =0 to 0.3V - 100 - 1
V =V t 2. V - 1 - 1
ll Input Current . IN DD 0 0 00 #A
22 pm le=o to 0.8V -l - 20
" = 0 to 0.3V -1 - 1
NU pin lhN--0 to 0.3V -1 - 1
VDDQ IOH = - 8mA 2.4 - -
=3.3Vt.5% 10H: -100prA VDDO-th2 - -
V Hi h V I
OH Output lg otage VDDQ lou-- -1mA 2.0 - -
= 2.375 to 2.9V IOH = - 100,11A VDDQ - 0.2 - - V
VDDQ IOL = 8mA - - 0.4
V O L V I =3.3Vi5% IOL-- 100/1A - - 0.2
OL utput ow otage VDDQ IOL=1mA - - 0.4
= 2.375 to 2.9V lor. = 100,1A - - th2
Device Selected, |out=0mA 167MHz - - 440
|DDO1 Operating Current All inputs--Vm/1hL 150MHz - - 425 mA
CLK 5 th min 133MHz - - 400
. Device Selected, |out=0mA 167MHz - - 400
IDDO2 2trting Current ADSC, ADSP, ADV 2 vIH 150MHz - - 385 mA
( e) All inputs=NhH/Vl, CLK 2 th min 133MHz - - 360
Device Deselected, 167MHz - - 110
IDDS1 ?:?:de CFrrint All inputs s le/vlL 150MHz - - 105 mA
runmn .
g CLK 2 th mm 133MHz - - 100
Device Deselected,
IDDSZ Standby Current All inputs E VDD- 0.2V or 0.2V, - - 10 mA
CLK frequency-- 0Hz
hil . , ZZ=VDo-th2V,
IDDS3 Snooze Current w I e 22 Pin IS All inputs=Nhri/NhL - - 20 mA
High CLK 2 th min
ZZ E 0.2V, Chip Deselected
|DD54 2:002; C35”: during CLK s 0.2V, ADSP, ADSC=Vorr- 0.2V - - 20 mA
op- oc o e All inputs: 0.2V
CAPACITANCE (Ta = 25°C, f=1.0MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
C Input Capacitance Vm: = GND 7 pF
Input Capacitance for MODE, ZZ, NU pin " =GND 10 pF
CI/o Input/Output Capacitance VI/o = GND 9 pF
Note: This parameter is periodically sampled and is not 100% tested.
2002-09-04 11/19
TOSHIBA
TC55V16366FF-167,-150,-133
AC CHARACTERISTICS(Ta = 0° to 70°C, VDD = 3.3V , 5%, VDDQ = 2.375v to 2.9V or 3.3V i 5%)
SYMBOL PARAMETER TC55V16366FF-167 TC55V16366FF-150 TC55V16366FF-133 UNIT
MIN MAX MIN MAX MIN MAX
th CLK Cycle Time 6 6.6 - 7.5 -
tKH CLK High Pulse Width 2.2 2.5 - 3 -
tKL CLK Low Pulse Width 2.2 2.5 - 3 -
tKQv Access Time from CLK - - 3.8 - 4.2
tKQX Output Hold Time from CLK 1.5 1.5 - 1.5 -
tKQLZ Output Enable Time from CLK 1.5 1.5 - 1.5 -
tKQHZ Output Disable Time from CLK 1.5 1.5 3.8 1.5 4.2
tGQv Access Time from E - - 3.8 - 4.2
tGQLz Output Enable Time from E 0 0 - O -
tGQHZ Output Disable Time from E 1.5 1.5 4 1.5 4.5
tas Address Input Setup Time from CLK 1.5 1.5 - 1.5 -
tAH Address Input Hold Time from CLK 0.5 0.5 - 0.5 -
tADss W, AD-SC Input Setup Time from CLK 1.5 1.5 - 1.5 - ns
tADSH W, AD-SC Input Hold Time from CLK 0.5 0.5 - 0.5 -
ttws m Input Setup Time from CLK 1.5 1.5 - 1.5 -
tAVH m Input Hold Time from CLK 0.5 0.5 - 0.5 -
tws 6W, BWE,WtoW Input SetupTime from CLK 1.5 1.5 - 1.5 -
tWH 6W, BWE, Wtom Input Hold Time from CLK 0.5 0.5 - 0.5 -
tCES E, m, CE2 Input Setup Time from CLK 1.5 1.5 - 1.5 -
tCEH E, W, CE2 Input Hold Time from CLK 0.5 0.5 - 0.5 -
th Data Setup Time from CLK 1.5 1.5 - 1.5 -
tDH Data Hold Time from CLK 0.5 0.5 - 0.5 -
tzs ZZ Standby Time 5 5 - 5 -
tZR 22 Recovery Time 5 5 - 5 -
tsz Output Disable Time from ZZ - - 2 - 2 cycle
AC TEST CONDITIONS Lig._1
VDDQ = 2.5V VDDQ = 3.0V 2.5V 3.3V
Input Pulse Level 2.5V/0.0V 3.0V/0.0V
Input Pulse Rise and Fall Time 1.8ns 2.0ns " 20:509 l/Opin
1''de,T,ici?2,t'asurement 1.25V 1.5V RL = 509 CL = SPF 21m
Output Timing Measurement CENT]; ;
Reference Level 1.25V 1.5V VL=1.25V/1.5V
(For te:QLz, tKQHZ.
Output Load Fig. 1 Fig. 1 tGQLZ, and tGQHZ)
2002-09-04 12/19
TOSHIBA TC55V16366FF-167,-150,-133
TIMING DIAGRAMS
READ CYCLE
I Single Read I Burst Read ,Deselected
_ - th _
.:4',-'-t:'
i... tADSS 4+1" tADSH 1tKH tet... taoss 1 w,sHi..Ao-ss, is blocked Jj..' Ce high/i..:'.. 1 1
ADSP _..:"'''':".::.)''"'.:..:.?,'?,',,:":.".:. "l)'iid'itl/yi/ t' 1'..i._.eir._.)esa..-.i./v_i._".
i..' tADss01tAL>5H i tADss101’EADSH i..'
ADSC _:.i'_'.trot.:r:. 2; WWWWY222
ADv2/ 2 w,,),''..; _._._i,',Ct'l,/,s",r..:i'_:.'i' 1222221222 (_"'- 2/ s..)
i.ADV suspends bu r511.
A‘8XZ22222A222 x.i? "j'"? /i? wir- 2 2/ x,s.",":
. tws1001’EWH 'i'
Gw//222WWWWWWWW2V2
BI/VE // A.:.'?"'-'',..-':':";;')'.,.-:.'':'-.'',.'::. ‘22 ey'::.. xgr'i., 'ey..:.'' '.',:ixari',', 22/22
i.' tces 010tCEH 1
%/////////////2/22////////
i' tCES , '1‘ r tCEH 1 CT misks AD-SP.:."
"'izv//:..'rttj'.i.'..,a,C //'.,rca.i'.'' 2 /yd,'.s:/ /s.'rs? 2F 'ar.. ‘2/2/ "j/i/trv/ si.",',
'.: tCES tCEH :..' W, CE2, CE2 state is sampled only when a new addres'.s is loade/q1/. tCES 14+14+1tCEH i'
CE2 // /2’/ 21/ // si? // // /.// 'tr"f..:. 'F"e.t' /-
1 tCES "1v tCEH 1 i..' i," Dese(ected With t::ij2 or iii",., tCES "1w tCEH 1
222222 As.'.""? str" sir" As'.;'" '/i/.Ci'"(p''''t.
Din i'
[um to I/032,; ]
" P1 to " F14 ttso-Zi, ' d 4 i)'" i,' i,' i,' i..' i..' 13511111111151 210121111
[v/eil,',?,?:":,',',:."'.:.'.'.'.:'"-'.)..:-?',' '. S-ii-woot)))"..:))' :,.' Q3(A2) . WWW“
V0 P1tol/OR.4 : 54m? 1tKQX E i i i ltvt, 5
'ff72f) Don't care
1 Indeterminate
1. Q1(A2) represents output data from 1st burst address starting from address A2. Q2(A2)
represents output data from 2nd burst address starting from address A2.
2. ZZ is Low.
2002-09-04 13/19
TOSHIBA TC55V16366FF-167,-150,-133
WRITE CYCLE
Single Write I Burst Write .Deselected
-..ct.',-"t il E
CLK . . E E . .
i.... tADss E tADSH EtKH EE'E i,' taoss 4+E4+ tADSH. 'ipuy-ss, is ti)ocked bYE CE h'ghE . E
ADSP 5% /riRa)x1r//l'1, %Ԥ3//2/ "sit _yt..z.__''Ehilh/':_:':.:_xgr.'...r'_.zer_.i.
'i' tADSS4+E4+|1AE>SH 'i' i,' taoss |4+E4+|tADSH i.," ' .
ADSC EW "'f" "f // '.:._eiti.i. WE eirii..... 'tsir/si.'.
"iAi:-ou mujt be high_ Efor Aiisp Ewrite. i.' tAvs "Ev tAVH i.' 7E" tAVH i'
ADV/E/ 2///2"///2“/2%//2‘E%%5E2V2// // 2”
.ADV suspends bu rs;
A‘8EZ2/4/22A222 2/ /si'? /_// ////XA3// /
E tws|4+E4+|tWH 'i' i' tws E i
GW// //"2.f'"f...i'le'v:r(.:R.iil.i-i..i-ilj
i .11 5 GW pEerforms wErite independent ofE BV/E andE BVI to B\_N4.
: tws4 w: tWH :
swe2/ 2225/2222 2/ 22 1//.../trr1,.r/'/t, wi:,.";
E22 24222 xr-,): /s,ei.,.r/ s'.? 2/2xE X222 xr'c-
Any:.' iof CE, CEz',
E tCEs tt' tCEH E E CE masks ADSEP. tCEs 54+ tCEH i..' CE2 Edeselects. E
E1//:E /.,._la,'i:.._jc_,"'zs,,.is:/CE/.l.'1atssA/Ds',.::. ‘EEE .
tces tCEH i.' E tWi, CEEZ, CE2 staEte is samlyed only when a neEw address':, is loadecEE. ..i
CE2 1E/ 11/ XA:::. /" 1/ "':,'" 1/ "f" 11/ AV A" .i.V'" w/ef'
i' tCEsE E4+EtCEH i' i:" '...' i" tCES‘ENE'EECEH ..:"
ce22 "::i1t;''1o..ir/i.r'vro."'.'.sv._,..'r /f(.///(. 2222222
@22222222/
I/O1DEIE/EO32E ED513101? ')'ir)rsoi)2eiir2sL, 02(E/u) D3042) vie:.'."))'"...."..:')':'.':..:..-'-':.-:'.":.
be PE‘Elotol/O $4] F4 EEGQHZ i." -:..' i.." i... i.." a
l/01tol/O32/ .
|:|/OP1to|/OF‘E4 E i
b/7,7fg'j' Don't care
Indeterminate
1. D1(A2) represents input data for 1st burst address starting from address A2. D2(A2)
represents input data for 2nd burst address starting from address A2.
2. ZZ is Low.
2002-09-04 14/19
TOSHIBA TC55V16366FF-167,-150,-133
WRITE CYCLE (BYTE WRITE TIMING)
Byte Write I Burst Read
. tKC .
5 tmoss tADSH 5
. 5 i i.' i.iAo-w''"i is t5|ocked by5CE high...: i
ADSP5 ":i7t'i;._.ressrirevi."..... 1f/riv'///./, //“///5
. 5 {ADSS 54-HtADSH 5
/ACi':.._',...i:'eil-,,,,/ii'..,,,i_ 15/5/‘(555‘55/5WWW
ADV 5W7/57 // //DVJUSt‘5ag/f/m s/iid"),'.',..'.''.':.:')"'?':,; /5/552‘;555;5AVH 5% gsari..''
A18;://5AS 5AH//5)(§2)(/5//5)(A5355//555)H(§4)///5 si'" "s.iev" ",j,.S
cw V55 "sit" (rtvisiti_.', 555/555/W5WW
BWE 5/5555 5/ /s'.:".ir/i:'.'i/-'artyHs,i_,rca'.ii.i' _.._ij,'rr.:'.'rtv"._.i"itivi"i/.jer.:..i. W5
BW15W/5/ "i.)" w,,:,'.:.")?,)"...'..:-"))"",,.'.":;?")''..":".." .._"C'sivs'"//o,.'zv" /5/ w)."..'" "i/ 5
W55: 'i.....,? "s) w,'':.;? "/'Ci-'ii"i) ",''izt,vishr'i.,.. tWH /r'''..r."v" "iv" /j'.e? /,i.r" "i),
C-E masks ADS5P. tcgswggltcm i'
-t-t-,,jrs'.'. -i.i',.:rsysi_rt.cist'..i'1trrs':'_rri....'i. vr1j///.21r/ea,at'ii,r,, 5:2 tit:' Af
CE, CE2, CE2 state IS 5am fe onl :
Deseleded with CEZ or CE2 na: new address is 53-8de y :"
«2555555555555555555555/55/ "f'" 5/ w)...'"
: t ALZAK t :" .
i CES CEH 5 tCES tttt tCEH E
cE2/i:resistiutcss."..":r" ''''iiir'//j(./i1:.e/''/(./i'rry)/j/., s,i,w,s::,.rs:,."o,
.i. tCEs . tCEH i 5 i." i' i'
Cor _..: i" 'ri'" wi"'.? // si? /5/ ",',..'a
Dime 'i," 'i.." i 'i' 5°:r-5-1ZD” 'i' .
3:2(‘f/om) i," 'i, i:.., i,." i," t ':...' t i:..,
Din9 to i.' ":.lKt-2H, i.' i.' i.' i.' tsle:Xt DH i.'
'lii'rgop2toii:op4) ':..tox i," i," i," i," 28'1(-'3)2iie i,"
Dout1to . 5 i.' i' i' i' i' i'
Dout8 5
Dout(|/OP1)5
Dout9 to
Dout32
Dout(|/0 P2to5IIO P4) 5 :.."
"f"ggy2' Don't care
i2iggli Indeterminate
1. ZZ is Low.
2002-09-04 15/19
TOSHIBA TC55V16366FF-167,-150,-133
READ / WRITE CYCLE
. . . Output
Single Read I Single Write I Burst Read l Disabled
.i.4_."-/"hi.
':.' tADss . tADSH i1TH tKL:. . tADss 1>E¢>tADSH :..' ':,AD-ss, is blOCked by c7 high;
7ir5!ri5 W flmfl/‘5‘%//W% 'f,.i,/Ehl''li:es/,.:.-...er,"'_,":.
5 i' uDssrr'.:euDsH 'i tADss|4+4+|tADsH ':.'
ADSC KV/g 4V/4V/7/WWWWW
:.AiV must be high] :for AD-SP :write. tAVS It.' tAVH i.' .
ADV/X/ // // "s:'rtAvj,'i,.jt't'1::'rxa..::ius::.::'. // // /’
"e, //%%/%AZW%%A3W// Ai'':." // // /:'r..r..y? "a:''';
i tws|4+54+|’EWH 5
GW/ //V//W//WWWWW
tws "i.," tWH i..' tws 4+tWH i..
BWE/i/ 'l'..."'"",'.,:.:'"''"'':.','.'" V/fl‘WWWWW
ssv-viv-e:i/si,.s? / /,w.:'..s? //E+WH/: "sit" /ss:.' // w/so:.,' wvi.t" si,.,'
i: tCES tCEH i.' i CE masks ADSP. tCES "ht tCEH i.'
t:ri/i.rr2li; ///>,\///\//// m//_/ /,,i'.r/ /'
i.' tCES 4+ tCEH i.' . CE; Cij2, CE are sampled only whin a new address is:' 'poaded. i.'
CE2 // /_/%§ trl/(icylr., /// // // tr WI.'..,;'" //
'.: tCES 'ri/r' tCEH '.:
CEZ/ W/flW/flW/fl/fl//
E i.' i' i.' t i.' i.' i.' i.' h i.' :..' i,' i.' js-'':,'.."
i' i..' i," i.' tos gHtDH i.' .' i : .' .' 5
Din f f f f DiI/o1tol/O32,i. g g t; '- n g g i ..' i gt
" P1 to " Pj4 . A GQHZ, 2 s 5 GQHI A
Dout :.." "i.., 'i,, ‘Q1(A:\1) 'i" _..'' _::..., A3))@(02¢A3)@(Q3 €¢A3))@(Q4 Aflfi;
[pt to I/O32,i ]
m Don't care
I/opltovoh4 i KQX i' i' tat..
1. When a write operation follows a rea_doper_atior1, 'tVg must be driven high prior to the
assertion of the byte write enables(GW, BWE, BWI to BW4) and before input data is
applied to avoid data bus contention.
2. ZZ is Low.
2002-09-04 16/19
TOSHIBA TC55V16366FF-167,-150,-133
SNOOZE CYCLE
Single Read I Snooze I Read
i... tADssH tADSH 'ttc, 'tTL':.. 5 hh i.' tADss VrEVrtADSH
ADSP _'._:itisssstt.i_.:.'" (.:%er%r.:..Njr..':.. lngWWW/W
i; 'i' tADSS (+10 '; . i..' '.; . . :'; tADSH§
WC 2 ; . ' 'N: air:..' W m/i.. tirrsi.s? si..,
ADVWW/WWWWWWWWWWWWWW
A1813 '/ii.rtir'i(1-iiiecl.i: xi.'" WWWWW WW s) WW WWWXAZW/
'i' tws [901w :..'
Gvvvii.y" WWWWW/WW s/ry W "sito" wi',/ujics'..i?v':i,
'.: tws4 N rigr r tWH '.:
BweW WWgsW'WWWWW W W W "//iiia//j///,../i1,
'''''''1''h''''(-'ii-,t/-t WW W WW W A:';:?))'),''',.' WW W WW c.',_cii'vt.i.t" W
i..' tCEsH'I tCEH i.'
cEWWg W W /z.',"'.ritis'sz.,'..i? "ir/ W si'? xt.iaj,ihsia/_..v'-ss.."'_
i.' tCEs A io . tCEH i.'
CEZW/Wx'f’ W W /.'.'.//iiirs.'..'.r WW s'-..? WW WWW W /
:..' tCEs ietcEri :..' i..' 'i." i..' i.' .
CE2 /// JV // '/'" (riirrsir /w.f""" // W/ s.,isie'sr:i'.'.'. WW”
_......-...- g : i..' i.' s a s 2
OE i 5 fi_;;‘ E “‘W/ / sf" // j:..aiiirvi.; W;
i," i... i." i..' i.." gg i' i' ..i ()3 .
Di .' a a z A ' a
[IIOHoI/lg32, (i...] g t g t2 gteQHz g
I/oP1tol/oP4.,'. . GQLZE: d i.' i'
Dout-il-i-i-. Q1éA1) 33
l/OI to IIO32, g i' tKQLZZH . ,
|:|/0P1to|/OP4:| tzriz ))
f i. i:.itetc..ax :
ZZ i' i E §;E i'
Don' t care .
:;: : icfiiiiiii
gii55) /|ndeterminate
2002-09-04 17/19
TOSHIBA TC55V16366FF-167,-150,-133
NOTE : 1. Do not apply opposite data polarity to the I/O pins when they are in the output state.
2. Output enable and output disable times are specified as follows using the output load
shown in Fig. 1.
(a) tKQLz, tKQHz
CLK _/t_/tV-hc/tt
(See Note 1) (See Note 1)
ADSP N
7ri5TR5 x1
)CE2, iiii)(
KQg 0.2V KQHZ
Dout . y,
VALID DATA OUT
(See Note 2)
(See Note 3)
I. Input states are defined in the Synchronous Input Truth Table.
2. If the device was previously deselected, when the device is selected, the
output remains in a high impedance state in the present clock cycle
regardless of UE because of the output enable delay register.
Valid data appears in the second clock cycle when tTE' is low.
3. When the device is deselected, the output goes into a high impedance
state in the present clock cycle regardless of UE.
(b) tGQLz, tGQHz, tZHz
OE, 22 y, 7 tsz
tGQLZ tGQHZ
- th2V tt v0.2V
Dout JI I
. VALID DATA OUT x is5-
o.2v '' "om/
2002-09-04 18/19
TOSHIBA TC55V16366FF-167,-150,-133
PACKAGE DIMENSIONS
Plastic LQFP (LQFP100-P-1420-0.65B)
Unit in mm
22.0i0.2
20.0A0.1
0.825TYP
14 021:0 1
16.0:t0.2
15.0:t0.2
Ii!ili!iIilililili!ilililililiflliflflli!
( . 9:032:00“
0.575TYP -daaa-rtse7u-,j.-1-a,
1.4 -005-
21.0:02 I
0.1i'0.05 ‘;1
0.45~o.75§ CD
1.0:02
Weight: 0.91 g (typ)
2002-09-04 19/19
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