TC55V1001FI-10 ,131,072 WORD BY 8 BIT STATIC RAMapplications where high speed, low power and battery backup are required. And, with aguaranteed ope ..
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TC55V1001FI-10-TC55V1001FI-85
131,072 WORD BY 8 BIT STATIC RAM
TOSHIBA TC55V1001Fl/FTl/TRl/STl/SRI-85,-10
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
131,072-WORD BY 8-BIT STATIC RAM
DESCRIPTION
The TC55V1001FI/FTI/TRI/STI/SRI is a 1,048,576-bit static random access memory (SRAM) or anized as
131,072 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technelo§1 , t is device
operates from a single 2.7 to 3.6 V power supply. Advanced circuit technology provides both igh speed and
low power at an operating current of 3 mA/MHz (typ) and a minimum cycle time of 85 us. It is automatically
placed in low-power mode at 1 PA standby current (ty ) when chip enable (CE1) is asserted high or (CE2) is
asserted low. There are three control inputs. CE1 and E2 are used to select the device and for data retention
control, and output enable (OT) provides fast memory access. This device is well suited to various
microprocessor system applications where high speed, low power and battery backup are required. And, with a
guaranteed operating range of - 40° to 85°C, the TC55V1001FI/FTI/TRI/STI/SRI can be used in environments
exhibiting extreme temperature conditions. The TC55V1001FI/FTI/TRI/STI/SRI is available in a plastic 32-
51% ngll-outline package (SOP) and normal and reverse pinout plastic 32-pin thin-small-outlirfe package
FEATU RES
0 Low-power dissipation 0 Access Times (maximum):
Operating: 10.8 mW/MHz (typical) 2.7 to 3.6V
0 Standby current of 3 pzA (maximum) at . -85 -10
Ta = 25°C Access Time 85 ns 100 ns
0 Single power supply voltage of 2.7 to 3.6 V CE1 Access lime 85 ns 100 ns
q Power down features using CE1 and CE2. C_E2 Access Time 85 ns 100 ns
OE Access Time 45 ns 50 ns
0 Data retention supply voltage of 2 to 3.6 V
0 Direct TTL compatibility for all inputs and . Packages:
t t SOP32-P-525-1.27(W) (Weight: 1.04 gtyp)
ou. pu S . o TSOP I 32-P-0820-0.50 (FTI) (Weight: 0.34 gtyp)
tt Wide operating temperature range of - 40 TSOPI32-P-0820-0.50A(TRI) (Weight: 0.34 gtyp)
to 85°C TSOP I 32-P-0.50 (STI) (Weight: 0.24 g typ)
TSOP I 32-P-0.50A (SR1) (Weight: 0.24 g typ)
PIN ASSIGNMENT (TOP VIEW)
o 32 PIN SOP o 32 PIN TSOP
V 32 El V (Normal pinout) (Reverse pinout)
31% E i 31 El Ali?
A14 l: 3 303 CE2
A12 l: 4 29:] MN
A7 C 5 283 A13
A6 E 6 27:I A8
A5 E 7 26: A9
A4 E 8 25:! Alf
A3 |: 9 24:I OE
A2 E 10 23:! Alll
A1 |: 11 22:| CE1
A0 c 12 213 l/O8
l/OI I: 13 20: I/O?
I/O2 E 14 133 :18:
gagE 12 17: I/O4
PIN NAMES
A0 to A16 Addresglnputs PinNo. 1 2 3 4 5 6 7 8 9 IO 11 12 13 14 15 16
R’_W Read/Write Control PinName A11 A9 N A13 R/W CE2 A15 VDD NC A15 A14 A12 A7 A5 As A4
OE Output Enable .
W. CE2 Chip Enable Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 3 31 3_2
l/OI to I/og Data Input/Output PinName A3 A2 A1 Ao l/OI l/O2 l/O3 GND l/O4 l/O5 l/O6 I/O7 l/O8 CE1 A10 OE
VDD Power
GND Ground
NC No Connection
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1997-06-20 1/13
TOSHIBA TC55V1001Fl/FTl/TRl/STl/SRI-85,-10
BLOCK DIAGRAM
A7 --o Voo
£3 a a 3: A-o GND
A10 g Em ii' MEMORY CELL
m; en: 0E 05 ARRAY
A13 5tt <2 S?, 1024x128x8
jyf, iii, iig ti?, (1048576)
A16 real rere tECI
l/OI SENSEAMP
COLUMN ADDRESS
t COLUMNADDRESS
I/08 02
AOA1A2 A3 A4 A5 A6
OPERATION MODE
MODE l/OI to l/O8
Read DOUT
Write DIN
Outputs Disabled H High-Z
H x x High-Z
Standby .
x x x Hi h-Z
Note: x = don'tcare. H = logic high. L = logiclow.
ABSOLUTE MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage - 0.3 to 4.6 V
" Input Voltage - 0.3* to 4.6 V
VI/o Input/Output Voltage - 0.5 to VDD + 0.5 V
PD Power Dissipation 0.8 W
Tsolder Soldering Temperature (10s) 260 ''C
Tstrg. Storage Temperature - 55 to 150 ''C
Topr. Operating Temperature - 40 to 85 ''C
* - 3.0 then measured ata pulse width of 50 ns ** SOP
1997-06-20 2/13
TOSHIBA
TC55V1001Fl/FTl/TRl/STl/SRI-85,-10
DC RECOMMENDED OPERATING CONDITIONS (Ta = - 40° to 85°C)
SYMBOL
PARAMETER MIN
Power Supply Voltage 2.7
Input High Voltage 2.2
In Low Vol
Data Retention Supply Voltage
2.7 to 3.6 V
- 0.3*
Yoo + 0.3
* - 3.0 V when measured at a pulse width of 50 ns
DC CHARACTERISTICS (Ta = - 40° to 85''C, VDD = 2.7 to 3.6 V)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
I.._ Input Leakage Current V,N = 0V to Voo - - l 1_0 ,uA
IOH Output High Current VOH = VDD - 0.5V - 0.5 - - mA
IOL Output Low Current VOL = 0.4V 2.1 - - mA
W: " or CE2 = " or W = " or
I t t L k C t - - - i 1. A
LO Ou pu ea age urren OE = VIH: VOUT = 0V to V00 0 ,u
VDD = T l min - - 35
- - - c c e
CE1 - VIL and CE2 - " and 3V i 10% y 1/15 - - 10
bool W = VIHI IOUT = 0 mA .
VDD = mIn - - 40
Other Input = VlHNIL Tcycle
3.3V i 0.3V I/s - - 12
Operating Current - . mA
CE1 = 0.2V and VDD = mm - - 30
Tcycle
I CE2=VDD-0.2V 3Vi10% 1/15 - - 5
DDO2 MN = VDD - 0.2 V, IOUT = 0mA VDD = T I min - - 35
Other Inputs = Voo - 0.2 V/0.2V 3.3V i 0.3V cyc e Ms - - 6
IDDS1 til = " or CE2 = VIL - - 2 mA
VDD = Ta = 25°C - 1 2
3V i 10% Ta = - 40° to 85°C - - 40
IDDSZ Standby Current C? = I/oo - 0.2V VDD = Ta = 25 C - 2 3
(Note) or CE2 = 0.2V 3.3V t 0.3V Ta = -400 to 85°C - - 45 ,uA
VDD = 2.0 to 3.6V Ta = 25°C - 1 -
VDD = 3.0V Ta = - 40° to 40°C - - 3
Ta = - 40° to 85°C - - 35
Note: In standby mode with C? 2 VDD - 0.2 V, these limits are assured for the condition CE2 2 VDD - 0.2 V or CE2 E 0.2 V.
CAPACITANCE (Ta = 25°C,f = 1 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
Cm Input Capacitance VIN = GND 10 F
Cour Output Capacitance VQUT = GND 10
Note: This parameter is periodically sampled and is not 100% tested.
1997-06-20 3/13
TOSHIBA TC55V1001Fl/FTl/TRl/STl/SRI-85,-10
AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = - 40° to 85°C, VDD = 2.7 to 3.6 V)
READ CYCLE
TC55V1001FI/FTI/TRI/STI/SRI
SYMBOL PARAMETER -85 -10 UNIT
MIN MAX MIN MAX
tRc Read Cycle Time 85 - 100 -
tacc Address Access Time - 85 - 100
tco1 Chip Enable (m) Access Time - 85 - 100
tcoz Chip Enable (CE2) Access Time - 85 - 100
tOE Output Enable Access Time - 45 - 50
tCOE Chip Enable Low to Output Active 5 - 5 - ns
tOEE Output Enable Low to Output Active 0 - 0 -
too Chip Enable High to Output High-Z - 35 - 40
tooo Output Enable High to Output High-Z - 35 - 40
tOH Output Data Hold Time 10 - 10 -
WRITE CYCLE
TC55V1001FI/FTI/TRI/STI/SRI
SYMBOL PARAMETER -85 -10 UNIT
MIN MAX MIN MAX
twc Write Cycle Time 85 - 100 -
twp Write Pulse Width 60 - 60 -
tcw Chip Enable to End of Write 75 - 80 -
tas Address Setup Time 0 - 0 -
tum Write Recovery Time 0 - 0 - ns
tODw RNV Low to Output High-Z - 35 - 40
toaw R/W High to Output Active 0 - 0 -
tog Data Set up Time 35 - 40 -
tDH Data Hold Time 0 - 0 -
AC TEST CONDITIONS
Output load: 100 pF + one TTL gate
Input pulse level: 0.4 V, 2.4 V
Timing measurements: 1.5 V
Reference level: 1.5 V
tR, W: 5 ns
1997-06-20 4/13
TOSHIBA
TIMING DIAGRAMS
TC55V1001Fl/FTl/TRl/STl/SRI-85,-10
READ CYCLE (See Note 1)
ADDRESS X X
tacc Jor-i
CE2 / tcoz ,
_ tco1 '
a /?A (
tOE OD
toss tooo
Dom VALID DATA OUT
INDETERMINATE
WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4)
ADDRESS
tas 4 tum tum
‘W 2t pr
4/ tcw iF'"
Ai) ("
toDw toew
(See Note 2) (See Note 3)
tos tDH
See Note 5
//s()))eU'jtj)t,L5),
VALID DATA IN
(See Note 5)
1997-06-20 5/13
TOSHIBA TC55V1001Fl/FTl/TRl/STl/SRI-85,-10
WRITE CYCLE 2 (CEl CONTROLLED) (See Note 4)
ADDRESS X X
twe tWR
CE2 /// tcw NF"
tCOE A tODW
tos tDH
IAN (See Note 5) VALID DATA IN (See Note 5)
WRITE CYCLE 3 (CE2 CONTROLLED) (See Note 4)
ADDRESS X X
AS twe tWR
MN % /
CE2 " s' tcw "t
C? % /
tcos tODW
tos tDH
DIN (See Note 5) VALID DATA IN (See Note 5)
1997-06-20 6/13
TOSHIBA TC55V1001Fl/FTl/TRl/STl/SRI-85,-10
Note: (1) ww remains HIGH for the read cycle.
(2) If C-E goes LOW (or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs
will remain at high impedance.
(3) If CE goes HIGH (or CE2 goes LOW) coincident with or before R/W goes HIGH, the
outputs will remain at high impedance.
(4) If tTIT is HIGH during the write cycle, the outputs will remain at high impedance.
(5) Because I/O signals may be in the output state at this time, input signals of reverse
polarity must not be applied.
DATA RETENTION CHARACTERISTICS (Ta = - 40" to 85°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDH Data Retention Supply Voltage 2.0 - 3.6 V
VDH = 3.0V - - 35*
'0032 Standby Current pzA
I/DH = 3.6V - - 45
tcrm Chip Deselect to Data Retention Mode Time 0 - - nS
tR Recovery Time 5 - - mS
* 3 /sA (max) at Ta = - 40° to 40°C
CE1 CONTROLLED DATA RETENTION MODE (See Note 1)
VDD ) DATA RETENTION MODE
2.7 V ------ - - - - q.-----------------.----------
(See Note 2) (See Note 2)
Ihr, - - - l /
- VDD - 0.2 V
CE1 tCDR tR
1997-06-20 7/13
TOSHIBA TC55V1001Fl/FTl/TRl/STl/SRI-85,-10
CE2 CONTROLLED DATA RETENTION MODE (See Note 3)
VDD —DD—\ DATA RETENTION MODE h=,
2.7V -----------d---
I/m N 4 tCDR tR
V - - -
IL tk, \\ 0.2V f"
Note: (1) In (El controlled data retention mode, minimum standby current mode is entered when
CE2 E 0.2 V or CE2 E VDD - 0.2V.
(2) When CEI is operating at the VIH level (2 V), the operating current is given by IDDSl
during the transition of VDD from 3.6 to 2.2 V.
(3) In CE2 controlled data retention mode, minimum standby current mode is entered when
CE2 E 0.2 V.
1997-06-20 8/13
TOSHIBA TC55V1001Fl/FTl/TRl/STl/SRI-85,-10
PACKAGE DIMENSIONS (SOP32-P-525-1.27)
Units in mm
'huusiuesiuisssvii----a-
1ljliCjljljljliljljlr:jjrL_,
0.775TYP o.3:o.1
H _).pp,ia,.,z,,i,
10 7i0 2
1 4.1 3i0.3
(525mil)
2 8MAX
0,15 +9005
Weight: 1.049 (typ)
1997-06-20 9/13
TOSHIBA
PACKAGE DIMENSIONS (TSOP I 32-P-0820-0.50)
TC55V1001Fl/FTl/TRl/STl/SRI-85,-10
Units in mm
n: k x
113 CNI
sly-j',, s''):',':) co'
35 A c::;
17 a.'
18.4A0.2 " ci,'-; 1.0i0.1 0.1 :0.05
20.0:02 <5 1.2MAX
Weight: 0.349 (typ)
1997-06-20 10/13
TOSHIBA
TC55V1001Fl/FTl/TRl/STl/SRI-85,-10
PACKAGE DIMENSIONS (TSOP I 32-P-0820-0.50A)
Units in mm
j,liil cu.
IEI k x
"ar'Cl _ u) co
iFg "it,:,
16 a.'
18.4i0.2 = E 1 0io.1
20.0:02 ci 1.2MAX
0.5i0.
Weight: 0.349 (typ)
1997-06-20 11/13
TOSHIBA
PACKAGE DIMENSIONS (TSOP I 32-P-0.50)
1 :53320
g C) 1:0 +1
EEC 2'13 a
12:: 71E w'
CITE = r
m "ru,",f,r---r---r-
cur, .113
[:n: 1111
Eli. EC]
:1: -rr-g
D]: -re, K
1:1: :53 m
:11: 3:33
15§$ a 174:
4 118iOJ E
" 13410.2 CD
Weight: 0.249 (typ)
TC55V1001Fl/FTl/TRl/STl/SRI-85,-10
Units in mm
8.4MAX
t).1-_F0.05
4 1.2MAX
1997-06-20 12/13
TOSHIBA
PACKAGE DIMENSIONS (TSOP I 32-P-0.50A)
TC55V1001Fl/FTl/TRl/STl/SRI-85,-10
Units in mm
; 113131 8 7
323% C) 33 :1
:11 ZED g
1:]: 3D ei
ET: 33 1: Q . _
CIC :[E] g
- :11: .
SE -rT" m io]
EH; - I
Cl]: :EEJ I
[iT, E73 [lil
EU: :LLI
17CICL; 4:1 SAi
11.8'_"O.1 _ l E‘ 0.1io.05
13.4:02 CY - 41.2MAx
jx’ h, ll
c) (h,
foo--"
05:0.1
Weight: 0.249 (typ)
1997-06-20 13/13
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