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TC558128BFT-12 |TC558128BFT12TOSHIBAN/a1400avai131,072-WORD BY 8-BIT CMOS STATIC RAM
TC558128BFT-15 |TC558128BFT15TOSN/a1000avai131,072-WORD BY 8-BIT CMOS STATIC RAM
TC558128BJ-12 |TC558128BJ12TOSHIBAN/a1400avai131,072-WORD BY 8-BIT CMOS STATIC RAM
TC558128BJ-15 |TC558128BJ15TOSHIBAN/a3190avai131,072-WORD BY 8-BIT CMOS STATIC RAM


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TC558128BFT-12-TC558128BFT-15-TC558128BJ-12-TC558128BJ-15
131,072-WORD BY 8-BIT CMOS STATIC RAM
TOSHIBA TC558128BJ/BFT-12,-15
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
131 ,072-WORD BY 8-BIT CMOS STATIC RAM
DESCRIPTION
The TC558128BJ/BFT is a 1,048,576-bit high-speed static random access memory (SRAM) organized as
131,072 words by 8 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high
speed, it operates from a single 5 V power supply. There are two control inputs. Chip enable (CF) can be used
to place the device in a low-power mode, and output enable (6E) provides fast memory access. This device is
well suited to cache memory applications where high-speed access and high-speed storage are required. All
inputs and outputs are directly TTL compatible. The TC558128BJ/BFT is available in a plastic 32-pin SOJ
(400 mil width) and TSOP packages for high density surface assembly.
FEATU RES
0 Fast access time (the following are maximum values) ft Single power supply voltage of 5 V i- 10%.
TC558128BJ/BFT-12: 12 ns 0 Fully static operation
TC558128BJ/BFT-15: 15 ns 0 All inputs and outputs are TTL compatible
0 Low-power dissipation 0 Output buffer control using t5E
(the following are maximum values) 0 Package:
Cycle Time 12 15 20 25 30 ns SOJ32-P-400-1.27A (BJ) (Weight: 1.22 gtyp)
Operation (max) 190 170 140 130 120 mA TSOP ll 32-P-400-0.80C (BFT) (Weight: 0.34 g typ)
Standby: 1 mA (both devices)
PIN ASSIGNMENT PIN NAMES
TC558128BJ TC558128BFT A0 to A16 Address Inputs
A3 E 1 32 JA4 A3 1: 1° 32 = A4 I/O1 t_o |/08 Data Inputs/Outputs
A2 L 2 31 Cl A5 A2 I: 2 31 = A5 CE Chip Enable
A E JA A1 E 3 30 = A6 - .
tl L , :3 ye,' &: 4 29 :1 A_7 lh_/E Write Enable Input
- - CE I: 5 ' 28 = OE OE Output Enable
CE L 5 E 28 Cl OE 1/01: 6 Lu 27 211/08
1/01 I: 6 Lu 27 :I |/08 I/O2 E 7 - 26 2. 1/07 VDD Power (+ 5V)
V02 L 7 - 26 3 V07 vDD 1: 8 > 25 = GND GND Ground
VDD E 8 > 25 II GND GND = 9 24 = VDD
GND E 9 n. 24 JVDD 1/03 1: 10 t 23 = I/O6
1/03 E 10 o 23 :1 l/O6 |/O_4|: 11 F- 22 = 1/05
|/O4E11 ._ 2231/05 WEI=12 v 21 =A8
)h-tEc12 v21:IA8 A16=13 2021A9
A16E13 20:1A9 “5:14 19=IA10
A15E14 19 J/NIO “4:15 18=A11
A14E 15 18 JA11 A13: 16 17 :A12
A13 E 16 17 :1 A12
(SOJ) (TSOP)
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operatin ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and con itions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1998-06-26 1/10
TOSHIBA TC558128BJ/BFT-12,-15
BLOCK DIAGRAM
A15 "‘
A14 'dl I ttt MEMORY
A13 g Lu tii' CELL ARRAY VDD
A4 a u. 0
A3 :3 mg 512x256x8 GND
ti o m a (1,048,576) ' Cl
SENSE AMP
BUFFER
COLUMN
DECODER
DATA OUTPUT
BUFFER
COLUMN ADDRESS
BUFFER
A5 A7 A9 A11
A6 A8 A10 A12
GENERATOR
MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage - 0.5 to 7.0 V
" Input Terminal Voltage - 2.0* to 7.0 V
l/vo Input/Output Terminal Voltage - 0.5 * to VDD + 0.5 V
Po Power Dissipation 1.1 W
Tsolder Soldering Temperature (10s) 260 °C
Tstrg Storage Temperature - 65 to 150 ''C
Topr Operating Temperature - 10 to 85 °C
*: - 3 V with a pulse width of 10 ns
1998-06-26 2/10
TOSHIBA TC558128BJ/BFT-12,-15
DC RECOMMENDED OPERATING CONDITIONS (Ta = 0° to 70°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
I/oo Power Supply Voltage 4.5 5.0 5.5 V
VIH Input High Voltage 2.2 - VDD + 0.5 V
" Input Low Voltage - 0.5 * - 0.8 V
*: - 3V with a pulse width of 10 ns
DC CHARACTERISTICS (Ta = 0° to 70°C, VDD = 5V i 10%)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
IIL Input Leakage Current VIN = 0V to VDD - - i 10 PA
E = V W = V E = V
ILO Output Leakage Current IH or IL or IH - - , 10 PA
VOUT = 0V to VDD
IOH Output High Current VOH = 2.4V - 4 - - mA
IOL Output Low Current VOL = 0.4V 8 - - mA
tcycle = 12 ns - - 190
- tcycle = 15 ns - - 170
E = VILI Iout = 0 mA
IDDO Operating Current tcycle = 20 ns - - 140 mA
Other Inputs = VIH or VIL tcycle = 25 ns - - 130
tcycle = 30 ns - - 120
Iryosl c7 = V|H, Other Inputs = " or VIL - - 30
bose Standby Current 3 = VDD - 0.2V _ _ 1 mA
Other Inputs = VDD - 0.2V or 0.2V
CAPACITANCE (Ta = 25°C,f = 1.0 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
CIN Input Capacitance VIN = GND 6 pF
CI/o Input/Output Capacitance VI/O = GND 8 pF
Note: This parameter is periodically sampled and is not 100% tested.
1998-06-26 3/10
TOSHIBA TC558128BJ/BFT-12,-15
OPERATING MODE
MODE E E WE I/OI to l/O8 POWER
Read L L H Output boo
Write L x L Input boo
Outputs Disable L H H High Impedance IDDO
Standby H x x High Impedance IDDS
X : Don't care
1998-06-26 4/10
TOSHIBA
TC558128BJ/BFT-12,-15
AC CHARACTERISTICS(Ta = 0° to 70°C (Note 1vm, = 5v l 10%)
READ CYCLE
TC5581283J/BFT-12 TC5581283J/BFT-15
SYMBOL PARAMETER UNIT
MIN MAX MIN MAX
tRc Read Cycle Time 12 - 15 -
tAcc Address Access Time - 12 - 15
tco Chip Enable Access Time - 12 - 15
toe Output Enable Access Time - 6 - 8
tOH Output Data Hold Time from Address Change 5 - 5 - ns
tCOE Output Enable Time from Chip Enable 5 - 5 -
tOEE Output Enable Time from Output Enable 1 - 1 -
tCOD Output Disable Time from Chip Enable - 6 - 8
tooo Output Disable Time from Output Enable - 6 - 8
WRITE CYCLE
TC558128BJ/BFT-12 TC558128BJ/BFT-15
SYMBOL PARAMETER UNIT
MIN MAX MIN MAX
twc Write Cycle Time 12 - 15 -
twp Write Pulse Width 8 - 9 -
tcw Chip Enable to End of Write 10 - 12 -
taw Address Valid to End of Write 10 - 12 -
tAs Address Setup Time 0 - 0 -
tWR Write Recovery Time 0 - 0 -
tos Data Setup Time 6 - 8 -
tDH Data Hold Time 0 - 0 -
toew Output Enable Time from Write Enable 1 - 1 -
toow Output Disable Time from Write Enable - 6 - 8
AC TEST CONDITIONS FIG. 1
5 V - 5 V
Input Pulse Level 3.0V, 0.0V
Input Pulse Rise and Fall Time 3 ns 480n 480n
Input timing Measurement 1 5V " pm " pm
Reference Level .
CL = 30 pF 255 Q CL = 5 pF 255 Q
Output Timing Measurement 1 5V l
Reference Level .
(For tcoe, tOEE: tCOD,
Output Load Fig. 1 tone. tOEW and toDw)
1998-06-26 5/10
TOSHIBA TC558128BJ/BFT-12,-15
TIMING DIAGRAMS
READ CYCLE (See Note 2)
ADDRESS
OD (See Note 6)
tooo (See Note 6)
EE (See Note 6
Dout VALID DATA OUT
tCOE (See Note 6)
INDETERMINATE INDETERMINATE
WRITE CYCLE 1 (W CONTROLLED) (See Note 5)
ADDRESS
tODW (See Note 6) tOEw (See Note 6)
Dout (See Note 3) (See Note 4)
INDETERMINATE INDETERMINATE
tos to
Din VALID DATA IN
1998-06-26 6/10
TOSHIBA TC558128BJ/BFT-12,-15
WRITE CYCLE 2 LEE- CONTROLLED) (See Note 5)
ADDRESS
tODW Note 6)
(See Note 6)
INDETERMINATE tos tDH
Din VALID DATA IN
1998-06-26 7/10
TOSHIBA TC558128BJ/BFT-12,-15
Note: (1) Operating temperature (Ta) is guaranteed for transverse air flow exceeding 400
linear feet per minute.
(2) WE remains HIGH for the Read Cycle.
(3)If tTE goes LOW coincident with or after IT/E goes LOW, the outputs will remain
at high impedance.
(4) If UE goes HIGH coincident with or before W goes HIGH, the outputs will remain
at high impedance.
(5) If UE- is HIGH during the write cycle, the outputs will remain at high impedance.
(6) The parameters specified below are measured using the load shown in Fig. 1.
(A) tCOE, tOEE, tOEW Output ...... Enable Time
(B) tCOD, tODO, tODW Output ...... Disable Time
(A) (B)
_-_ _-_
' _) 0.2 v
0.2V '
Dow -, VALID DATA OUT
0.2 V f - 0.2 v
INDETERMINATE INDETERMINAT 4
1998-06-26 8/10
TOSHIBA TC558128BJ/BFT-12,-15
PACKAGE DIMENSIONS
Plastic SO) (SOJ32-P-400-1.27A)
Unitsinmm
r-Ir-It-Iron.?).,-?,-?.?.-,,-?,""],"""?!"",
a si t
2 a g.
L.JLuulcltuL.ludulL...lLdultul-lulrut-l
I 21-38MAX
20.96i0.12
l omytls
0.8MIN
Weight: 1.22g (typ)
1998-06-26 9/10
TOSHIBA TC558128BJ/BFT-12,-15
PACKAGE DIMENSIONS
Plastic TSOP (TSOPII 32-P-400-0.80C)
Units in mm
JlfiiiflHlfifigfifHlflUi?
10.16L0‘1
“79:02
1HHH ill HHH " " HH "
0.67TYP = ' 0. 32, 007 Elma
"m 13.74MAX - g Q 'g.
fl E a '
H” 13.34i0.1 ' o. N m _/f''
, r T" '- g
( 3 o' '
"v'' " T0~100
Ejid.1 3 I =
fi 0 5:0 1
C5 o.eio.2
Weight: 0.34 g (typ)
1998-06-26 10/10

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