TC5564APL-15 ,-0.3 to 7V; 1W; 150ns; 8.192 word x 8bit MOS static RAMTOSHIBA M08 MEMORY PRODUCTSTC5564APL-15 ,TC5564APL-20TC5564AF L-15 ,TC5564AF L-208,192 WORD X 8 BIT ..
TC5564APL-15 ,-0.3 to 7V; 1W; 150ns; 8.192 word x 8bit MOS static RAMTOSHIBA M08 MEMORY PRODUCTSTC5564APL-15 ,TC5564APL-20TC5564AF L-15 ,TC5564AF L-208,192 WORD X 8 BIT ..
TC5564APL-15 ,-0.3 to 7V; 1W; 150ns; 8.192 word x 8bit MOS static RAMTOSHIBA M08 MEMORY PRODUCTSTC5564APL-15 ,TC5564APL-20TC5564AF L-15 ,TC5564AF L-208,192 WORD X 8 BIT ..
TC5564APL-15 ,-0.3 to 7V; 1W; 150ns; 8.192 word x 8bit MOS static RAMTOSHIBA M08 MEMORY PRODUCTSTC5564APL-15 ,TC5564APL-20TC5564AF L-15 ,TC5564AF L-208,192 WORD X 8 BIT ..
TC5564APL-20 ,8,192 WORD X 8 BIT CMOS STATIC RAMTOSHIBA M08 MEMORY PRODUCTSTC5564APL-15 ,TC5564APL-20TC5564AF L-15 ,TC5564AF L-208,192 WORD X 8 BIT ..
TC5565AFL10 ,65,536 bit static random access memory organized as 8,192 words by 8 bits using CMOS technologyTOSHIBA MOS MEMORY PRODUCTS TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, T ..
TC9276P ,SUMM-DELTA MODULATION SYSTEM DA CONVERTER WITH BUILT-IN 8 TIMES OVER SAMPLING DIGITAL FILTERTC9276F/PT(‘Q77EF T(‘Q776Pv-2-A MODULATION SYSTEM DA CONVERTER WITH BUILT-IN 8 TIMESOVER SAMPLING D ..
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TC9279F ,Summ-Delta Modulation system DA converter with built-in 8 times over sampling digital filterTC9279F/PT(‘Q77QF T(‘Q77QPOVER SAMPLING DIGITAL FILTERThe TC9279F and TC9279F are a second-order EA ..
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TC5564APL15-TC5564APL-15
-0.3 to 7V; 1W; 150ns; 8.192 word x 8bit MOS static RAM
?@WDIA WEEDS giElifjl(i)]fyf PMMMQTS
8,192 WORD 'sf, 8 BIT CMOS STATIC RAM
TC5564APL-15 ,TC5564APL-20
TC5564AFL-15,TC5564AFL-20
DESCRIPTION
TC5564APL is 65536 bits static random access
memory organized as 8192 words by 8 bits usmg
CMOS technology, and operates with a single 5V
power supply.
Advanced CIFCUII techniques provides low power
feature with a maximum operating of 5mA/MHZ.
Operation current depends on cycle time.
TC556iAPr- has three control inputs. Two chip
enables (CEI, CE2) allow for device selec_tion and
data retention control. Output enable (OE) input
provides fast memory access. When device IS placed
in standby mode with chip off state, standby current
FEATURES
o Low Power Dissipation
5mA/MHZ (MAX.) Operating
0.2,uA (MAX.) at Ta=25''C Standby
1 .OpA (MAX.) at Ta=60°C Standby
o 5V Single Power Supply
0 Fully Static Operation
0 Data Retention Voltage : 2.0--5.5V
0 Plastic DIP and Plastic Flat Package
o Pin Compatible with 2764 type EPROM
195m CONNECTMN;;T_ (TOP VIEW)
64k bit. EPROM
TC5564APL TIM2764D
PRELIMINARY
is typically O.01PA. So the TC5664APL IS suitable
for use in various microprocessor application sys-
tems where low power and battery back up are
required. Ultra low standby power allow not only
battery but capacitance backup.
Pin assignment of TC5564APL is pin-compatible
with the 64K bits EPROM (TMM2764D). RAM and
EPROM are then interchangeable in the same
socket, resulting in flexibility in the definition of the
qyantity of RAM versus EPROM in microprocessor
application systems,
TC5564APL is offered in both a standard duaI-in-
line 28 pin plastic package (0.6 inch width) and
small-out-ri plastic flat package.
0 Access Time
TC5564APL-15
TC5564AF L-15
TC5564AP L-20
TC5564AF L-20
Address Access Time
(MAX) 150ns 200ns
C_ET Access Time
(MAX.) 150ns 200ns
CE2 Access Time
(MAX.) 150ns 200ns
TyrfAccess Time I 70ns 100
(MAX.) I
- D-57 -
o Directly TfL Compatible : All Inputs and Outputs
0 Wide Temperature Operation : -40-85'C
BLOCK mAGRAM
0 SHERATON
PRECHAROE CIRCU "
---o Irrm
IDIORY CELL
(65536)
--<, 0ND
RIO ESTER
ROI ADDREH
DEODLR
ROW ADDRES
SENS! AMP.
COLUMN 05001311?
TtyiliMN'lel5, T05564APl-20
T65564AFl-l 5, TB5564AFL-20
PiN NAMES OPERATING MODE
A0~A12 Address Inputs Operation $1 CE2 tre R/W l/OI- Power
R/W Read/Write Control Input Mode I/08
E Output Enable Input Read L H L H Dom
m, CE2 Chip Enable Inputs Write L H * L Dm IDDO
I/O1 --l/O8 Data Input/Output Output Deselect * * H * High-Z
l/oo Power (+5V) Standby H * * * n loos
GND Ground * L * * u loos
N. C. No Connection
SYMBOL ITEM RATING UNIT
'Von Power Supply Voltage --0.3--7 .O V
VW Input Voltage -O.3'"--VDD V
I/vo Input and Output Voltage -0. 5~Voo+0.5 V
Po Power Dissipation 1 .0(O.6)“‘ W
Tsome, Soldering Temperature 260-10 'C.sec
Tstg Storage Temperature -- -55--1 50 "C
Top. Operating Temperature --40--85 "C
* 8.5V at 100ns,
* * --3.OV Pulse width 50ns
* * * SOP
clilliiE, - " v'irs,iTa----40--ms'c)
SYMBOL MIN. TYP MAX. UNIT
VDD Power Supply Voltage 4. 5 5.0 5. 5 V
w. Input High Voltage. 2.2 - voo+o.3 V
( Input Low Voltage -0.3' - 0.8 V
I/ore Data Retention Supply Voltage 2.0 - 5.5 V
* -3.0V Pulse width SOns
W. Tug; w
- (Taa---i-85'C, VDD=5Vi 10% Unless other wise noted)
PARAM ETE R
SYMBOL CONDITIONS MIN TYP. MAX. UNIT
lm Input Leakage Current V.N=0~VDD - - i1 .0 PA
lo... Output High Current VOH=2.4V -1 .0 - - mA
IOL Output Low Current VOL=O.4V 4.0 - - mA
I/ou Output High Voltage lore -20PA Von-O. 1 - - V
VOL Output Low Voltage LoL=20pA - - O. 1 V
EET=VIH or CE2=VIL or
ILO Output Leakage Current R/wr-NL - - :1 .0 AA
or E:\JIH, Vou1=0~Voo
- D-58 -
T1mi64hPb1 5, T05564APl-20
TG5564AFl-15, T05iiMllFb20
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
WW”, and CE2 = “W: lps - W IO
VIH Other Input--- 5 Tc5564APL-15
loom Operating Current VIH/VIL b', TC5564AFL-15 - - 40 mA
IOUT = OmA g TC5564APL-20 - i 35
E TC5564AFL-20
W=02V and tcycle-ls - - 5
CE2=VoD-0. 2V, w TC5564APL15
IDDo2 Operating Current Other Input 5 . - - 35 mA
c-z/oo-O/f/om/ ic, TC5564AFL15
now = OmA duty 100% g :ggggjggggg - - 30
.0051 Standby Current CE1:V\H or CE2--VI - - 2 mA
t%---Vci-0.2V or Ta=25°C - 0.01 0.2
IDDSQ Standby Current CE2=O.2V st/l
Voo:2.o~5.5v Ta=60'C - - 1-0
Note: (1) In standby mode with CE1 gVoD-OQV, these specmcatlon hmlts are guaranteed under the
condmon of CE2iaVocr-0, 2V or CE2§O.2V.
(2) All voltage IS measured from GND.
AM'tACtrgt'dtett (Ta=25'c. f:1MHz)
SYMBOL PARAMETER CONDITIONS MAX. UNIT
Cm Input Capacitance Vee-GND 10 pF
Cour Output Capacitance VoszND 10 pF
Note : This parameter is periodically sampled and IS not 100% tested.
- D-59 -
T65564APL-15, T65564APL-20
T05564AFL-‘I5, T05564AFl-20
A. C. CHARACTERISTICS
READ CYCLE
T ' TC5564APL-15 TC5b64APL-20
SYMBOL ' PARAMETER I TC5564AF L-15 TC5564AFL-20 ' UNIT
1 MIN. , MAX. MIN. MAX.
T tRc Read Cycle Time 150 - 200 w T
Mr Address Access Time - [ 150 - l 200
tcol _ CE1 Access Time - 150 - _ 200
tcoz CE2 Access Tune - 150 L - i 200
toe 1 Output Enable to Output in Valid - L 70 - j 100
--c_, ns
Chip Enable to (CE1, CE2) ‘
ICOE IC) - 1O -
i-- Output In Low-Z 1
Lori Output Enable to Output Low-Z A 5 - 5 j -
ton Chip Enable (CEI, CE2) Output In Hith I - 7O - 100 1
Output Enable to _1
tooo ' - 60 - 80
Output High-Z
IOH Output Data Hold Time 20 - 20 _
WRITE CYCLE
F TC5564APL-15 TC5564APL-20
SYMBOL PARAMETER TC5564AFL-15 TC5564AFL-20 UNIT
MIN. MAX. MIN. I MAX.
twc Wnte Cycle Time 150 - 200 -
twp Write Pulse Width 100 - 150 -
tcw Chip Selection to End of Write 120 - 180 A
tas Address Set up Time 0 H O -
' ----]
twn Write Recovery Time o - O -
toow R/VV to Output High-Z - 70 - 100
IoEw R/W to Output Low-Z 1O - 1O -
IDs Data Set Up Time 60 - 80 -
mm Data Hold Time o - O -
i 2.4V/0.6V I/OPin
0 Timing Measurement Reference Levels : 2 .2V/0.8V RI:24 m
q Output Reference Levels . 2.2V/O.8V co g 32:8100
0 Input Pulse Rise and Fall Times : 5ns C :lOOpF
. Output Load : See F:g.1 (Inc lude 115)
D 1181588
(or Equivalent)
FigAl Output Lood
TIMING WAVEFORMS
READ CYCLE (1)
T05564APL-15, TG5564APl-20
T85564AFl-15, TMM4liFb20
ADDRESSES
CE;? 1llllijji, tAcc, \T\\\\\\\\: \\\\\\\\m
/iiillUf tcol -y//'/'f/,i//irii/i//s//////i/i/ /f/i/,,(///,t,
t5E /iiriiiii'vu,'" /,4¢57{;5%5W////m
WRITE CYCLE (R/W Controlled Write)
ADDRESSES
w [iiiiiilil twp z WR
CE2 1lllGlllllliiilj] tcw "'liiiiiyi)iiiy%fijr,rr
tTW- '',;iF77iS777)s ' tcw li/lil/ily/l,
DOUT RIE%EiiEE%ir, (G)
D-61 -
T05564APl-I li, TG5564APl-20
'miti64liF1r1li, 'mi5MhFir20
WRITE CYCLE 2 (4) (tFET Controlled Write)
w mm \\\\\\\\\\\ MW/W/M
CE2 Etltlttit/'diliilt/ /jir1liiii1i1yriji?"
'c7T -""'isiiiS7)s t /
m \\\\\\\\i\§s7 (/iiiiil tiiics-:-v:i:1
///// l
cel- i"ijT7rffi"rrp]'"p]] y///,,f',f/f/f/,tttfj/f/,/ttf/,ff/j(/f/f/f/ff
tCOE I tonw
Dom -----------HEE)
- D-62 -
T65564APL-15. 'miii64Mr20
T05564AFl-l ii, TtaiMllFllr20
Note , (1 ) R/W IS High for Read Cycle. (2) ASSUming thatciLouvtransmon or CE2 High transmon occurs comeldemwnh
or after R/W low transmon, Outputs remain in a high impedance state. (3) Assuming that C757 High transution or
CE2 Low transmon occurs comeldent With or prior to R/W High transation, outputs remain in a high impedance
state. (4) Assuming that Oins High for Write Cycle, Outputs are m high impedance state during this period.
DATA RETENTION CHARACTERISTics (Ta = -4C) _ 85 C)
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
VDH Data Retention Supply Voltage - - - - - 2.0 - 5.5 V
' ---- - Ta:25°C i !0.01 0.2
IDDs2 Standby Current Ta:60°C - - 1 _C) “A
((309 Chip Deselection to Data Retention Mode __- u 0 - - ps
IR Recovery Time tact!) - - us
CE1 Controlled Data Retention Mode (2)
Vnh DATA hhTHNTlUN Mona
VD“ - uzv
CE2 Controlled Data Retention Mode (4)
VIM: ' , .
DATA HF'TENTIUN MODL
Note : (1) Tee : Read Cycle Time (2) In Wcomrolled data retention mode, minimum standby current mode IS achieved
under the condition of CE2SO.2V or CE2 2_eVmo--02V, (3) If the VIH of Wis 2.2V in operation, during the period
that the V00 Voltage is going down from 4.5 to 2.4V, loom current flows. (4) In CE2 controlled data retention
mode, minimum standby current mode is achieved under the condition of CE2so.2V."
_ V C C 5, ' 'C'4' . _;§
, e P T “(,y
tss.' . RT 'It, ("1 .'
he TC5564APL is an asynchronous RAM using
after only row address change, as is shown in the
address activated circuit technology, thus the inter-
nal operation is synchronous. Then once row
address change occur, the precharge operation
executed by internal pulse generated from row
address transient. Therefore the peak current flows
ADDRESS
IDDo(mA)
following figure.
This peak current may induce the noise on VDD/
GND line. Thus the use of about O.1#F decoupiing
capacitor every device is recommended to eliminate
such noise.
vDstsv
VIH-- 53V
v, L-OZV
HDR lZON 200ns/div
Fig. TYPICAL CURRENT WAVEFORMS
- D-63 -
Ttyili64N'lr15, T65564APl-20
TtyitiMMr15, T'iyi5Ml1rir20
Unit in mm
DIP 28 PIN OUTLINE DRAWING (6028A-P)
P-Nr-tr"''',-'-",-'-''-,.-",'''-,'-'",'-,,-,
-x=FG-T-E-gG-J=IiJE=rL-AELJL-JuairL-aL-gL-J
14.2MAX
l 5.24i025
5.2 MAX
38.0 MAX , 2
0.5 t 0.1 5
14 I 0.15
2.541025 0.2ty-005
Note : Lead pitch is 2.54 and tolerance is t 0.25 against theoretical center of each lead that is obtained on the
basis of No. 1 and No. 28 leads.
‘23”ij L
Unit in mm
MFP 28 PIN OUTLINE DRAWINGS (F28GA-P)
[l_fHljrlll'lllflfllll'lllflll
"yr"l]lll]ljrllnllll],ll,
[1 18.9MAX ii. g 11.8:t05
'tfee,?"'"'")?,?,?,"'"'------;-,,,-' d E‘
0.43 10.05 l L27t0.1 'j' -.., II-SiOA:
.1 I d
Note : Lead pitch is 1 .27 and tolerance is i0. 12 against theoretical center of each lead that is obtained on the basis of
No.1 and No.28 leads.
Toshiba does nat assume any responsibility for use of any circuitry described : no circuit patent licenses are implied, and Toshiba teserves the right. at any time
without notice, to change said Circuitry.
©May, 1986 Toshiba Corporation
Note :
- D-64 -
www.ic-phoenix.com
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