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TC554161FTL-70L-TC554161FTL-85L
262,144-WORD BY 16 BIT STATIC RAM
TOSHIBA TC554161FTL-70L,-85L,-10L
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT STATIC RAM
DESCRIPTION
The TC554161FTL is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by 16
bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5 V
i 10% power supply. Advanced circuit technology provides both high speed and low power at an operating
current of 10 mA/MHz (typ) and a minimum cycle time of 70 ns. It is automatically placed in low-power mode
at 60 ph standby current (max) when chip enable (UE) is asserted high. There are two control inputs. CE is
used to select the device and for data retention control, and output enable (UE) provides fast memory access.
Data byte control pin (W, W) provides lower and upper byte access. This device is well suited to various
microprocessor system applications where high speed, low power and battery backup are required. The
TC554161FTL is available in a plastic 54-pin thin-small-outline package (TSOP).
FEATU RES
0 Low-power dissipation 0 Access Times (maximum):
Operating: 55 mW/MHz (typical) TC554161FTL
0 Standby current of 8 PA (maximum) at -70L -85L -10L
Ta = 25°C Access Time 70 ns 85 ns 100 ns
0 Single power supply voltage) 5 V i 10% E Access Time 70 ns 85 ns 100 ns
0 Power down features using CE. E Access Time 35 ns 45 ns 50 ns
0 Data retention supply voltage of 2 to 5.5 V .
o Di t TTL tibilit f 11 . t d qt Package:
1rec compa 1 1 1 y or a 1npu S an TSOPE 54-P-400-0.80 (FTL) (Weight: 0.55 gtyp)
outputs
PIN ASSIGNMENT (TOP VIEW) PIN NAMES
NC E IO 54 JA4 A0 to A17 Address Inputs
A3 E 2 53 Cl A5
A2 L 3 52 ZIA6 l/OI to_|/O16 Data Inputs/Outputs
A1 L 4 51 CIA? CE Chip Enable
A0 L 5 50 Cl NC R/W Read/Write Control
1/016 E 6 49 JI/OI -
I/O15 E 7 48 Cl I/O2 OE Output Enable
VDD E 8 47 Cl VDD 7 W Data Byte Control Input
GND E 9 46 Cl GND
l/014 L 10 45 II I/O3 VDD Power (+ 5V)
|/O1_3E 11 44 JKM GND Ground
UB E 12 43 3 LB .
E E 13 42 IE NC No fonnection
OP E 14 41 :1 OP OP* Option
W L 15 40 3 NC *: OP pin must be open or connected to GND.
1/012 E 16 39 i] 1/05
l/O11 E 17 38 31/06
GND L 18 37 :iGND
VDDE19 36 jVDD
1/010 L 20 35 Cl l/O?
1/09 C 21 34 Cl 1/08
NC L 22 33 3A8
A17 E 23 32 JA9
A16 E 24 31 3A10
A15 L 25 30 3A11
A14 E 26 29 3A12
A13 E 27 28 Cl NC
(Normal pinout)
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operatin ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and con itions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1997-06-12 1/9
TOSHIBA
BLOCK DIAGRAM
DECODER
>>>>222222
O—‘NWNWhU’ImN
BUFFER
GENERATOR
MEMORY
CELL ARRAY
1,024 x 256 x 16
(4,194,304)
SENSE AMP
COLUMN
DECODER
COLUMN
TC554161FTL-70L,-85L,-10L
A-o GND
OUTPUT
BUFF ER
OUTPUT
BUF FER
ADDRESS BUFFER
A4 A6 A8 A10
A5 A7 A9 A11
MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage - 0.3 to 7.0 V
VlN Input Voltage - 0.3 * to 7.0 V
VI/o Input/Output Voltage - 0.5 * to VDD + 0.5 V
PD Power Dissipation 0.6 W
Tsolder Soldering Temperature (10s) 260 'C
Tstrg Storage Temperature - 55 to 150 °C
Topr Operating Temperature 0 to 70 'C
* - 3.0 V when measured at a pulse width of 30 ns
DC RECOMMENDED OPERATING CONDITIONS (Ta = 0° to 70°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDD Power Supply Voltage 4.5 5.0 5.5 V
" Input High Voltage 2.2 - VDD + 0.3 V
VIL Input Low Voltage - 0.3 * - 0.8 V
VDH Data Retention Supply Voltage 2.0 - 5.5 V
* - 3.0 V when measured ata pulse width of 30 ns
1997-06-12 2/9
TOSHIBA TC554161FTL-70L,-85L,-10L
DC CHARACTERISTICS(Ta = 0° to 70°C, VDD = SV , 10%)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
IIL Input Leakage Current " = 0V to VDD - - i 1.0 prA
c-E = V = V to-E = V
Lo Output Leakage Current C [H or RNV IL or O IH - - + 1.0 pA
VOUT = 0V to VDD
IOH Output High Current VOH = 2.4V - 1.0 - - mA
IOL Output Low Current VOL = 0.4V 2.1 - - mA
E = " 70 ns - - 110
bool MN = VIHI IOUT = 0 mA Tcycle 85 ns, 100 ns - - 100 mA
Other Inputs = Vm/Ihr, 1 ps - 15 -
Operating Current E = 0.2V 70 ns - - 100
'DDOZ MN = VDD - 0.2 v, IOUT = 0 mA Tcycle 85 ns, 100 ns - - 90 mA
Other Inputs = VDD - 0.2 V/0.2V 1 ps - 10 -
|DDS1 _E = VIH, Other Inputs = VIHNIL - - 3 mA
I Standby Current E = VDD - 0.2V Ta = 25°C - 4 8 A
DDS2 VDD = 2.0 to 5.5V Ta = ty' to 70°C - - 60 "
CAPACITANCE (Ta = 25°c,f = 1 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
Cm Input Capacitance VIN = GND 10 pF
COUT Output Capacitance VOUT = GND 10 pF
Note: This parameter is periodically sampled and is not 100% tested.
OPERATING MODE
MODE E TE R/IN E W l/OI to l/O8 I/O9 to l/O16 POWER
L L Output Output IDDO
Read L L H H L High-Z Output IDDO
L H Output High-Z IDDO
L L Input Input IDDO
Write L x L H L High-Z Input IDDO
L H Input High-Z IDDO
L H H x x
Outputs Disable High-Z High-Z IDDO
L x x H H
Standby H x x x x High-Z High-Z loos
x = don't care
H = logic high
L = logiclow
1997-06-12 3/9
TOSHIBA
TC554161FTL-70L,-85L,-10L
AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = 0° to 70°C, VDD = 5 V i 10%)
READ CYCLE
TC554161FTL
SYMBOL PARAMETER -70L -85L -10L UNIT
MIN MAX MIN MAX MIN MAX
tRc Read Cycle Time 70 - 85 - 100 -
tAcc Address Access Time - 70 - 85 - 100
tco Chip Enable Access Time - 70 - 85 - 100
tog Output Enable Access Time - 35 - 45 - 50
tBA Data Byte Control Access Time - 35 - 45 - 50
tOH Output Data Hold Time 10 - 10 - 10 -
tCOE Chip Enable Low to Output Active 10 - 10 - 10 - ns
tOEE Output Enable Low to Output Active 5 - 5 - 5 -
tBE Data Byte Control Low to Output Active 5 - 5 - 5 -
tOD Chip Enable High to Output High-Z - 25 - 30 - 35
tooo Output Enable High to Output High-Z - 25 - 30 - 35
tBD Data Byte Control High to Output High-Z - 25 - 30 - 35
WRITE CYCLE
TC554161FTL
SYMBOL PARAMETER -70L -85L -1OL UNIT
MIN MAX MIN MAX MIN MAX
twc Write Cycle Time 70 - 85 - 100 -
twp Write Pulse Width 50 - 55 - 60 -
tcw Chip Enable to End of Write 60 - 70 - 80 -
th Data Byte Control to End of Write 50 - 55 - 6O -
tas Address Setup Time 0 - 0 - 0 -
tWR Write Recovery Time 0 - 0 - O - ns
tos Data Setup Time 30 - 35 - 40 -
tDH Data Hold Time 0 - 0 - 0 -
tOEW R/W High to Output Active 5 - 5 - 5 -
tODW R/W Low to Output High-Z - 25 - 30 - 35
AC TEST CONDITIONS
Output load: 100 pF + one TTL gate
Input pulse level: 0.6 V, 2.4 V
Timing measurements: 1.5 V
Reference level: 1.5 V
tR, tF: 5 ns
1997-06-12 4/9
TOSHIBA TC554161FTL-70L,-85L,-10L
TIMING DIAGRAMS
ADDRESS
Dout VALID DATA OUT
IND ERMINATE
WRITE CYCLE 1 jR/W CONTROLLED) (See Note 4)
ADDRESS X X
tas ’ twp - tWR
RNV )c _ /
CE _ /
W, LE "As, A"
tODW tOEW
Dout (See Note 2) k (See Note 3)
I tos toc
Din (See Note 5) X VALID DATA IN X (See Note 5)
1997-06-12 5/9
TOSHIBA TC554161FTL-70L,-85L,-10L
WRITE CYCLE 2 LEE- CONTROLLED) (See Note 4)
ADDRESS X X
tas twp tWR
R/W 's, ,
tTir s, 'Rss, /
W,t7 ptr"
Dout ,
tos tDH
Din (See Note 5) VALID DATA IN (See Note 5)
WRITE CYCLE 3 (trg, tTIT CONTROLLED) (See Note 4)
ADDRESS X X
JAS, 4 twp _ tum _
_ tcw ’
ET _ 2
UB, LB 'y _ ,
Dout A
tos tDH
Din (See Note 5) VALID DATA IN (See Note 5)
1997-06-12 6/9
TOSHIBA TC554161FTL-70L,-85L,-10L
Note: (1) R/W remains HIGH for the read cycle.
(2) If CE goes LOW coincident with or after R/W goes LOW, the outputs will remain at high
impedance.
(3) If tTrif goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at
high impedance.
(4) If ttE is HIGH during the write cycle, the outputs will remain at high impedance.
(5) Because I/O signals may be in the output state at this time, input signals of reverse
polarity must not be applied.
1997-06-12 7/9
TOSHIBA TC554161FTL-70L,-85L,-10L
DATA RETENTION CHARACTERISTICS (Ta = 0° to 70°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDH Data Retention Supply Voltage 2.0 - 5.5 V
VDH = 3.0V - - 30*
box Standby Current pA
VDH = 5.5V - - 60
tCDR Chip Deselect to Data Retention Mode Time 0 - - nS
tR Recovery Time 5 - - mS
* 6,uA (max) at Ta = 0°to 40°C
UECONTROLLED DATA RETENTION MODE
VDD -1 DATA RETENTION MODE
4.5 v - - - - - ----_
(See Note) (See Note)
" -.--. l /
/ Von - 0.2V
E 4 tCDR 4 tR _
Note: When CE is operating at the Vm level (2.2 V), the operating current is given by IDDSl during
the transition of VDD from 4.5 to 2.4 V.
1997-06-12 8/9
TOSHIBA TC554161FTL-70L,-85L,-10L
PACKAGE DIMENSIONS (TSOPII 54-P-400-O.80)
Units in mm
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L 22.62MAX
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01:0 05
0.5i0.1
Weight: 0.55g (typ)
1997-06-12 9/9
www.ic-phoenix.com
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