TC55257DFI-85L ,32,768 WORD x 8 BIT STATIC RAMapplications where high speed, lowpower and battery backup are required. And, with a guaranteed ope ..
TC55257DFI-85L ,32,768 WORD x 8 BIT STATIC RAMTOSHIBA TC55257DPl/DFl/DFTl/DTRl-7OL,-85L32,768-WORD BY 8-BIT STATIC RAMThe TC55257DPI/DFI/DFTI/DTR ..
TC55257DFI-85L ,32,768 WORD x 8 BIT STATIC RAMTOSHIBA TC55257DPl/DFl/DFTl/DTRl-7OL,-85L32,768-WORD BY 8-BIT STATIC RAMThe TC55257DPI/DFI/DFTI/DTR ..
TC55257DFI-85L ,32,768 WORD x 8 BIT STATIC RAMTOSHIBA TC55257DPl/DFl/DFTl/DTRl-7OL,-85L32,768-WORD BY 8-BIT STATIC RAMThe TC55257DPI/DFI/DFTI/DTR ..
TC55257DFL ,32,768 WORD-8 BIT STATIC RAMTOSHIBA TC55257DPL/DFL/DFTL/DTRL-55V,-7OV,-85V32,768-WORD BY 8-BIT STATIC RAMThe TC55257DPL/DFL/DFT ..
TC55257DFL ,32,768 WORD-8 BIT STATIC RAMapplications where high speed, lowpower and battery backup are required. The TC55257DPL/DFL/DFTL/DT ..
TC9171P ,High Speed PLL with Built-In PrescalerI1L.--.7i'i71'r)'i'rl'7 109HIBA.o HIGH SPEED PLL NITH BUILT IN PRESCALERELECTEQNICE1The T"09171p/72 ..
TC9172AP ,HIGH SPEED PLL WITH BUILT-IN PRESCALERTOSHIBA TC9172AP,TC9227,28PT(‘Q177AP T(‘Q777P T(‘Q77RPTC9172AP, TC9227P and TC9228P are high-speed ..
TC9176P ,HIGH EFFICIENCY ELECTRONIC VOLUMEELECTRICAL CHARACTERISTICS (Unless otherwise specified,CHARACTERISTI'C_ TESTS.YMBOL" CIR-.CUIT1lss- ..
TC9176P. ,HIGH EFFICIENCY ELECTRONIC VOLUMEELECTRICAL CHARACTERISTICS (Unless otherwise specified,CHARACTERISTI'C_ TESTS.YMBOL" CIR-.CUIT1lss- ..
TC9176P.. ,HIGH EFFICIENCY ELECTRONIC VOLUMEa..."...V m...“_,)i/,il)),frrli,1iit1" ('lj)?,i,"i)l,r,!),,l),,li,,- ELECTRONIC rri'i"iic 18234,. . ..
TC9177P ,High Efficiency Electronic VolumeELECTRICAL CHARACTERISTICS (Unless otherwise specified,CHARACTERISTI'C_ TESTS.YMBOL" CIR-.CUIT1lss- ..
TC55257DFI-70L-TC55257DFI85L-TC55257DFI-85L-TC55257DFTI-70L-TC55257DPI-70L-TC55257DPI-85L
32,768 WORD x 8 BIT STATIC RAM
TOSHIBA TC55257DPl/DFI/DFTI/DTRI-70L,-85L
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
32,768-WORD BY 8-BIT STATIC RAM
DESCRIPTION
The TC55257DPI/DFI/DFTI/DTRI is a 262,144-bit static random access memory (SRAM) organized as 32,768
words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a
single 5 V , 10% power supply. Advanced circuit technology provides both high speed and low power at an
operating current of 5 mA/MHz (typ) and a minimum cycle timesf 70 ns. It is automatically placed in low-
power lime at 0.3 PA standby current (typ) when chip enable (CE) is asserted high. Thee_are two control
inputs. CE is used to select the device and for data retention control, and output enable (OE) provides; fast
memory access. This device is well suited to various microprocessor system apphcations where high speed, low
ower and batter hrfa; are required. And, with a guaranteed operating range of - 40° to 85°C, the
C55257DPI/DF DFTI/D RI can be used in environments exhibiting extreme tem erature conditions. The
TC55257DPI/DFI/DFTI/DTRI is available in a plastic 28-pin dual-in-line package (D ), plastic 28-pin small-
outline package (SOP) and normal and reverse pinout plastic 28-pin thin-small-outline package (TSOP).
F EATU R ES
0 Low-power dissipation 0 Access Times (maximum):
Operating: 27.5 mW/MHz (typical) TC55257DPl/DFl/DFTl/DTRl
0 Standby Eurrent of 2 PA (maximum) at -70L -85L
Ta = 25° .
0 Single power supply voltage) 5 V i‘ 10% Iccess Time 70 m 85 ns
0 Power down features using CE. CE Access Time 70 ns 85 ns
0 Data retention supply voltage of 2 to 5.5 V E Access Time 35 ns 45 ns
0 Direct TTL compatibility for all inputs and o Packages:
outputs - - -
It Wide operating temperature range of - 40° to J'/Jifif'd'/tfjif7ggl
85°C TSOP I 28-P-0.55 (DFTI)
TSOP I 28-P-0.55A (DTRI)
(Weight: 4.42 g typ)
(Weight: 0.79 g typ)
(Weight: 0.22 g typ)
(Weight: 0.22 g typ)
PIN ASSIGNM ENT (TOP VIEW)
o 28 PIN DIP & SOP o 28 PIN TSOP (Normal pinout) (Reverse pinout)
A14E 1 28 3 van lllllllllNlllllllllllll flllllllhlMlllllllll
A12 E 2 27 J R/W 14 1 1 14
A7 E 3 26 il A13
A6 E 4 25 3 A8
A5 E 5 24 1 A9
A4 E 6 23 3&1
A3 E 7 22 [l OE
A2 E 8 21 [lA_10
A1 E 9 20 l CE
A0 E 10 19 l I/O8
1/01 L 11 18 31/07
l/Oil E 12 17 31/05
1/03 L 13 16 J 1/05
GNDE‘I4 1511/04 15 28 28 15
llllllllllllllllllllllllll [lllllllllllllllllllllllllll
PIN NAMES
A0 to A14 Addresslnput PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14
'e Read/Write Control PIN NAME E A11 A9 A8 A13 R/W Vor, A14 A12 A7 As As A4 As
C5 OutputEnable PIN NO. 15 16 17 18 19 20 21 22 23 24 25 26 27 28
CE ChipEnable PIN NAME A A A l/OI 1/02 1/03 GND 1/04 1/05 I/O6 I/O? l/O8 E A
1/01 to I/O8 Data Input/Output 2 1 o IO
VDD Power (+ 5V)
GND Ground
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operatin ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and con itions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1998-08-05 1/11
TOSHIBA TC55257DPl/DFI/DFTI/DTRI-70L,-85L
BLOCK DIAGRAM
A-4:) VDD
A5 m m
A6 vs n: m _ GND
A7 I' 5 E E MEMORY CELL
23 gig f:htii, ARRAY
2:; L... L... 512 x 64 x 8
A13 t I t 2 (262144)
- 64 -
l/OI 5' SENSE AMP
E COLUMN ADDRESS
' O DECODER
- < COLUMN ADDRESS
g g n: REGISTER
|/08 8 'il
_I LLI
A0 A1A2 A3 A4A10
OPERATION MODE
MODE E E W l/OI to |/08 POWER
Read L L H DOUT IDDO
Write L X L Dm IDDO
Outputs Disabled L H H High-Z IDDO
Standby H x x High-Z IDDS
Note: x = don't care. H = logic high. L = logiclow.
ABSOLUTE MAXIMUM VALUES
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage - 0.3 to 7.0 V
" Input Voltage - th3* to 7.0 V
VI/O Input/Output Voltage - 0.5* to VDD + 0.5 V
Po Power Dissipation 1.0/0.6 ** W
Tsolder Soldering Temperature (10s) 260 "C
Tstrg Storage Temperature - 55 to 150 "C
Topr Operating Temperature - 40 to 85 ''C
* - 3.0 V when measured at a pulse width of 50 ns
** SOP
1998-08-05 2/11
TOSHIBA TC55257DPl/DFI/DFTI/DTRI-70L,-85L
DC RECOMMENDED OPEVALUE CONDITIONS (Ta = - 40° to 85°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDD Power Supply Voltage 4.5 5.0 5.5
VIH Input High Voltage 2.4 - VDD + 0.3 V
VIL Input Low Voltage - 0.3* - 0.6
VDH Data Retention Supply Voltage 2.0 - 5.5
* - 3.0 V when measured at a pulse width of 50 ns
DC CHARACTERISTICS (Ta = - 40° to 85°C,VDD = 5V , 10%)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
In. Input Leakage Current VIN = 0V to VDD - - i 1.0 #A
IOH Output High Current V0H = 2.4V - 1.0 - - mA
IOL Output Low Current VOL = 0.4 V 4.0 - - mA
C"E--NhHorR/w--ihLoro-E--ihH - - +
lLo Output Leakage Current VOUT = 0V to VDD - 1.0 ,A
E = VIL t l = 1 s - 10 -
brro1 W = VIH, IOUT = 0 mA cycle [1 mA
Other Inputs = VIHNlL tcycle = min - - 70
Operating Current -
CE = 0.2V tcycle = Ire; - 5 -
IDDOZ MN = VDD - 0.2 V, IOUT = 0 mA mA
Other Inputs = VDD - 0.2 V, 0.2V tcycle = min - - 60
|DDS1 E = " - - 3 mA
I Standby Current E = VDD - 0.2V Ta = - 40° to 85°C - - 30
DDS2 VDD = 2.0 to 5.5V Ta = 25°C - 0.3 2 #A
CAPACITANCE (Ta = 25°C,f = 1 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
CIN Input Capacitance VIN = GND 10 pF
COUT Output Capacitance VOUT = GND 10 pF
Note: This parameter is periodically sampled and is not 100% tested.
1998-08-05 3/11
TOSHIBA TC55257DPl/DFI/DFTI/DTRI-70L,-85L
AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = - 40° to 85°C, VDD = 5 V i 10%)
READ CYCLE
TC55257DPl/DFl/DFTl/DTRl
SYMBOL PARAMETER -70L -85L UNIT
MIN MAX MIN MAX
tRC Read Cycle Time 70 - 85 -
tACC Address Access Time - 70 - 85
tco Chip Enable Access Time - 70 - 85
toe Output Enable Access Time - 35 - 45
tcos Chip Enable Low to Output Active 5 - 5 - ns
tOEE Output Enable Low to Output Active 0 - 0 -
too Chip Enable High to Output High-Z - 25 - 30
tooo Output Enable High to Output High-Z - 25 - 30
tOH Output Data Hold Time 10 - 10 -
WRITE CYCLE
TC55257DPL/DFUDFTL/DTRL
SYMBOL PARAMETER -70L -85L UNIT
MIN MAX MIN MAX
twc Write Cycle Time 70 - 85 -
twp Write Pulse Width 50 - 60 -
tcw Chip Enable to End of Write 60 - 65 -
tAs Address Setup Time 0 - O -
tWR Write Recovery Time 0 - 0 - ns
toow R/W Low to Output High-Z - 25 - 3O
tOEW R/W High to Output Active 0 - 0 -
tos Data Setup Time 30 - 4O -
tDH Data Hold Time 0 - 0 -
AC TEST CONDITIONS
Output load: 100 pF + one TTL gate
Input pulse level: 0.4 V, 2.6 V
Timing measurements: 1.5 V
ReferenChip Enable level: 1.5 V
tlt, tF: 5 ns
1998-08-05 4/11
TOSHIBA TC55257DPl/DFI/DFTI/DTRI-70L,-85L
TIMING DIAGRAMS
ADDRESS X
tAcc - t0H
- \\ tco
JOEE l tooo
DOUT VALID DATA OUT
INDETERMINATE
WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4)
ADDRESS
DOUT See Note 2) (See Note 3)
DIN See Note 5) VALID DATA IN See Note 5)
TOSHIBA TC55257DPl/DFI/DFTI/DTRI-70L,-85L
WRITE CYCLE 2 LLCTif CONTROLLED) (See Note 4)
ADDRESS
tDs tDH
DIN See Note 5) VALID DATA IN See Note 5)
Note: (1) W remains HIGH for the read cycle.
(2) If 5E- goes LOW coincident with or after R/W goes LOW, the outputs will remain at high
impedance.
(3) If C-E' goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at
high impedance.
(4) If COE is HIGH during the write cycle, the outputs will remain at high impedance.
(5) Because I/O signals may be in the output state at this time, input signals of reverse
polarity must not be applied.
1998-08-05 6/11
TOSHIBA
TC55257DPl/DFl/DFTI/DTRI-70L,-85L
DATA RETENTION CHARACTERISTICS (Ta = - 40° to 85°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDH Data Retention Supply Voltage 2.0 - 5.5 V
Vor, = 3.0V - - 15* ps/k
IDDSZ Standby Current
Vor, = 5.5V - - 30 #A
tCDR Chip Deselect to Data Retention Mode Time 0 - -
tR Recovery Time thSee Note) - - ns
Note: Read cycle time.
UECONTROLLED DATA RETENTION MODE
DATA RETENTION MODE
* 2PA (max) at Ta = - 40°to 40°C
(See Note)
(See Note)
VDD - 0.2V
Note: When C-E is operating at the VIH level (2.4 V), the standby current is given by IDDSl during
the transition of VDD from 4.5 to 2.6 V.
1998-08-05 7/11
TOSHIBA TC55257DPl/DFI/DFTI/DTRI-70L,-85L
PACKAGE DIMENSIONS (DIP28-P-600-2.54)
Units in mm
0-25 3a 1
310i02
Weight: 4.42g (typ)
1998-08-05 8/11
TOSHIBA TC55257DPl/DFI/DFTI/DTRI-70L,-85L
PACKAGE DIMENSIONS (SOP28-P-450-1.27)
'iiccpppcccpcwii'
EH [ICI])])])))), m
8 8:0 2
11.8i0.3
0.43:0.1 EEEE-IIE
0.995TYP
[1.C27]]
I 19.0MAX ,
l 18.5:02 _.
Chl. x
l; : [ijt-g:
"o.1 ~13.
.4- $5,
Weight: 0.799 (typ)
Units in mm
(450mil)
i l 1.0102
1998-08-05 9/11
TOSHIBA
PACKAGE DIMENSIONS (TSOP I 28-P-0.55)
TC55257DPl/DFl/DFTI/DTRI-70L,-85L
m C) El =1,
tat n: I
CE I]: n
CE III:
ii lg. "
'jig'' L
= 'IIZI
14 = h 1:
= 11.Wc0.2 ' E
N 13.4:02 = ti
Weight: 0.229 (typ)
Units in mm
8.2MAX
0.15 1.6.05
1998-08-05 10/11
TOSHIBA TC55257DPl/DFI/DFTI/DTRI-70L,-85L
PACKAGE DIMENSIONS (TSOP I 28-P-0.55A)
Units in mm
28 an: l (x;
C) 1m CD
iii “I
L It.8:t:0.2 E 1 Od:0.1 A 0.110.05
A V 13.4K0.2 _ tii 1.2MAx
" ci = A
fl vu, 5;ng
o.5¢o.1
Weight: 0.22g (typ)
1998-08-05 11/11
www.ic-phoenix.com
.
