TC514400ASJ-60 ,60 ns, 4-bit generation dynamic RAM1,048,576 WORD x4 BIT DYNAMIC RAM * This is advanced information and specifiea-
tions are subjec ..
TC514400ASJ-70 ,70 ns, 4-bit generation dynamic RAMfeatures include single power supply of 5Vi10% tolerance, direct
interfacing capability with high ..
TC514400ASJL-70 ,70 ns, 4-bit generation dynamic RAMfeatures include single power supply of 5Vi10% tolerance, direct
interfacing capability with high ..
TC514400ASJL-70 ,70 ns, 4-bit generation dynamic RAM1,048,576 WORD x4 BIT DYNAMIC RAM PRELIMINARY
DESCRIPTION
The TC514400APL/AJvASJLAZL is the n ..
TC514400AZ-60 ,60 ns, 4-bit generation dynamic RAMFEATURES
. 1,048,576 word by 4 bit organization 0 Low Power .
. Fast access time and cycle time 6 ..
TC514400AZ-80 ,80 ns, 4-bit generation dynamic RAMFEATURES
0 1,048,576 word by 4 bit organization
. Fast access time and cycle time
TC514400AP ..
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TC7WBL125FK ,Bus SwitchFeatures • Operating voltage: V = 2~3.6 V CC• High speed operation: t = 0.25 ns (max) @3 V pd• Ultr ..
TC514400ASJ-60-TC514400AZ-60
60 ns, 4-bit generation dynamic RAM
1,048,576 WORD x4 BIT DYNAMIC RAM * This is advanced information and speeifica-
tions are subject to change without notice.
DESCRIPTION
The TC514400AP/AJ/ASJ/AZ is the new generation dynamic RAM organized 1,048,576 words by 4
bits. The TC,514400AP/AJ/ASJ/AT utilizes TOSHiBA's CMOS Silicon gate process technology as well
as advanced circuit techniques to provide wide operating margins, both internally and to the system
user. Multiplexed address inputs permit the TC614400AP/AJ/ASJ/AZ to be packaged in a standard 20
pin plasti" DIP, 26/20 pin plastic SOJ(300/350mi1) and 20 pin plastic ZIP. The package size provides
high system bit densities and is compatible with widely available automated testing and insertion
equipment. System oriented features include single power supply of 5V:h10% tolerance, direct
interfacing capability with high performance logic families such as Schottky TTL.
FEATURES
. 1,048,576 word by 4 bit organization 0 Low Power .
0 Fast access time and cycle time 660mW MAX. Operating
(TC5 14400AP/AJ/ASJ/AZ - 60)
TC514400AP/AJ/ASJ/AZ ~60 5.5mW MAX. Standby
IRAC 'ThGAccessTsme 60ns . Outputs unlatched at cycle end allows two-
taa Column Address dimensional chip selection
Access Trme 30ns O Iiad-Modify-Write, CRS before RM refresh,
chc mAccess Time 20ns 11Tdj-only refresh, Hidden refresh, Fast Page
' Mode and Test Mode capability
:Z: F2): :agngode 110ns . All inputs and outputs 'ITL compatible
Cycle Time 45ns . 1024 refresh cycles/16ms
. Package TC514400AP '. D1P20-P-300C
q T0514400AJ : SOJ26-P-350
. Smgle iooy.er.supply of 5Vi10% TC514400ASJ : SOJ26-P.300A
with a bullt-lll Vm; generator TC514400AZ : ZIP20-P-400A
PIN NAMES
A0~A9 Address Inputs t5t" Output Enable
P7G Row Address Strobe l/Ol-l/Oil Data input/Output
C s Column Address Strobe Vcc Power(+ SV)
WRITE Read/Write Input Vss Ground
PIN CONNECTION (TOP VIEW) JiL2uC..p_r./..g.LLV.Llll
um um v0: voa
9mm DIP Plum SO) Plasuc ZIP
", ...4
USE; IA, era l
v .::I [4: U04 WW!
ms; 'r-i, CC' POI om.
-.. r-- u. not
W33“: E2: WRITE m mutton
A0 II} 9-9: A9 cowuu comm
Ta", " At A0 moms Ia') DICDOII
AU}. f" At Iunmuo) .
""'' Al. A3 mus! AMP
Vcc.‘5.' Ciif A4 Mo- mm" v06”:
Tit .;= A3 CONYIOLLKI
A5J1. r anzb
.-. " A6 A40. “
A7”: rid A8 A50. 1mm
-_. “o. couumuo) "
A70. u
ww a Mmou
2:2: moms Alt lil, AMAT
Iwm no) 'll 1014 u mu:
NO.‘ ClOCK
EMO--- umlumn sumuu IN
cmuuox
A-31 1
TC51 4400AP/AJ IASJ /AZ-60
ABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING UNITS NOTES
Input Voltage Vm - _ V 1
Output Voltage VOUT - _ V 1
Power Supply Voltage Vcc - l-r V 1
Operating Temperature Tom 0~70 'C 1
Storage Temperature Tsro - 55-150 'C 1
Soldering Temperature‘Time Tsouso 260 F 10 'trset 1
Power Dissipation Po ' 700 mW 1
Short Circuit Output Current lout 50 mA 1
RECOMMENDED DC OPERATING CONDITIONS (Ta=0--7ty'c)
SYMBOL PARAMETER MIN. TYP.
Vcc Supply Voltage 4.5 5.0
V." Input High Voltage 2.4 -
" Input Low Voltage -
TC51 4400AP/AJ IASJ/AZ-60
DC ELECTRICAL CHARACTERISTICS (Vcc = 5V i 10%, Ta = 0~70°c)
SYMBOL
PARAMETER
OPERATING CURRENT
Average Power Supply Operating Current
tras, 676. Address Cycling: lac=inc MIN.)
TC514400AP/AJ/
ASJ/AZ-GO
STANDBY CURRENT
Power Supply Standby Current
(m:C7§= Vm)
TOT' ONLY REFRESH CURRENT
Average Power Supply Current, m Only Mode
(m Cycling, mam: tru:=tec MIN.)
TC514400AP/AJ/
ASJ/AZ-GO
FAST PAGE MODE CURRENT
Average Power Supply Current, Fast Page Mode
(WAT: VIL, r7G, Address Cycling: tpc=tyc MIN.)
TC514400AP/AJ/
ASJ/AZ-GO
STANDBY CURRENT
Power Supply Standby Current
(HEW: VCC" 0.2V)
EATS BEFORE RT; REFRESH CURRENT
Average Power Supply Current, t7G Before "k7G
Modetli7G, 63 Cycling: tracratRt: MIN.)
TCS I 4400AP/AJ/
ASJ/A 2-60
ll (L)
INPUT LEAKAGE CURRENT
Input Leakage Current, any input
(0V5 VINS 6.5V, All Other Pins Not Under Test..-. 0V)
lo (L)
OUTPUT LEAKAGE CURRENT
(Dow is disabled, 0VSVourSS.5V)
OUTPUT LEVEL
Output "H" Level Volta9eilouv= -5mA)
OUTPUT LEVEL
Output "L" Level VoWage0our--il.2mA)
TC514400AP/AJ/ASJ/AZ-60
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Vcc=5V.t 10%, Ta=0--70''c)(Notes 6, 7, 8)
TC514400AP/AJIASJ/AZ-60
SYMBOL PARAMETER UNIT NOTES
MIN. MAX.
tec Random Read or Write Cycle Time 110 - ns
ttttaw Read-Modify-Write Cycle Time 165 - ns
tpc Fast Page Mode Cycle Time 45 - ns
tpRMw Fast Page Mode Read-Modify-Write Cycle Time 100 - ns
tug Access Time from m - 60 ns 'li,"
tag Access Time from ER - 20 ns 9,14
tAA Access Time from Column Address - 30 ns 9,15
tcpA Access Time from EA? Precharge - 40 ns 9
1a; m to output in Low-Z 0 - ns 9
torr Output Buffer Turn-off Delay 0 20 ns 10
tt Transition Time(Rise and Fall) 3 50 ns 8
(p m Precharge Time 40 - ns
teas CAT Pulse Width 60 10,000 ns
tgAsp m Pulse Width(Fast Page Mode) 60 200,000 ns
tas" m Hold Time 20 - ns
1mm, m Hold Time From m Precharge(Fast Page Mode) 40 - ns
tcsH CAT Hold Time 60 - M
tcas CAT Pulse Width 20 10.000 ns
taco RAT to m Delay Time 20 40 ns 14
tRAD m to Column Address Delay Time 15 30 ns 15
tcnp m to m Precharge Time 5 - ns
tcp GE Precharge Time 10 - ns
tASR Row Address Set-Up Time 0 - ns
tRAH Row Address Hold Time 10 - ns
tasc Column Address Set-Up Time 0 - ns
tau Column Address Hold Time 15 - ns
trtac Column Address to m Lead Time 30 - ns
tact Read Command Set-Up Time 0 - ns
tncH Read Command Hold Time 0 - ns 11
tun” Read Command Hold Time referenced to m 0 - ns 11
two, Write Command Hold Time 10 - ns
TC51 4400AP/AJ IASJ /AZ-60
ELECTRICAL CHARACTERISTICS AND RECOMMENDED
(Continued)
AC OPERATING CONDITIONS
TC514400AP/AJIASJ/AZ-60
SYMBOL PARAMETER UNITS NOTES
MIN. MAX.
twp Write Command Pulse Width 10 - ns
terse Write Command to lih7 Lead Time 20 - ns
tcm Write Command to (23 Lead Time 20 - ns
tos Data Set-Up Time 0 - ns 12
ton Data Hold Time IS - ns 12
um Refresh Period ... 16 ms
twcs Write Command Set-Up Time 0 - ns 13
tcwo CM to WW Delay Time 50 - ns 13
tovo FR to WWW Delay Time 90 - ns 13
tawo Column Address to WW Delay Time 60 - ns 13
toswo tAs Precharge to WT? Delay Time 70 - ns 13
tcse tyrs Set-Up Time 5 - m
(CA3 before k7G Cycle)
tom EB-Hold Time 15 - M
(as before m Cycle)
[Rpc EAS to ths- Precharge Time I 0 - ns
ttpr ttWS" Precharge Timum before R73 Counter Test 30 - ns
Cycle)
tnoH FAT; Hold Time referenced to 5? 10 - ns
tora (TE A(cess Time - 20 ns
tom tTE to Data Delay 20 - ns
toez Output buffer turn off Delay Time irorn 6? 0 20 ns
tom ce Command Hold Time 20 - ns
twrt Write Command Set-Up Time (Test Mode In) 10 - ns
\WTH Write Command Hold Time (Test'Mode In) 10 - ns
tpr WRWE to 't7G Precharge Time (as before m Cycle) 10 - ns
twnH WR'ITTE lo 'ar Hold Time (m before W Cycle) 10 - ns
TC51 4400AP/AJ IASJ /AZ-60
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS IN THE
TEST MODE
TC5 1 MOOAP/AJ/ASJ/AZ-SIO
SYMBOL PARAMETER UNIT NOTES
MIN. MAX.
tn: Random Read or Write Cycle Time 115 - ns
tpc Fast-Page Mode Cycle Time 50 - ns
tug Access Time from m - 65 ns ?'514
tom Access Time from EM - 25 ns 9,14
(ta Access Time from Column Address - 35 n5 9,15
tora Access Time from m Precharge - 45 ns 9
truss W Pulse Width 65 10,000 ns
ms: m Pulse Width(Fast Page Mode) 65 200,000 ns
insu Ei'G Hold Time 25 - ns
tcsn W Hold Time 65 - ns
tRHcp m Hoid Time From m Precharge(Fast Page Mode) 45 - ns
tcas 65 Pulse Width 25 10,000 ns
tttAt. Column Address to m Lead Time 35 - ns
CAPACITANCE (Vcc = 5V t 10%, f = 1MHz, Ta = 0--70oc)
SYMBOL PARAMETER MIN. MAX. UNIT
Cn Input CapatitaneeiA0-A9) - 5 PF
Ca Input capatitantetl7T, E73. WENT, UE) - 7 pi
Co Input/Output Capatitantetl/01-l/04) - 7 pF
TC51 44OOAP/AJ IASJ/AZ-BO
NOTES:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device.
All voltages are referenced to Vss.
ICCI. Icc3, Icc4, lay, depend on cycle rate.
1cm, ICC4 depend on output loading. Specified values are obtained with the output open.
Column address can be changed once or less while RM---vu, and CKS=VHL
An initial pause of 200ps is required after power-up followed by 8 RAS only refresh cycles before
proper device operation is achieved. In case of using internal refresh counter, a minimum of 8
m before RAS refresh cycles instead of 8 RAS only refresh cycles are required.
7. AC measurements assume tT=5ns.
& Vm (min.) and VIL(max.) are reference levels for measuring timing of input signals. Also,
transition times are measured between V111 and VIL-
9. Measured with a load equivalent to 2 'ITL loads and 100pF.
10. torv(max.)and tor:z(max.)define the time at which the output achieves the open circuit condition
and are not referenced to output voltage levels.
11. Either tile“ or tmm must be satisfied for a read cycle.
12. These parameters are referenced to CM leading edge in early write cycles and to WRITE leading
edge in Read-Modify-Write cycles.
13. twcs, ERWD, tcwn, tAWD and tcpwn are not restrictive operating parameters. They are included
in the data sheet as electrical characteristics only. If twcs2-etwCs(min0, the cycle is an early
write cycle and the data out pin will remain open circuit(high impedance)through the entire cycle;
If trtwo2.titwio(rnin0, tcwrf2tcwio(min0, tAwoi2tAwo(min.) and tcPwrri2tcPmo(min00?ast
Page Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from
the selected cell: If neither of the above sets of conditions is satisfied, the condition of the data
out (at access time) is indeterminate.
14. Operation within the tRCD(max.)limit insures that “me (max.) can be met.
tecD(max.)is specified as a reference point only: If tItCD is greater than the specified tncp(max.)
limit, then access time is controlled by tCAC.
15. Operation within the tRADimax.)limit insures that tRAC (max.) can be met.
htAn(max.) is specified as a reference point only: If tltAD is greater than the specified tRAD(max.)
limit, then access time is controlled by tAA.
A-31 7
TC51 4400AP/AJ/ASJ /AZ-60
READ CYCLE
Ihr, -
Ihr, -
AO~A9 COLUMN
VII. -
POI VoH---
DATA - OUT
~|/O4 VOL -
Eg.. "H" or "L"
TC51 4400AP/AJ IASJ /AZ-60
WRITE CYCLE {EARLY WRITE!
A0~A9 COLUMN
l/O1 V H
~|/04 " DATA - IN
.: "H'' or "L"
TC51 4400AP/AJ IASJ /AZ-60
WRITE CYCLE (W CONTROLLED WRITE)
m Ihr,
A0 ~A9
, tctw teco - _
" - ' S"
" - hug 'iss.
II? -.Cirii'tiiiiiiiiXEivrXiiiie,',
1hu "r])'),',';,'',!)'',", ,,'ifiij''ifj: C
tht ciiffiitiitifitiiiiiiiieiiiiiiiiiij?
‘ _ tos
1/01 '" .
‘4 4 VIL -
t tits,
COLUMN
'ril?f,)
k twi, "sri/ir/sv/y/trs/n/yo/a,,,
DATA-IN "a//(/////////)//i/it/5/f/// A,
'bE : "H" or "L"
TC51 4400AP/AJ IASJ /AZ-60
READ-MODIFY-WRITE CYCLE
tase tRAH tasc
A0-A9 ROW COLUMN
VI/OH--
l/O1 DATA-IN
~IIO4 VUOL -
Ea,. "H" or "c"
TC51 4400AP/AJ IASJ /AZ-60
FAST PAGE MODE READ CYCLE
1/01 v0H --
ga.. "H'' or "L"
TC51 4400AP/AJ IASJ /AZ-60
FAST PAGE MODE WRITE CYCLE
VIH ---
VI]. -
Vii. W“
I/OI N/m
--l/04
Eiir. "H" or "L"
TC51 4400AP/AJ IASJ /AZ-60
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
A0-A9 IH
AM-. VIIOH -
l/Od ' _
ET. "H'' or "L"
TC51 4400AP/AJ IASJ IAZ-GO
trt7ig ONLY REFRESH CYCLE
ATG 31:: I, tttAS VT ttt \___
TAT; 3:: j'"' 7 7U
A(rsA9 :::* 'ii-v-j-': (iiiiiiiiiiiiiiiiiiiiitEiiiiiiit%iiiiE)
Note: WRITE, UE="H" or "L" .1 "H" or "U'
m Z::‘:_/‘t R K? tmst; 7L RP L_...-
CA5 " - / , 'gtss',
twnp twttH
m::://// Ady2ff. 'iii?iififj, /////
l/OI - 'ae-----'""-'"'""
l/O4 ( OPEN
VOL ---
Note: Uff, A0--A9..-."H" or "L" EEr "H'' or "L'
TC51 4400AP/AJ IASJ /AZ-60
HIDDEN REFRESH CYCLE (READ)
m " ..,...-...r-a(..", 1/ 'i,--:,.,.::'---,)''''' 'ic.,
m z: I-:,)'''''' tRAD 'Is., ttmt j/i'-"-"-'--'------ tCRP
Th7lTrrE C'T"iitCii,,'(t')','" taa 'Rit,Ctfji?' 'ttjiiiiiiiiiiitiiiiEiit
Ir. t,,,fiiiiit-: ,,tioEZ F---
(fyCft : "H" or "L"
TC51 4400AP/AJ IASJ /AZ-60
HIDDEN REEFRESH CYCLE (WRITE)
m 3:: Tf-h teat / tRP ass,Lli1.cy tttp 'su,
~- _.'.',].' 17/ "‘12; 'ts, '
trt' 't WWW
'eu, :1: : >6 DATA WW /////////// '///i//ffj/f/g///h///fi/i//d//7tt/i///,
TC51 44OOAP/AJ IASJ /AZ-60
m BEFORE RM REFRESH COUNTER TEST CYCLE
A0-A9 COLUMN
READ CYCLE
1/01 Vow
~|/04 V DATA-OUT
WRITE CYCLE
_..__ VIH
POI " -
*4/04 DATA . IN
READ-MODIFY-WRITE CYCLE ttwo
1/01 I/v-
~|104 V DATA-IN
DATA - OUT
7/4: "H" or "L"
TC51 4400AP/AJ IASJ/AZ-60
WRITE, OAS BEFORE RA§ REFRESH CYCLE
IRAs }._L_.
VIH - a 7
RAS " --- 's, L,
Ity, L631; tgun
- " - / l 6t ',iiii,ifliifiii,f;
CAS " - _L sy,f,,i,tt,' titii))i,
twrs Lvglti
"i/Tart'' gym" //////////////////////////////////////
l/OI l/OH -
l/04 VOL - i
Note: W, A0--A9="H'' or "L" .2 "H" or "U'
TC51 4400AP/AJ /ASJ /AZ-60
TEST MODE
The TC5144OOAP/AJ/ASJ/AZ is the RAM organized 1,048,576 words by 4 bits, it is internally
organized 524,288 words by 8 bits. In "Test Mode", data are written into 8 sectors in parallel and
retrieved the same way. Ath: is not used. If, upon reading, two bits on one I/O pin are equal (all"I"s or
"O"s), the I/O pin indicates a"I".
If they were not equal, the I/O pin would indicate a"0". Fig.1 shows the block diagram of
TC5i4400kP/AJ/ASJ/AZ. In "Test Mode", the 1MX4 DRAM can be tested as if it were a 512KX4
"WRITE, Chg Before RTE Refresh Cycle puts the device into"Test Mode". And'CEg Before ITM"
Refresh Cycle" or “73 Only Refresh Cycle"pues it back into"Normal Mode". In the Test Mode,
"WRITE, m Before R73 Refresh Cyele"Performs the refresh operation with the internal refresh
address counter. The "Test Mode"function reduces test times(1/2 in case of N test pattern).
TC51 4400AP/AJ /ASJ /AZ-60
BLOCK DIAGRAM IN THE TEST MODE
------o
-atog-.--. A 4 'les''-'-?-')
Normal 512K block cED:r---o
uou --
C Aoc B
Test - oss?------- S12K block Test
E --)) D tls,,, I
------o CiNormal
--'---""'i-
ADC C Normal
Normal --osdr------ 512K block Cc-EJs'.'.---?,,'; I
02 tb-------- E Test
ll e-dA. -
o Aoc D
Test _ "s" 512K block 'i Test
t5 fl) D 1'ms,, I
--------<, Normal
-----o
_.-....-...:,
Aoc E k 0clNormal
Normal -"sd?--- 512K block EY-------), l
I/O3 Cy------ E Test
Ny Aoc F
Test _ 512K block fix Test
K” r ID-------;:':':';:,
-------o lNormaI
------o
Nc G \ oclNOrmal
Normal -'sf?---- 512K block cEDy------o,t, I
I/O4 Ch-------- Ti- Test
*0; Aoc H
Test b 512K block " Test
"s' n )rD----ti'iils
-----o iNormal
-------o
Fig. 1
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