TC5090AP. ,CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHICAPPLICATIONS:
. Various control instruments (for temperature,
humidity, pressure, etc.)
. Home e ..
TC5092AP ,CMOS Digital Integrated Circuit Silicon MonolithicGENERAL DESCRIPTION I
The TC5092AP is an integration 13-bit A/D converter
of high precision and ..
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TCSO93AP 8 BIT ANALOG TO DIGITAL CONVER ..
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TC514100AP-80 ,80 ns, 1-bit generation dynamic RAMFEATURES
. 4,194,304 word by lbit organization
. Fast access time and cycle time
TCS 1 AIO ..
TC514100ASJ-60 ,60 ns, 1-bit generation dynamic RAMFEATURES
. 4,194,304 word by 1bit organization . Low Power
0 Fast access Lime and cycle time ..
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TC7W04FK ,3 INVERTERS
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TC7W08FU ,DUAL 2-INPUT AND GATETC7W08F/FU/FKT(‘7WDRF "rf'mfunmul "rf'mhm$trit-‘vv. 'IVVI v,VVII‘The TC7WO8 is a high speed CZMOS 2 ..
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TC5090AP-TC5090AP.
CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
cNos DIGITAL INTEGRATED CIRCUIT
SILICON MONOUTHm
TCS©9©AP
T05090AP PENTAPHASIC INTEGRATION 8-BIT A/D CONVERTER
The TC5090AP is a pentaphase integration 8-bit A/D
converter of high precision and low power consumption,
which is mounted in a compact 16-pin standard package.
The 8-bit output data can be taken out in the form of
tine-shared higher order 4 bits and lower order 4 bits
on four T-state data outputs.
This output system is designed specifically
considering interface to 4-bit CPU.
The features of low power consumption and compact
outline are applicable to battery-driven small-sized
instruments.
FEATURES:
. High precision : i1 LSB MAX. VDD=5V
. Low power consumption: 10mW(Typ.) @(fOSC=lMHZ)
. Single power supply : VDD=Sil.SV
. High-speed conversion: 2mS(Max.) @fosc=l.5MHz
J Reference clock oscillation circuit contained
(CR oscillation)
. 3-state output with output latch
. TTL/CMOS compatible digital Input/Output
. Offset automatic correction
APPLICATIONS:
. Various control instruments (for temperature,
humidity, pressure, etc.)
. Home electric appliances
. Electric wiring apparatuses
Battery-driven instruments
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTIC SYMBOL RATING UNIT
DC Supply Voltage VDD vSS-0.5--VSS+8 V
Input Voltage VIN vSs-0.r-v00+0.5 ll
Output Voltage VOUT 1lsS-0.5--1lDD+0.5 V
DC Input Current IIN tlo mA
Power Dissipation PD 300 mil
Operating Temperature - _ o
Range Topr 40 85 C
Storage Temperature - ' o
Range Tstg 65 150 C
IJ?16(3D16A-P)
PIN ASSIGNMENT
RENB- 1 l6 - Irmo
RSEL-2 15-EOC
ATN---) 14r-DATA 3
STC' _.4 13r- DATA 2
INTI__5 12r-DATA 1
TNTJ-6 ll-DATA o
INTO-c, 1i)--OSCouT
VSS ._ 8 9 - OSCIN
(TOP VIEW)
TC5oggAP
BLOCK DIAGRAM
RI CI Rf
INTIJ\ INIJI llNTo 0SCIN oscoUTSTC EOC
" Inte-
AIN ty- "s-, grator Compactor Oscillation
o-ss . circuit
Offset drift Control clrcult and
. F-- counter
automatlc cor-N
rectingcircuit
Data latch
Multiplexer RSEL
VDD 'h I l 1
Vss - 3-state buffer RENE
_,,i, #5
O 1 2 3
Data Outputs
TIMING DIAGRAM
PHASE I 0 I II I III IV 0 l I
Correction Corrlction
cycle cycle
VINTO ",,,,ww'"
(Integrator Out-)
put Voltage
(Integrator In-, Vss VDD Vss VDD AIN Vss VDD Vss
put Voltage
STC rt,
EOC l I
DATA Old data -)( New data
AIN = VDD
Note)* AIN = 1/2 VDD
AIN = VSS
J_ TC5090AP
FUNCTION OF EACH PIN
PIN PIN
N0 SYMBOL NAME & FUNCTION N0 SYMBOL NAME ' FUNCTION
(Read Enable) 9 050 IN 1/0 for reference clock
Data read signal. oscillation. Clock oscillation
'hatt. can be made by means of external
1 RENB H . :2: :ita 0s3 can be registance. Clock can be sup-
"L": Thepout ut above is at plied from outside through
. p . 10 OSC OUT input of OSC IN.
high impedance.
(Read Select)
Input to select the higher 11 DATAO
order 4 bits or the lower
(3-state Parallel Data Outputs)
2 'RSEL order 4 bits to 4-bit data 12 DATAI Conversion data output.
output. 13 DATA2 The data 0 is LSB, and the
"H": Output of the higher data 3 is MSB.
order 4 bits.
"L": Output of the lower 14 DATA3
order 4 bits.
(Analog Input) (End of Conversion)
3 AIN Analog input terminals. Conversion ending signal.
I t lt . V V EOC goes to "L" level at the
npu vo age range ls DDI ss. fall of STC, and returns to
15 EOC "H" level at the end of
(Start Conversion) conversion.
4 STC Conversion starting signal.
Conversion starts at the fall-
ing edge.
5 INT I (Integrator Input, Integrator
Junction, Integrator Output) (Power Supply)
6 INT J Integrator censists of 5Vil.5V
external resistor RI and 16 ll
7 INT 0 external capacitor CI. DD
8 VSS (Ground)
Normally 0V
TCSDBOAP
FUNCTIONAL DESCRIPTION
(1) System Description (Pentaphasic Integration)
The operation of the TCSO90AP
. Power On
is composed of the correction cycle
and the conversion cycle as shown . . .
Inltla. cor- Min. 64 Cor-
in the timing chart. While the rection period rection cycles
power is switched on, the repeti-
tion of correction cycle and con- '
Correction cycle PHASE 0,1
version cycle enables the TC5090AP
at make A/D conversion under the NO
optimum conditions at all times. aarrCfiijliiirct:-v.
. . . YES
The operation flowchart lS shovnin PHASE O,I,
Fig. 1. Conversioncycle II,III,IV
(a) Initial correction period New data
The internal state of this LSI is
reasonably unsettled at the time Fig. 1 Operation Flowchart
when the power is switched on;
therefore, the initial correction cycle is requires before stable
converting operation becomes possible.
The correction cycle automatically corrects conversion error
caused by offset voltage of the integrator or the like, and
is composed of the period (PHASE 0) for which VDD is integrated
and the period (PHASE I) for which Vss is integrated.
Since system correction is performed in steps at the end of
this PHASE I, 64 correction cycles (64 X 102ho TOSC) are
required as the initial correction period. (Tosc denotes
one clock cycle.)
T05090AP
Conversion cycle
If the initial corection cycle period is completed, normal cCmver-
sion becomes possible.
Wen STC input is given, (although the correction cycle in
PHASE 0 or PHASE I is in operation at this time), the correc-
tion operation stops, and the conversion cycle starts.
In other words, even if STC input is given, this LSI performs
the same operation as the correction cycle until PHASE I is
completed; but it does not perform the correction at the time
of completion of PHASE I, and shifts to PHASE II. Therefore,
attention should be given to the fact that PHASE I prior to
PHASE II does not act as correction cycle.
When STC input is given, the LSI integrates analog input in
PHASE III through PHASE I and PHASE II, performing digital
conversion in PHASE Ill. When the LSI completes digital con-
version in PHASE Ill, the output is turned to the new data and
the LSI returns to the correction cycle.
Correction cycle
When the next STC input is given between completion of
arbitrary conversion cycle (at the time of completion of
PHASE IV) and completion of one correction cycle (1024-ToscL
no correction is substantially made. Therefore, in case the
STC input is consecutively given, another STC should be
given after the lapse of one correction cycle at the earliest
from completion of PHASE w.' When the STC input is given
during conversion (while EOC is at "L" level), the STC cannot
be accepted.
_T_C5090AP
Constant of integration
The RI and C1 composing the integrator should be selected
R101 = (0.9 'u2.5)
_to satisfy the following equation.
fOSC [S]
Attention should be paid to the fact that, when the external
R oscillation is used, fosc has i30% variations in regard to
the typ. value in Fig. 5 due to variations in sample and
temperature characteristic.
In other words, if the typ. value in Fig. 5 is denoted by
fR-TYP, the R1 aid C1 should be selected according to the
following equation.
RICI = (1.2 ~1.75) . -GTiGr- [s]
(2) Output Data Mode
TRUTH TABLE
DIGITAL OUTPUTS
- " " ,
RENE ANALOG INPUT DATA 15$: Li) DATA DATA Ish') '=L'i'li' DATA
0 l 2 3 0 l 2 3
L Don't care High Impedance
H < 'LSB L L L L L L L L
H - J-CLSB m %LSB L L L L L L L L
H -l-LSB 'l, , LSB H L L L L L L L
H ............. . Straight Binary
H "rs"-i- LSB m "rs"--] LSB L H H H H H H H
H "FS"-%LSB N "ss''-)-, H H ll H H H H H
H "rs"--) LSB < H H H H H H H ll
Note : V55 = 0V
"FS" ..... Full Scale (VDD)
1 LSB = VDD/256
Ttyitlimlie,
S-bit digital data is output on four data lines after
having been divided into the higher order 4 bits and the lower
order 4 bits. Either the higher order bits or the lower order
bits can be selected by RSEL.
/System Clock Oscillation Circuit
For oscillating reference clock the oscillation circuit is
composed of external resistors as shown in Fig. 2.
OSC OSC OSC OSC
IN OUT IN OUT
Rf External Clock
J1rLfL
Fig.2 clock Supplying Methods
Timings for STC-EOC and E'oc-DATA
o Time (tSE) from the fall of STC l r]
STC to the fall of EOC.
tsE=5Tosc ” f Tosc . tSE tES
o Time (tDE) from the out of DATA
DATA output to the rise of EOC tDE
tDE = éTosc Fig.3 Timing chart of STC/EOC
o Min. time (tES) from the rise of ECG to the accpetance of
another STC.
tEs = 3 Tosc m 5 Tosc
TC5090AP
(5) Timings for STC Input and RSEL/RENB Input
STC signal is taken in synchro-
nously with the internal clock; there-
STC T-I,
fore, if TOSC denotes one clock cycle or l
of OSC terminal, the pulse width of '
tw thold
more than (Z'TOSC) is required.
Either RSEL input or RENB input Fig.4 Timing chart of
is required to be set to "H" level at Control Input
the falling time of STC by reason of internal structure.
Further, the hold time of (TOSC + SOns) or more after the falling
time of STC at least for "H" level time of RSEL or REMB is required.
NOTE l tw> 2 . Tosc, thold > Tosc + 50ns
TC5090AP
RECOMMENDED OPERATING CONDITIONS (VSS= 0V)
ITEM SYMBOL MIN. TYP. MAX. UNIT
Supply Voltage VDD 3.5 5 6.5 V
Input Voltage VIN 0 - VDD V
Integral Resistor RI 0.4 - 2 M0
Integral Capacitor CI Note
Oscillatory Resistance Rf VDD = SV 10 - l. KR
Note: Refer to Fuction Description (1) for determing the values of R1 and cr,
respectively
ELECTRICAL CHARACTERISTICS (VSS= 0V)
SYM- TEST v -li0 c 25 c 85 c
ITEM BOL CONDITIONS DD UNIT
[V] MIN. MAX. MIN. TYP. MAX. MIN. MAX.
. [IOUTI<1uA - -
Input High Voltage VOH VIN=VSS,VDD 5 4.95 4.95 5.00 4.95 V
IOUTI<1uA
Out ut Low Volt e ll l 5 - 0.05 - 0.00 0.05 - 0.05
p ag 0L VIN=Vss,VDD
Output High Current 10H VOH--ti.0V * 5 -1.2 - -1.0 -2.0 - -0.7 -
VIN=Vss,VDD A
VOL=0.4V *
Out ut Low Cu rent I 5 2 4 - 2.0 4 0 - 1 6 -
p r 0L V1N=Vss,VDD
Input High Voltage VIH * 5 2.4 - 2.4 - - 2.4 -
Input Low Voltage VII, * 5 - 0.8 - - 0.8 - 0.8
Output Disable IDH VOH=6.5V * - - - -
Current IDL VOL=0V 6.5 Lr0.5 i10 410.5 15
11H VIH=6.5V * 5 - - + o-5 - +1
Input Current IIL VIL=0V 6. $0.3 tl 10.3 - uA
A l S 'tch Off- I =6.5V
na og W1 IOFF 1H 6.5 - 10.3 - s10-5 i0.3 - KI
Leak Current VIL=OV
Operating Con- IDD fosc= 1 MHZ 5 - - - 2.0 3 - - mA
sumption Current (opr)
* Applicable to digital input/output. Not applicable to analog input/output and
OSCIN/OSCOUT.
TC5090AP
.SWITCHING CHARACTERISTICS (VDD= 5V, VSS= 0V, Ta-- 25°C, CL= 50 pF)
ITEM SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Output Rise Time tTLH - 50 100
Output Fall Time tTHL - 40 100
(Low-High) 1tepaga- tpLH - 180 400
tion Delay Time RSEL("L"+"H")-DATA OUT
(High-Low) Propaga- t HL _ 150 400
tion Delay Time p
$233522; Ir/ey" tpLH - 380 700
(Hi h_Low)yP oma _ RSEL("H"-r"L")-DATA OUT
.g r.p ga LpHL - 300 700 ns
tlon Delay Time
Output Enable Time t3; - 80 250
tl, RENB-DATA OUT
Output Disable Time tHg - 280 500
Max. Clock Frequency fMAX¢ OSC Input 1.5 3.0 - MHz
Min. Clock Frequency fMIN¢ OSC Input - - 100 kHz
Input Capacity CIN Digital Inputs - 4 - pF
Analog Input Capacity CIN - 7 - pF
T-State Output C
Capacity OUT 8 p
SYSTEM CHARACTERISTICS (Ta= -40r1o85oC)
ITEM SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Zero Point Error Ezp - " tT
Full Scale Error EFS VDD=5V, Vss=0V - k al- KI LSB
N nli 'rt - +.l
o nearl y - 4 KI
STC Min. Pulse Wldth tw * - - s
. fosc
. . 10a 3
Conversion Time tconv. A1N= 0sFS * f - 3.1x10 s
OSC fOSC
* fosc l OSC terminal clock frequency [Hz], FS l Full Scale voltage, VDD level
TEST CIRCUIT
TCSOQQAP
IDD(opr .) Test Circuit
, Egg ic?---- 0.1uF
lSOOpFI 7
DOT 15
l,2,4,8
J: __VJ
Switching Time Test Circuit
1500PF
Rf is adjusted as fosc==lMHz.
\JO‘LnkDJ-‘NH
SWITCHING CHARACTERISTICS TEST WAVEFORMS
DATAOm3
DATA0m3
1. tpLH, tpHL (RSEL-DATA)
3. tw (STC)
20ns 20ns
5or, 501"
102 .LQA.
- g, 907,
il? 5070
tPLH I I tpHL
__4 .tp_HL, tpLH
20ns 20ns
tZL, tzn, th, tZL
20ns 20ns
RENB 3% .9%7
4.318% i451.
DATA / 901',
(YI/Y ' lor, KCl..
tzn tHZ
DATAOW '-""hr. 90T,
tZL th
EsosoAP
STANDARD CHARACTERISTICS CHARTS
Fi . 1 VDD - IDD(opr) Fig 2 IDD(opr) - fOSC
c. 3 Ta=25°C tl 2.2 Ta=25°C /
3 fOSC=l MHz 3 . R oscillation
g 25 (R oscillation g 2.0- TYP.
Cg TYP. 5 "
.5'tC2 "H LS r
“ E 3." VDD---
$15 EEl 0.5v
m U) b---
g0 1 32°14
“.4 -H
, 05 tf 2
8. O 1 2 3 4 5 6 Q. 100k 300k 500k 1M 2M
C) u 1 e VDD O Clock Frequency fOSC (Hz)
Fig. 3 P-channel Output Buffer Drain Fig. 4 N-channel Output Buffer Drain
Current Characteristics Current Characteristics
Drain to Source Potential Difference vDS(V
-6 -5 -4 -3 -2 -1 0
Vcs = -5v
Ta = 25°C
VGS =5ll
Ta = 25°C
In (mA)
Drain Current
Drain Current
0 l 2 3 4 S
Drainto SourcePotentialDifferenceVDS(V)
Fig.5 Rf - fosc Fig. 6 fosc - VDD
Rf=20kQ
Ta = 25°C
fosc (Hz)
fosc (Hz)
300k500k
3k 10k 30k 50k 100k
External Resistor Rf[Q]
Su 1 Volta e VDD ll
Cl til
Q) tll
{1. In
Propagation Delay Time tpd (ns)
Fig. 9
(Note)
Tcsgsom:
tpd - VDD (PERB-DATA) Fig. 8 tpd - VDD (RSEL (L-HO-DATA)
Ta=25°C TYP.
CL=50pF
Ta=25°C
CL---50PF
2 3 4 5 6 7
Supply Voltage VDD(V)
l 2 3 4 5 6
Supply Voltage VDD(V)
Propagation Delay Time tpd (ns)
tpd - VDD(RSEL(H-+L)-DATA) RT.CI - fosc
l 2 3 h 5 6
Supply Voltage VDD(V)
105 106
Clock Frequency fOSC (Hz)
IntegratorTimeConstant RI-C1(s)
The characteristics at Fig. 10 have been prepared for reference at the
time of determination of an integrator time constant, according to the
equation of for determing Rrcr.
(RI-C1= (0.9s2.5) [Sec])
In case of the determination of R1 and CI, the product, or the value,
of RI and CI is required to be within the range of MIN. to MAX. as shown
in Fig. 10 after due consideration of dispersion.
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