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TB62708NTOSHIBAN/a640avai16BIT SHIFT REGISTER, LATCHES & CONSTANT CURRENT SOURCE DRIVER


TB62708N ,16BIT SHIFT REGISTER, LATCHES & CONSTANT CURRENT SOURCE DRIVERT362708NTR677DRMvVVI‘1GBIT SHIFT REGISTER, LATCHES & CONS'TAN'TThe TB62708N is specifically designe ..
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TB62708N
16BIT SHIFT REGISTER, LATCHES & CONSTANT CURRENT SOURCE DRIVER
TOSHIBA
TB62708N
TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC
TB62708N
16BIT SHIFT REGISTER, LATCHES & CONSTANT
CURRENT SOURCE DRIVERS
The TB62708N is specifically designed for LED and LED
DISPLAY (Cathode Common) constant current drivers.
This constant current output circuits is able to set up
external resistor (lOUT=5--90mA).
This IC is monolithic integrated circuit designed to be
used together with Bi-CMOS process.
The devices consist of 16bit shift register, latch, AND-
chlllliilll‘ll
GATE and Constant Current Drivers. 'll
FEATURES
SDlP30-P-400-1.78
o Constant Current Output : Weight : 1.999 (Typ.)
Can set up all output current with one resistor for 5 to 90mA.
o Constant Output Current Matching :
OUTPUT-GND CURRENT OUTPUT
VOLTAGE MATCHING CURRENT
22.0 [V] $6.0 [%] -90 [mA]
. Maximum Clock Frequency : fCLK= 15 [MHz] (Cascade Connected Operate, Topr=25°C)
0 5V CMOS Compatible Input
0 Package : SDlP30-P-400-1.78 (TB62708N)
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within sdecified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual propert or other rights of the third
parties which may result from its use. No license is granted by implication or ot erwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1998-05-19 1/11
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TOSHIBA
TB62708N
TIMING DIAGRAM
SERIAL-IN
ENABLE
SERIAL-OUT
(Note) Latches are level sensitive, not rising edge sensitive and not synchronous CLOCK.
Input of LATCH-terminal to "H" level, data passes latches, and input to "L" level,
data hold latches.
Input of ENABLE-terminal to "H" level, all output (OUTO-15) do off.
TERMINAL DESCRIPTION
PIN No. PIN NAME FUNCTION
1 GND GND terminal for control logic.
2 SERIAL-IN Input terminal of a serial-data for shift-register
3 CLOCK Input terminal of a clock for data shift to up-edge.
4 LTrtlq Input terminal of a data strobe. Latches passes data with "H" level input of
LATCH-terminal, and hold data with "L" level input.
3:;3: OUTO-15 Output terminals.
- Input terminal of output enable. All outputs (OUTO~7) do off with "H" level
27 ENABLE . - . . " " .
input of ENABLE-terminal, and do on with L level input.
26 SERIAL-OUT2 Output terminal of a serial-data for next SERIAL-IN terminal.
28 SERIAL-OUT1 Output terminal of a serial-data for next SERIAL-IN terminal.
29 R-EXT Input terminal of connects with a resister for to set up all output current.
30 VDD 5V Supply voltage terminal
"d, 122' VCC 0--17V Supply voltage terminal for LED
1998-05-19 3/11
TOSHIBA
TB62708N
TRUTH TABLE
CLOCK LATCH ENABLE SERIAL-IN OUTO ... OUT7 ... OUT15 SERIAL-OUT1 SERIAL-OUT2
UP H L Dn Dn Dn-7 . Dn-15 Dn-15 Dn-16
DOWN H L Dn Dn Dn-y . Dn-15 No change Dn-15
UP L L Dn +1 No change (data hold) Dn-14 No change
DOWN L L Dn +1 No change (data hold) No change Dn-14
No Edge H L Dn +1 Dn+1 ... Dn-ti . Dn-14 No change No change
No Edge X H Dn +1 Off Dn-14 No change
(Note) OUTO--15=on in case of Dn="H" level and OUTO--15=off in case of Dn ="L" level.
A resistor is connected with R-EXT and GND accompanied with outside, and it is
necessary that a correct power supply voltage is supplied.
EQUIVALENT CIRCUIT OF INPUTS AND OUTPUTS
1. ENABLE, LATCH, CLOCK & SERIAL-IN terminal
2. SERIAL-OUT terminal
voDCr- VDD
CLOCK, x
SERIAL-IN O—fi DATA{: SERIAL-OUT1, 2
LA-TCH
GND GND
MAXIMUM RATINGS (Ta=25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage VDD o--7.o V
Supply Voltage for LED VCC 0~17 V
Input Voltage VIN -0.4--VDD+0.4 V
Output Current IOUT -90 mA
Output Voltage VCE - 0.4--17.0 V
Clock Frequency fCK 15 MHz
GND Terminal Current 'VCC 1440 mA
. . . 2.08 (ON PCB, Ta=25°C)
Power Dissipation PD 1.56 (FREE AIR, Ta=25°C) W
Operating Temperature Topr -40--85 "C
Storage Temperature Tstg - 55--150 "C
(Note) Ambient temperature delated above 25°C in the proportion of 16.64mW/°C on PCB.
On PCB(100 x 150 x1.6mm.Universa| PCB).
1998-05-19 4/11
TOSHIBA
TB62708N
RECOMMENDED OPERATING CONDITION (VDD=5V, Ta = -40--85oc unless otherwise noted)
CHARACTERISTIC SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Supply Voltage VDD - 4.5 5.0 5.5 V
Supply Voltage for LED VCC GND Standard 0 - 17 V
Output Voltage VOUT VCC Standard 0 - - 17 V
IOUT OUTn, DC 1 circuit -5 - -78
Output Current IOH SERIAL-OUT1, 2 - - 1.0 mA
IOL SERIAL-OUT1, 2 - - - 1.0
VIH - DD
VDD + 0.3
Input Voltage V
VIL - 0 3 0.3
LATCH Pulse Width tw LAT vDD=4.5~5.5v 100 - - ns
CLOCK Pulse Width tw CLK 50 - - ns
ENABLE Pulse Width tw EN 1000 - - ns
Set-Up Time tsetup 50 - - ns
Hold Time thold 30 - - ns
Clock Frequency fCLK Cascade operation - - 10.0 MHz
Power Dissipation PD ON PCB, Ta=85°C - - 1.08 W
ELECTRICAL CHARACTERISTICS (Vcc=17V, VDD=5V, Ta = 25°C unless otherwise noted)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
"H" L I v - - - V
Input eve IH VDD DD V
Voltage " " 0.3
L Level VIL - - GND -
Output Leakage
I - v =17. v - - -1 A
Current LEAK CC 0 0 /4
V - I = 1. A - - .4
Output S-OUT OL OL 0m 0 V
Voltage VOH - IOH = -1.0mA 4.6 - -
VOUT= REXT= 3600
Output Current 1 IOL1 - l/cc-NN (Include skew) 66.3 78 89.7 mA
VOUT= - + + 0
Current Skew AIOL1 - Vcc-2.0V REXT--360n - - 1.5 -6.0 hh
Supply Voltage 0 - - o o
Regulation A: /VDD - REXT - 3600, Ta - 40 85 c - 1.5 5.0 A: /V
C ent 1 " " - EXT" I = - . I
urr ON IDD (on) OUTO--15=on 10.0 15.0
" " REXT=3600, ALL DATA="L"
FF I - - 1. 2. A
Supply 0 CC (off) OUTO--15 =off o 0 m
Current 2 " " REXT=3600, ALL DATA="H"
ON 'CC(on) - OUTO-15=on - 1260 - mA
1998-05-19 5/11
TOSHIBA TB62708N
SWITCHING CHARACTERISTICS (Ta=25°C, unless otherwise noted)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
P . CLK-OUTn - 200 500
'ir2'lri,t,i,1n LATCH-OUTn t - 200 500 ns
("L")Ccol”H") ENABLE-OUTn pLH - - 200 500
CLK-SOUT - 30 70
P . CLK-OUTn - 200 500
'ir2'lri,t,1',n TTCHOUT“ t {CLK, LATCH &IEN/:BLE - 200 500 ns
'/"'ipd "L") ENABLE-OUTn PHL 2,ta'Y & tPHL ' 50% to - 200 500
CLK-SOUT tl - 30 70
CLK t CLK - VDD = 5.0V, VCC =17.0V - 20 30
Pulse Width W CLK, I/OUT-O/cc-MI/ ns
LATCH tw LAT, LAT - V|H=VDD - 10 25
tg/l Time for LATCH & tsetup LAT - VIL-- GND - 25 50 ns
Hold Time for LATCH & REXT=3600
CLOCK thold LAT - RL= 3000 - 0 15 ns
Maximum CLOCK Rise Time tr - - - 10 gs
Maximum CLOCK Fall Time tf - - - 10 gs
Output Rise Time tor - 150 300 600 ns
Output Fall Time tof - 150 300 600 ns
1998-05-19 6/11
TOSHIBA TB62708N
DC CHARACTERISTICS TEST CIRCUIT
VDD VCC
OUTO D-o
o-C. ENABLE l I .
Ill. llH o-C) CLOCK l
- o-C) LATCH OUT15 D-o
o-C) SERIAL-IN SERIAL-OUT1 D-o
VIL, VIH
o- CLEAR GND SERIAL-OUT? D-o
AC CHARACTERISTICS TEST CIRCUIT
VIH, VIL DD CC
CLOC K
SERIAL-IN OUT15
CLEAR SERlAL-OUT1, 2
SW-MATR |
PRECAUTIONS for USING
Utmost care is necessary in the design of the output line, VCC Woo) and GND line since IC may be
destroyed due to short-circuit between outputs, air contamination fault, or fault by improper
grounding.
1998-05-19 7/11
TOSHIBA TB62708N
TIMING WAVEFORM
1. CLOCK-SERIAL OUT, OUTn
10% 10%
SERIAL IN 50% S 50%
thold t'
I tsetup
SERIAL OUT1,
SERIAL OUT2
tpLH tpHL
2. CLOCK-LATCH
CLOCK / 50% $50%
tw CLK
SERIAL IN X X
LATCH Li-T, 5\50%
tw LAT
tsetu p
3. ENABLE, LATCH-OUTn
ENABLE, LATCH 50% ii 50%
tpLH tpHL
OUTn 50% 50%
1998-05-19 8/11
TOSHIBA TB62708N
IOUT - DUTY CYCLE IOUT - DUTY CYCLE
ON PCB
Ta =25°C it
- FREE AIR
g Ta=60°C z
£3) Ta=85 C 5
VDD-- 5V, VCC=17V it
Vo=VCC-Vf--2.0V 2
Tj=120°C (MAX.)
16BIT ACTIVE
0 20 40 60 80 100 - 25 0 25 50 75
DUTY CYCLE (%) AMBIENT TEMP. Ta (°C)
LED DRIVER TB6270X SERIES APPLICATION NOTE
Fig.1 'OUT - REXT
IOUT = fl 26/REXT (0)} X 16
Jj.. 20
""s......
500 1,000 2,000 3,000 5,000
R-EXT (Q)
1998-05-19 9/11
TOSHIBA TB62708N
[1] Output current (IOUT)
IOUT is set by the enternal resistor (R-EXT) as shown in Fig.1.
[2]Tota| supply voltage (VLED)
This device can operate 2.0--2.3V (V0).
When a higher voltage is input to the devide, the excess voltage is consumed inside the device, that
leads to power dissipation.
In order to minimize power dissipation and loss, we would like to recommended to set the total
supply voltage as shown below.
VLED (Total supply voltage)
=VCE (Tr Vsat) +Vf (LED Forward voltage) +Vo (IC supply voltage)
When the total supply is too high considering the power dissipation of this devide, an additional R
can decrease the supply voltage (V0).
APPLICATION
ABA Vcc=4~17(V)
O C) " , ,
- VCC VCC _
J‘ OUTO
w ENABLE I c.A
aC,.") CLOCK E
w LATCH l
n OUT15
w SERIAL-IN D-
R-EXT GND SERIAL-OUT
CPU ( i C) T
Impedance
<3 5 , ,
- Vcc Vcc
f‘ OUTO - - - I-
w ENABLE I
-'C, CLOCK l
V LATCH l
-c SERIAL-IN OUT1 5 ”7
R-EXT GND SERIAL-OUT
VCE = VLED - Vf (LED) - VCE (NPNTr)
Best Condition at VCE=2.0~2.4V
[3] Pattern layout
This device owns only one ground pin that means signal ground pin and power ground pin are
common.
If ground pattern layout contains large inductance and impedance and the voltage between ground
and LATCH, CLOCK terminals exceeds 2.5V by switching noise in operation, this device may miss-
operate. So we would life you to pay attention to pattern layout to minimize inductance.
1998-05-19 10/11
TOSHIBA TB62708N
OUTLINE DRAWING
SDIP30-P-400-1.78 Unit : mm
r-lr-nf-lr-Ir-lr-lei-lr-Tl-CIF-lr-lr-nr-lf-l
8.8:02
l_Jl_l|_H_l|_H_l|_l|_l|_l|_ll_]l_ll_1I_ll__l
27.9MAX pe
27.4i0.2
044 t'0.-r.
I: F J} E
flu. st' t
a' b to.
1.254TYP ' l 1.0101 I ' 0.46i0.1 Slj5.C1Ctitih5
1 .778
Weight : 1.99g (Typ.)
1998-05-19 11/11

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