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TB62702FTOSHIBAN/a40avai10 BIT SERIAL-IN PARALLEL-OUT SHIFT REGISTER/ LATCH/10SEGMENT LED DRIVERS


TB62702F ,10 BIT SERIAL-IN PARALLEL-OUT SHIFT REGISTER/ LATCH/10SEGMENT LED DRIVERSFEATURES DIPZO-P-300-2.54A. . . . . TB62702F0 10bit serial-in parallel-out shift reguster/latch/10s ..
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TB62702F
10 BIT SERIAL-IN PARALLEL-OUT SHIFT REGISTER/ LATCH/10SEGMENT LED DRIVERS
TOSHIBA TB62702P/F
TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC
TIM2702P, TB62702F
1OBIT SERIAL-IN PARALLEL-OUT SHIFT REGISTERILATCH/1OSEGMENT
LED DRIVERS
The TB62702P, TB62702F are specifically designed for 10- T862702P
Segment LED Drivers and LED display. And these are
monolithic integrated circuits designed to be used
together with Bi-CMOS (DMOS) integrated circuit. The
devices consist of a 10bit shift Register and 10bit Latches,
and 10bit DMOS structures.
FEATURES DIP20-P-300-2.54A
. . . . . TB62702F
o 10bit serial-in parallel-out shift register/Iatch/105egment
LED driver (Bi-CMOS process)
0 CMOS compatible inputs
0 Open-drain DMOS outputs
0 Low steady-state power consumption
0 Serial data output for cascade operation
SOP20-P-300-1.27
o Packge; P-type DIP-20-P-300A Weight
F-type SOP-20-P-300 DIP20-P-300-2.54A : 2.25g (Typ.)
SOPZO-P-300-1.27 : 0.489 (Typ.)
PIN CONNECTION (TOP VIEW)
L-tSNDC1 V zkoDD
ENABLEEZ 191m
WE3 18]CLOCK
S-OUTEA 17 JS-IN
P-tiNDr 5 16 JP-GND
WES 151W
(WIN 14IIWT2
(WEB 131m
OTT7[9 121m
(WEN 111m
961001EBA2
O TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can
malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing
TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss
of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the
TOSHIBA Semiconductor Reliability Handbook.
0 The products described in this document are subject to foreign exchange and foreign trade control laws.
o The information contained herein is presented only as a guide for the apflications of our products. No responsibility is assumed by TOSHIBA
CORPORATION for any infringements of intellectual property or other rights 0 the third parties which may result from its use. No license is granted
b implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
o T e information contained herein is subject to change without notice.
1998-04-21 1/8
TOSHIBA TB62702P/F
BLOCK DIAGRAM
OUT1 OUT2 OUT? OUT9 OUT10
% s) #1.) I O VSS
ENABLE 0 ? ,
Q Q Q Q Q
- F I F I [a I r T i" T.
D D D D D
LATCH O . . . .
Q Q Q Q Q
S-IN o- D Q D Q D Q - ------_-- - D Q D Q -o S-OUT
> - > - > - > - > -
R R R R R
T T c) U
CLK C . . . .
CLEAR C
MAXIMUM RATINGS (Ta = 25°C, vss = 0V)
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage VDD -0.3--7.0 V
Input Voltage VIN -0.3~VDD+O.3 V
Output Drain-Source Voltage VOUT -0.4--30 V
Input Current IOUT 30 mA/bit
Power Dissipation PD 1.47 W
F (Note 1) 0.96 (Note 2)
Operating Temperature Topr -40~85 "C
Storage Temperature Tstg -55--150 "C
(Note 1) Deleted above 25°C in the proportion of 11.7mW/°C (P-type),
7.7mW/°C (F-type).
(Note 2) On Glass Epoxy (50x50x1.6mm Cu 40%)
1998-04-21 2/8
TOSHIBA TB62702P/F
RECOMMENDED OPERATING CONDITIONS (Ta = -40--8yC, I/ss-UN)
CHARACTERISTIC SYMBOL CONDITION MIN. TYP. MAX. UNIT
Supply Voltage VDD - 4.5 5 5.5 V
Input "H" Level VIH - 0.7 VDD - VDD V
Current "L" Level VIL - 0 - 0.3 VDD
Output Drain-Source
Voltage VOUT - - - 30 V
Output Current 'OUT Duty=100%, All output "L" level - - 24 mA/ch
Power P - - - 760
Dissipation F PD (Note 1) - - 470 mW
(Note 1) On Glass Epoxy (50x50x1.6mm Cu 40%)
ELECTRICAL CHARACTERISTICS (Ta = -40--85oc, VDD=4.5~5.5V, VSS=OV)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
"L" Level l/DSI - IOUT =15mA, Ta = 25°C - - 0.18
Output "L" Level I/DSI - IOUT=15mA - - 0.27 V
Voltage "L" Level VDS2 - IOUT=26mA, Ta =25°C - - 0.31
"L" Level VDS2 - IOUT=26mA - - 0.47
Output Resistor RON - Ta=25°C, IOUT=26mA - - 12 n
V = V EN = "L"
'021 - It,?,," 30 ' - - 10
Output Current I VOUT= 30V, EN = "L" ll PA
022 10bit -
IIN - VIN =VDD or l/SS - - ll
Input Current IlL - ENABLE, le=v55 -27.5 -55.0 - 110.0 ”A
"H" Le el I - -400 -600 -
Output V OH VDS =4.61/, VDD = 5.0V pA
Current " " S-OUT
L Level IOL - VDS = 0.4V, VDD = 5.0V 400 600 -
Input "H" Level VIH - - 0.7 VDD - VDD V
Voltage "L" Level VIL - - 0 - 0.3 VDD
Operating Supply fCLK=5MHz
Current IDD1 - NO loads, 1bit - - 1500 pA
Supply Current IDD2 - - - - 500
TOSHIBA TB62702P/F
SWITCHING CHARACTERISTICS
(Ta = 25°C, VDD = 5V, VOUT = 30V, RL =11500, CL =15pF, "H" = VIH, "L" = VIL)
CHARACTERISTIC SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
. CLK-OUTn LAT="H", CLR="H", EN="H" - - 250
PD'jPagTémn CLK-OUTn t W=”H", EN="H" - - 250
eay ".'l.e LtiT-Otm, pLH ctR="H", EN="H" - - 200 ns
(Low-to-High) _...-.......-- u " _..-..-....- " "
EN-OUTn LAT= H ' CLR= H - - 150
Propagation CLK-OUTn W: "H", CW: "H", EN = "H" - - 250
Delay Time LttOUTn tpHL CW: "H", EN = "H" - - 200 ns
(High-to-Low) EN-OUTn W: "H", ttR-- "H" - - 150
. CLK-CET tsetup (L) - - - 50
Set Up Time CLK-S-IN tsetup(D) - - - 35 ns
. CLK-W thold (L) - - - 105
old 1me CLK-S-IN tholdm) - - - 50
Clock Pulse Width tw CLK - - - 100
Latch Pulse Width tw LITn - - - 50
Clear Pulse Width tw a - - - 50 ns
Enable Pulse Width tw EN - - - 400
. . tor OUTn - - 1000
Output use me tr S-OUT, VSS=OV - - 50 ns
0 t t Fall Time tof OUT" - - 150
u pu tf S-OUT, Vss=OV - - 50
Maximum Clock fMAX1 Duty=50% Cascade connected 5 8 - MH
Frequency fMsz Duty = 50% 6 12 - z
RECOMMENDED TIMING CONDITIONS (Ta-- -4iV-85oC, VDD=4.5~5.5V, Vss--0)
CHARACTERISTIC SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Clock Pulse Width tw CLK - 100 - - ns
Enable Pulse Width tw EN - 400 - - ,us
Latch Pulse Width tw W - 100 - - ns
Clear Pulse Width tw = - 100 - - ns
Data Set Up Time tsetup - 100 - - ns
Data Hold Time thold - 150 - - ns
1998-04-21 4/8
TOSHIBA TB62702P/F
TIMING DIAGRAM
1. Input timing diagram
1 MMAX
CLOCK 50%
S-IN 50% s))iN::j_s1:hs)::):,), \X0% 50%
tsetup (D) thold (D) tsetup (D) thold (D)
tw LAT
LATCH 50% 50%
0V tsetup (L) thold (L)
2. Propagation delay time
CLOCK 50% 50%
ENABLE
tpLH tpHL
90% 90%
o 10% 10%
N -il,
1998-04-21 5/8
TOSHIBA TB62702P/F
LATCH I 50% 50%
CLEAR 50%
0V tpLH tpHL
tpHL [
90% 90%
OFF -,..,r,,T
90% - - 90%
10% 10%
tof tor
PD - Ta
C) co TYPE-P FREE AIR PRECAUTIONS for USING
E 1.25 N a TYPE-F ON GLASS EPOXY
Z N, (50x50x1.6mm Cu 40%) Utmost care is necessary in the design of the
m 1-00 N output line, Vcc (VDD) and GND (L-GND,
,9 0.75 © 0 P-GND) line since IC may be destroyed due to
< . . . . .
'tri \ N short-circuit between outputs, an contamination
'i), 0.50 N )x, fault, or fault by improper grounding.
E 's, N
l 0.25 "c:,
0 25 50 75 100 125 150 175 200
AMBIENT TEMPERATURE Ta CC)
1998-04-21 6/8
TOSHIBA TB62702P/F
OUTLINE DRAWING
DI P20-P-300-2.54A
r-lr-lr-lr"'"))'-).-]'"''"-)'"'''"):
I-JI-JL-ll-JI.,,..-).,.,.-);););)
25.1 MAX v
24.trhth2
2id.7-TY-P. um I
Weight : 2.259 (Typ.)
1998-04-21 7/8
TOSHIBA TB62702P/F
OUTLINE DRAWING
SOPZO-P-300-1.27 Unit : mm
FlllRliFlplliRliR "
cu. N 1;:
D) E E 2?
ID n g),
[lljhljhldldl3ljrL_..__.__._, IL
th685TYP, = " _ 0.43101 23m:
l I 13.3MAx _
12.8:02
, -.“o’.
g ttt W?
'dtaCl5t1la5tCl%ti, ,. .2 f
F8 ci,
_,Zhtj.I 5ieis" J
g -. l 0.8:02
Weight : 0.48g (Typ.)
1998-04-21 8/8

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