TB1212N ,SINGLE CHIP NICAM SYSTEMTB1212N/Fm""'""""""""' M-MM-MM-qSINGLEThe TB1212N and TB1212F are single chip processor forNICAM (N ..
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TC74HC166AFN , 8-Bit Shift Register (P-IN, S-OUT)
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TC74HC166AP , 8-Bit Shift Register (P-IN, S-OUT)
TB1212N
SINGLE CHIP NICAM SYSTEM
TOSHIBA
TB1212N/F
TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC
TIM 21i 2N, TIM 21l 2F
SINGLE CHIP NICAM SYSTEM
The TB1212N and TB1212F are single chip processor for
NICAM (Near Instananeous Conpand Audio. Multiplex)
System. This is to get a PCM sound signal from QPSK
modulated signal and to get an analog sound signal
selected between said PCM sound signal and FM sound
signal.
Functionally, QPSK demodulation, sound data decoding,
sound channel selection, Digital filter, DAC, and so on are
integrated into one chip.
FEATURES
It AGC Circuit
0 Phase Synchronous Demodulation by Base Band Select PLL
0 Frame Sync. Detection. (FAW Sync., Co Sync.)
o De-scramble. (PN code reduction)
It Control data majority-decision detection
o De-interleave.
0 Range bit majority-decision detection
It Control information bit majority-decision detection
It Parity detection and error correction
o 10-el4bit expansion
o Digital Mutiny Circuit (Variable Mute Level)
It " bus interface
It Built in RAM (3.5Kbit)
TB1212N
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SDIP64-P-750-1.78
TB1212F
QFP80-P-1420-0.80A
Weight
SDIP64-P-750-1.78 : 8.85g (Typ.)
QFP80-P-1420-0.80A : 1.6g (Typ.)
2001 -06-1 9
TOSHIBA TB1212N/F
o 2 times over sampling digital filter
0 Switchable Digital De-emphasis (CCITT Recommendation J.17)
0 182 times over sampling EADAC
o 5V power Supply
BLOCK DIAGRAM
”K QPSK Decoder oii'it2afiiifte,
Analog I
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GNDC-- RAM r-------------" L ODE SEL
sELIC-- l
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Bus loc: ,2 2 - x182 0.5. Digital
SCL ' I C - EADAC De-emphasis
SDAC l l l
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Digital
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38 TB1212N
TB1212F
D 2BCK
(is) 2DATA
DOUT R
D DAC GND
Cii) DOUT R
DOUT L
(ii) DOUT L
D DAC GND
D 2LRCK
D DAC VDD
TOSHIBA
TERMINAL CONNECTION DIAGRAM
TB1212N/F
TOSHIBA TB1212N/F
TERMINAL FUNCTION (64 PIN SHRINK DIP)
Kl"?! PIN NAME I/O FUNCTION
1 GAIN I GAIN -6dB/ -3.5di? Select SW (L : -6dB, H : -3.5dB)
2 MUTE LVL I MUTE level control
3 N.C - -
4 N.C - -
5 NC - -
6 NC - -
7 CL VCXO O 0 Data Clock VCXO output
8 CL VCXO l2 I Data Clock VCXO input 2
9 CL VCXO " I Data Clock VCXO input 1
10 CL APC FO 0 Data Clock APC filter output
11 CL APC Fl I Data Clock APC filter input
12 A VCC - Analog VCC 5Vi10%
13 QPSK IN I QPSK signal input
14 AGC FILTER O AGC filter output
15 CH A OUT 0 Channel A detection output
16 CH B OUT 0 Channel B detection output
17 CH B IN I Channel B detection input
18 CH A IN I Channel A detection input
19 CA APC F 0 Carrier APC filter output
20 CA VCXO O C) Carrier VCXO output
21 CA VCXO I I Carrier VCXO input
22 A GND - Analog GND
23 NC - -
24 W/PCM O FM/PCM select (H : FM, L : PCM)
25 DAC VDD - DAC power supply 5VA 10%
26 DOUT R O PCM sound Digital data output R (Positive)
27 m 0 PCM sound Digital data output R (Negative)
28 DAC GND - DAC GND
29 DAC GND - DAC GND
30 DOUT L O PCM sound Digital data output L (Positive)
31 DOUT L O PCM sound Digital data output L (Negative)
32 DAC VDD - DAC power supply 5VA10%
33 2LRCK 0 LR clock output for DAC (x2 over sampling)
34 2BCK 0 Bit clock output for DAC (x2 over sampling)
35 2DATA 0 DATA output for DAC (x2 over sampling)
36 D VDD - Digital VDD 5Vi10%
37 LRCK 0 LR clock output for DAC
38 BCK 0 Bit clock output for DAC
39 DATA 0 DATA output for DAC
40 SCL I SCL input for IZC bus control
4 2001-06-19
TOSHIBA
TB1212N/F
K's PIN NAME I/O FUNCTION
41 SDA I/O SCL input for Pc bus control
42 DE SEL I Digital De-emphasis control (L : use, H : No use)
43 SEL2 I PCM Audio output selection signal input
44 SEL1 I PCM Audio output selection signal input
45 MUTE IN I Digital Mute signal input
46 MUTE OUT 0 Digital Mute signal output
47 D GND - Digital GND
48 D GATE 0 Gate signal for data output
49 D DATA 0 Data output
50 ptTITi 0 Parity error output
51 SE-RR O Sync error output
52 C71 0 Mode display signal output : C4
53 MON-tya- 0 Mode display signal output : Monaural 2
54 MONO1 0 Mode display signal output : Monaural 1
55 STE-REO 0 Mode display signal output : Stereo
56 D GND - Digital GND
57 TEST3 I Test terminal (to be grounded to D.GND)
58 TEST2 I Test terminal (to be grounded to D.GND)
59 TEST1 I Test terminal (to be grounded to D.GND)
60 'l1TGTrT' I RESET input
61 MCLK O Clock output 2 (5.824MHz)
62 RCLK O Clock output 1 (728MHz)
63 RDATA 0 Bit Stream data output
64 D VDD - Digital VDD 5V* 10%
2001 -06-1 9
TOSHIBA TB1212N/F
TERMINAL FUNCTION (80 PIN FP)
fe'. PIN NAME I/O FUNCTION
1 CL VCXO li? I Data Clock VCXO input 2
2 N.C - -
3 CL vcxo " I Data Clock vcxo input 1
4 CL APC FO o Data Clock APC filter output
5 CL APC Fl I Data Clock APC filter input
6 A VCC - Analog VCC 5Vi'10%
7 QPSK IN I QPSK signal input
8 AGC FILTER O AGC filter output
9 CH A OUT 0 Channel A detection output
10 N.C - -
11 CH B OUT o Channel B detection output
12 N.C - -
13 CH B IN I Channel B detection input
14 CH A IN I Channel A detection input
15 N.C - -
16 CA APC F 0 Carrier APC filter output
17 CA VCXO O 0 Carrier VCXO output
18 CA VCXO I I Carrier VCXO input
19 A GND - Analog GND
20 N.C - -
21 N.C - -
22 W/PCM O FM/PCM select (H : PCM, L : FM)
23 N.C - -
24 DAC VDD - DAC power supply 51/* 10%
25 DOUT R O PCM sound Digital data output R (Positive)
26 DOUT R O PCM sound Digital data output R (Negative)
27 DAC GND - DAC GND
28 DAC GND - DAC GND
29 DOUT L O PCM sound Digital data output L (Positive)
30 TRh-yt-L O PCM sound Digital data output L (Negative)
31 DAC VDD - DAC power supply 5Vi10%
32 N.C - -
33 2LRCK 0 LR clock output for DAC (x2 over sampling)
34 2BCK 0 Bit clock output for DAC (x2 over sampling)
35 2DATA 0 DATA output for DAC (x2 over sampling)
36 N.C - -
37 D VDD - Digital VDD 5Vt10%
38 LRCK 0 LR clock output for DAC
39 BCK O Bit clock output for DAC
40 DATA C) DATA output for DAC
6 2001-06-19
TOSHIBA
TB1212N/F
2l,u. PIN NAME l/O FUNCTION
41 NC (GND) - -
42 SCL I SCL input for " bus control
43 SDA I/O SDA input/output for IZC bus control
44 DE SEL I Digital De-emphasis control (L : use, H : No use)
45 SEL2 I PCM Audio output selection signal input
46 NC - -
47 SEL1 I PCM Audio output selection signal input
48 MUTE IN I Digital Mute signal input
49 NC - -
50 MUTE OUT O Digital Mute signal output
51 D GND - Digital GND
52 D GATE 0 Gate signal for data output
53 D DATA 0 Data output
54 NC 0 -
55 "pt-lik- o Parity error output
56 f;tiTt'k- O Sync error output
57 N.C - -
58 C7; 0 Mode display signal output : C4
59 MON02 0 Mode display signal output : Monaural 2
60 hTOTTtTf 0 Mode display signal output : Monaural 1
61 TTtTkTrt5 0 Mode display signal output : Stereo
62 D GND - Digital GND
63 NC - -
64 TEST3 I Test terminal (to be grounded to D.GND)
65 TEST2 I Test terminal (to be grounded to D.GND)
66 TEST1 I Test terminal (to be grounded to D.GND)
67 W I RESET input
68 MCLK O Clock output 2 (5.824MHz)
69 RCLK O Clock output 1 (728MHz)
70 RDATA 0 Bit Stream data output
71 D VDD - Digital VDD 5Vi10%
72 N.C - -
73 GAIN I GAIN -6dB/ -3.5di? Select SW (L : -6dB, H : -3.5dB)
74 NC - -
75 MUTE LVL I MUTE level control
76 NC - -
77 NC - -
78 NC - -
79 N.C - -
80 CL VCXO O 0 Data Clock VCXO output
2001 -06-1 9
TOSHIBA TB1212N/F
FUNCTION
Outline explain
QPSK demodulation stage
This stage is to get PCM digital data stream from the QPSK signal. An AGC for input signal,
VCXO for Carrier and Clock, differential operation, and P/S conversion functions are included.
VCXO frequency is 6.552MH2 for UK, and 5.85MH2 for Scandinavia. Clock VCXO is 11.648MH2
(16 times of 728kHz).
PCM decoding stage
This stage is to get digital sound data from QPSK demodulated digital data stream and apply
the data to digital filter. Sound signal decoding, receiving mode display, and sound output
selection function are included. De-interleave with SRAM of around 3.5Kbit for frames is built
Digital filtering stage
This is the 2 times over sampling digital filter. (49 order shift adder type) with pass band
ripple of less than 10.1dB, and attenuation less than -40dB.
Digital de-emphasis stage
This is digital de-emphasis circuit meets to CCITT recommendation 1.17 with gain error of less
than i0.25dB. DE SEL of " bus (address B4HEX, sub address 1) or DE SEL (pin 44) setting to
"H" make this circuit invalided.
The DESEL is result of OR logic between the terminal of DE SEL (pin 44) and DE SEL of "
bus (address B4HEX, sub address 1). So, pin 44 is to be connected to D-GND in case of " bus
Control. Or, since the register of IZC is to be initialized to "L" by Reset, SCL, SDA (pin 42, 43)
are to be connected to D-VDD in case of terminal SEL1, SEL2 Control.
Ed DAC stage
182 times sampling EADAC is adopted. This is equivalent to more than 14bit performance.
Complementally output is adopted to improve the sound quality (Distortion Characteristics)
and requires an external adder circuit consist of 'op-amp', which is used also as LPF.
Explanation for each block
Pin 7 QPSK signal level fluctuation is to be controlled.
8 2001-06-19
TOSHIBA TB1212N/F
2. Carrier PLL of 6.552MH2
Control voltage is generated by baseband switching. 90° phase shifter for Det. Phase
generating is built in. Signal from AGC circuit is to be detected by 2 detector of 90° phase
shifted each, and applied to CH A OUT (Pin 9), CH B OUT (Pin11) through LPF. These output
from pin 9 and pin 11 are coupled with capacitance (DC Cut), applied to CH A IN (Pin 14) and
CH B IN (Pin 13). Phase difference of these inputs is detected with analog SW to establish the
control loop for the PLL.
3. Clock PLL
Clock PLL circuit for 11.648MHz, which is 16 times of 728k.
4. Data re-generation circuit
Data and Clock (5.824MHz, 728kHz Synchronized to Data are generated by differential
operation and Pararell to serial conversion. With "H" for O-BS of IZC resister (address B4HEX,
Sub-address 1), Data and Clock (5.824MH2, 728kHz synchronized to Data) can be monitored
each by RDATA (Pin 70), MCLK (Pin 68), and RCLK (Pin 62).
5. Sync. circuit
This stage detects the Shit sync pattern (FAW-Frame Alignment Word) from QPSK signal from
the data re-generation Circuit. And the 'Frame' of 728bits is defined utilizing the 'FAW'.
(TAN-sync established.) The continuity of the sync pattern is checked. The 'FAW-sync'
protection performed with forward 2 frames and backward 6 frames. That is to say the 'FAW-
sync' is established in case of synchronization over 2 continuous frames, and is to be canceled
in case of a synchronization over 6 continuous frames. After FAW established, the 'Co-Frame'
of 16 frames is defined utilizing the 'Co Bit' of the 'Control Bit'. (Co-synchronization.) And the
'Co-sync' protection is performed with forward 2 'Co-Frames' and backward 4 'Co-Frames'. The
-irilTITi" (Pin 56) is to be "L" level in case of a synchronized state (as to 'FAW sync' and 'Co
sync').
6. Descramble circuit
Built-in PN Code generator works synchronously with the frame by the Frame Sunk Pulse
from the sync circuit, and the PN Code of the QPSK demodulated signal is to be rejected.
7. Timing generator
Generate the various timing signal synchronous with the Frame Sync Pulse from the Sync
Circuit.
Control Bit is detected with the majority-decision over 16 frames (1 C0 Frame). So, the data is
to be refreshed by every 16 frames. And the detected control bit is decoded to be lead to
the C4 (Pin 58), MONO2 (Pin 59), MONO1 (Pin 60), and STEREO (Pin 61) output.
8. Control Bit Detection Circuit
Control Bit is detected with the majority-decision over 16 frames (1 C0 Frame). So, the data is
to be refreshed by every 16 frames. And the detected control bit is decoded to be lead to
the CT, (Pin 58), MONO2 (Pin 59), MONO1 (Pin 60), and STEREO (Pin 61) output.
9 2001-06-19
TOSHIBA TB1212N/F
9. Address generator, RAM l/O controller
The de-scrambled signal from the De-scramble Circuit is to be de-interleaved, that is to say
the de-scrambled and interleaved signal from the De-scramble Circuit is to be written into the
RAM, de-interleaved, and read out from the RAM, and these are to be performed under the
Address and timing generated from this Address Generator, RAM I/O Controller. And the
'Write timing', 'Read Timing' for Range Bit Detection, and 'Read timing' for data output to
DAC are the time shared. The data thus de-interleaved is to be applied to the processor for
scale or error, but also is to be generated as it is from the 'DDATA' (Pin 53) with the timing
of the DGATE' (Pin 52) considering the data output in case of the DATA Mode.
10.Range bit detector
The 'Range Bit' and 'Control Information Bit' multiplied to the 'Parity Bit' are detected by the
Majority-decision detection.
11.Parity detector
The 'Range Bit' and the 'Control Information Bit' multiplied to the 'Parity Bit' are removed
with these detected 'Range Bit' and the 'Control Information Bit'. After that, the parity is
checked, and the PERR (Pin 55) is to be "L" level in case of error.
12.10-914bit expander
10bit data is expanded to 14bit data subject to the 'Range Bit'. Adding the "oo" to this 14bit
data as the lowest 2bit, the data is to be regarded as total 16bit data.
13.Error correction circuit
The error found by the Parity Detector is to be corrected by the Average compensation, and
the previous value compensation. Former is against discrete error, latter is against a
continuous error.
10 2001-06-19
TOSHIBA TB1212N/F
14.0utput selector
This stage is to control the output for digital filter subject to control bit C1, C2, C3. from
NICAM data stream and SEL1, SEL2. Here, the SEL1, SEL2 are result of OR logic between the
terminal of SEL1, SEL2 (Pin 47, 45) and bit for SEL1, SEL2 of " bus (address "B4H",
subaddress "0"). So, Pin 47, 45 are to be grounded in case of litc bus Control. Or, since the
register of " is to be initialized to "L" by Re-set, SCL, SDA (Pin 42, 43) are to be connected
to D-VDD in case of terminal SEL1, SEL2 Control.
In case of C1, C2, C3=0, 0, 0, that is stereo, the output is controlled to stereo sound for L-ch
and R-ch. In case of C1, C2, C3: 1, o, 0 that is mono+Data, the output is controlled to
monaural sound for both of L-ch and R-ch.
In case of C1, C2, C3=0, 1, 0 that is mono 2ch, the output is subject to SEL1, SEL2. Ref to
output selection table.
Additionally, in case of SEL1, SEL2=1, 1, the digital sound output is forced to be muted.
Selected digital sound signal can be monitored when "H"=0DI of " (address B4H, sub-
address 1).
Terminal "DATA" (Pin 40) : Data
Terminal "LRCLK" (Pin 38) : LR Clock
s nchroni ed to Data
Terminal "BCK" (Pin 39) : Bit Clock y IZ
15.Muting circuit
MUTE OUT (Pin 50) becomes "H" when ,
0 Sync Error Occurs.
It Parity Error exceed the criteria in a counting period (around 0.55).
MUTE OUT due to sync error has 7 frames delay as same as the Sync Error output.
The MUTE activated when parity bit error rate in 512 frames exceeds 1/8 (MUTE LVL=0) or 1
/16 (MUTE LVL=1), and released when the error rate decreases to less than 1/16 (MUTE
LVL=0) or 1/32 (MUTE LVL=1).
The digital mute function is realized by connecting MUTE OUT (pin 50) and MUTE IN (pin48).
MUTE IN (pin 48) should be grounded ("L") when the digital mute is not required.
This Mutiny circuit is mute level changeable type. And controlled by the terminal of MUTE
LVL (Pin 75) or bit for MUTE LVL (address B4HEX, subaddress 1). The MUTE LVL is result of OR
logic between the terminal of MUTE LVL (pin 75) and bit for MUTE LVL of IZC bus (address
B4HEX, subaddress 1). So, pin 75 is to be connected to D-GND in case of litc bus control. Or,
since register of " is to be initialized to "L'' by RESET, SCL, SDA (pin 42, 43) are to be
connected to D-VDD in case of terminal MUTE LVL control.
11 2001-06-19
TOSHIBA TB1212N/F
16.l2C bus control circuit
Read out of Control bit, output selection, mode setting can be executed through IZC bus
interface. Data is transmitted by selecting the register subject to 8bit address and 3bit sub
address in data. Synchronously to SCL Clock, data is transferred through SDA.
The register is to be initialized to 00H by "L" input to RESET (pin 67).
Stored once, information is kept stored in the register up to next writing.
Analog output select signal is controlled by FM/PCM (L : FM, H : PCM) OF " bus (address
B4HEX, sub address 0). Analog output select signal, put out from FM/PCM (pin 24) is same
signal asset by " and control FM/NICAM (pin 23) of TA2047F.
j: It is required to initialize with RESET (pin 67) of "L" level for start operation. (After power
supply)
17.Digital filter circuit
Digital sound signal from the output selection circuit is applied to this stage to be processed
by 2 times over sampling digital filtering. Filter has 49th order, shifts data and apples the
serial summing, realize the performance of pass band ripple less than i0.1dB, attenuation
less than -40dB.
This digital filter circuit is gain changeable type. And controlled by the terminal of GAIN (pin
73) or bit for GAIN (address B4HEX, subaddress 1). The GAIN is result of OR logic between
the terminal of GAIN (pin 73) and bit for GAIN of IZC bus (address B4HEX, sub address 2). So,
pin 1 is to be connected to D-GND in case of " bus control. Or, since register of " is to be
initialized to "L" by RESET, SCL, SDA (pin 42, 43) are to be connected to D-VDD in case of
terminal GAIN control.
Real output level is maximum level of digital filter in case of control to -3.5dB. And -tidB
from maximum output level in case of control to -6dB. When control to -3.5dB, EADAC has
3.5dB attuenation so not to be overflow, and when control to -6dB LIDAC has no
attunation.
12 2001-06-19
TOSHIBA TB1212N/F
18.Digital De-emphasis Circuit
2 times over sampled digital sound signal is processed by CCITT Recommendation J.17
digital de-emphasis. The gain error is less than t0.25dB. This digital de-emphasis is killed
by "H" =DESEL. Here DESEL is result of OR logic between the terminal of DE SEL (pin 44)
and bit for DE SEL of " bus (address B4HEX, sub address 1). So 44pin is to be connected
to D-GND in case of " bus control. Or, since the register of IZC is to be initialized to "L"
by RESET, SCL, SDA (pin 42, 43) are to be connected to D-VDD in case of terminal DESEL
control.
Digital de-emphasised digital sound signal can be monitored when with "H" =O-D2 of "
bus (address B4HEX, sub address I), O-D2 of sub address"I".
Terminal "2DATA" (pin 35) : DATA
Terminal "2LRCK" (pin 33) : LR clock
Terminal "2BCK" (pin 34) : bit clock
19.24DAC
Synch ron ized to Data
2 times over sampled digital sound signal is interpolated (7 times) and times sampling (13
times) to be 182 times sampled. That is, 1bit ZADAC output of 182 is to be available,
which is equivalent to the performance of more than 14bit multi bit type DAC.
To improve distortion characteristics, complementary outputs are applied to DOUTR,
m, m, DOUTL (pin 25, 26, 29, 30 each). These are converted to analog signal with
external summing circuit TA2047F.
Table. 1 Sound output and display output subject to control bit and sound selection
MODE CONTROL BIT 53$th DISPLAY OUTPUT 381JIDIUDT
c1 c2 c3 c4 SEL1 SEL2 STEREO MONO1 MON02 T L R
x x 0 1 1 1/0 L R
STEREO 0 0 0 0/1 1 1 1 1 1 1 - -
0 0 1 0 0 1/0 M1 M1
0 1 1 0 0 1/0 M2 M2
MONO 2CH 0 1 0 0/1 1 0 1 0 0 1/0 MI M2
1 1 1 1 1 1 - -
x x 1 0 1 1/0 M M
MONO + DATA 1 0 0 0/1
1 1 1 1 1 1 - -
DATA 1 1 0 0/1 x x 1 1 1 1 - -
OTHERS x x 1 0/1 x x 1 1 1 1 - -
x ; means "don't care", - ; means "mute"
M1, M , Data of ODD Frame, M2 ; Data of Even Frame
(Note) SEL1 and SEL2 are result of "OR-Logic" between the terminal of SEL1, SEL2 (pin 47,
45) and bit for SEL1, SEL2 of IZC bus register.
13 2001-06-19
TOSHIBA TB1212N/F
Pc BUS REGISTER
Address B4HEX (Write register)
MSB LSB
0 0 0 0 W/PCM ERMUTE SEL2 SEL1
W/PCM : FM/PCM select O-OFM, I-9PCM
i: Analog output select signal is controlled by W/PCM (L : FM, H .' PCM) of Pc bus (address
B4HEX, sub address 0). Analog output select signal, put out from W/PCM (pin 22) is same signal
as set by " and control FM/NICAM (pin 23) of TA2047F.
ERMUTE : Digital mute ON/OFF control
O-soil 1-9OFF
SEL1, 2 : Digital sound selection (for mono 2 channel)
OO-among 1 01-amono 2
10-9mono 1/mono 2 11-ymute
it In case of received signal is mono 2 channel, output signal to digital filter is controlled by the
terminal of SEL1, SEL2 (pin 47, 45) or bit for SEL1, SEL2 (address B4HEX, sub address O). The
SEL1, SEL2 are result of OR logic between the terminal of SEL1, SEL2 (pin 47, 45) and bit for
SEL1, SEL2 of " bus (address B4HEX, sub address 0). So, pin 47 45 are to be connected to D-
GND in case of " bus control. Or, since register of Pc is to be initialized to "L" by reset, SCL,
SDA (pin 42, 43) are to be connected to D-VDD in case of terminal MUTE LVL control.
Address B4HEX (Write register)
MSB LSB
0 0 1 MUTE LVL DESEL O-BS O-D1 O-D2
MUTE LVL : Mute level control
0-9 MUTE output becomes "H" when the parity bit error rate exceeds 1/8 in 512
frames, and released when the error rate decreases to less than 1/16.
1-9 MUTE output becomes "H" when the parity bit error rate exceeds 1/16 in 512
frames, and released when the error rate decreases to less than 1/32.
i: This muting circuit is mute level changeable type. And controlled by the terminal of MUTE LVL
(pin 75) or bit for MUTE LVL (address B4HEX, subaddress 1). The MUTE LVL is result of OR logic
between the terminal of MUTE LVL (pin 75) and bit for MUTE LVL of IZC bus (address B4HEX,
sub address 1). So, pin 75 is to be connected to D-GND in case of Pc bus control. Or, since
register of PC is to be initialized to "L" by RESET, SCL, SDA (pin42, 43) are to be connected to
D-VDD in case of terminal MUTE LVL control.
DESEL : De-emphasis utility control
0-ause, 1-9NO use
14 2001-06-19
TOSHIBA TB1212N/F
i? This digital de-emphasis circuit is switchable type. DE SEL of " Bus (address B4HEX, sub address
1) or DE SEL (pin 44) setting to "H" make this circuit invalied.
The DESEL is result of OR logic between the terminal of DE SEL (pin 44) and DE SEL of " Bus
(address B4HEX, sub address 1). So, pin 44 is to be connected to D-GND in case of IZC Bus
control. Or, since the register of IZC is to be initialized to "L" by reset, SCL, SDA (pin 42, 43) are
to be connected to D-VDD in case of terminal SEL1, SEL2 control.
In case of digital de-emphasis is off, it is required to use analog de-emphasis by LPF IC, TA2047F.
(c.f. Example of application circuit (1), (2))
Test terminal output control
0-9Fix to "L", I-9Signal output
O-BS : MCLK, RCLK, RDATA
0-D1 : LRCK, BCK, DATA
0-D2 : 2LRCK, 2BCK, 2DATA
Address B4HEX (Write register)
MSB LSB
0 1 0 GAIN SFSEL I-BS l-DI I-D2
GAIN .' Gain control
O-e-tidly 1-a-3.5dB
i: This digital filter circuit is gain changeable type. And controlled by the terminal of GAIN (pin 73)
or bit for GAIN (address B4HEX, subaddress 1). The GAIN is result of OR logic between the
terminal of GAIN (pin 73) and bit for GAIN of " bus (address B4HEX, sub address 2). So, pin1 is
to be connected to D-GND in case of IZC bus control. Or, since register of " is to be initialized
to "L" by RESET, SCL, SDA (pin 42, 43) are to be connected to D-VDD in case of terminal GAIN
control.
SFSEL : Super frame sync. control
0-9All pattern comparison, 1-aEdge detection
Test terminal 1/0 control
0-9Output ' 1-elnput
l-BS : MCLK, RCLK RDATA
l-D1 : LRCK, BCK, DATA
l-D2 : 2LRCK, 2BCK, 2DATA
j: Test terminal 1/0 control (Sub address 2) is prior to Test terminal output control (Sub address 1).
i: "o" shall be put into poen bit above register.
15 2001-06-19
TOSHIBA
TB1212N/F
i: Sub address bit combination other than above must not be applied. (That is to be used for IC
inspection)
Address BSHEX (Read register)
MSB LSB
CI c2 c3 c4 SERR MUTEO CIB1 CIB2
C1-4 : Control bit
SERR .' Sync. error flag
0-aSync. error, 1-aSynchronized
MUTEO : Digital mute flag
0-9Normal, 1-yMute
CIB1, 2 : Control information flag
i: It is required to initialize write register with RESET (pin 67) of "L" level for start operation.
j: Sub address bit combination other than the above must not be applied. (That is to be used for
IC inspection)
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATINGS UNIT
Supply Voltage Vcc, VDD V55~V55+6.0 V
Input Voltage VIN -0.3--vcc, VDD+0-3 V
. . . 1900 (Note 1)
Power Dissipation PD 900 (Note 2) mW
Storage Temperature Tstg - 55--125 ''C
(Note 1) Derated above Ta=25°C in the proportion of
19.0mW/°C. [TB1212N (64pin SDIP Package)]
(Note 2) Derated above Ta=25°C in the proportion of
9.0mW/°C. [TB1212F (80pin QFP Package)]
RECOMMENDABLE OPERATING CONDITION
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Supply Voltage VDD - - 4.5 5.0 5.5 V
Input Voltage VIN - - 0 - VDD V
Operting Temperature Top, - - -20 - 65 "C
16 2001-06-19
TOSHIBA TB1212N/F
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Ta = 25°C, Vcc, VDD = 5.0V)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Consumption Current ICC - - 15 35 55 mA
Consumption Current IDD - - 5 15 35 mA
Power Dissipation PD - - 90 250 495 mW
High Level le - (*1) 4.0 - - v
Input Voltage Low Level VIL - (*1) - - 1.0 v
Hysterisis Width VH - (*2) - 0.6 - V
High Level IIH - VIH = D VDD (*1) - - 10 pA
Input Current Low Level IIL - V|L=D GND (*1) - IO - - pA
High Level vom - IOH = -2.0mA (*3) 4.0 - - v
Low Level V0L1 - IOL= 2.0mA (*3) - - 0.4 V
Output Voltage High Level VOH2 - IOH = -4.0mA (*4) 4.0 - - v
Low Level VOLZ - IOL=4.0mA (*4) - - 0.4 V
(*1) For GAIN, MUTE LVL, SCL, SDA, DE SEL, SEL2, SEL1, MUTE IN, TEST3, TEST2, TEST1, RESET
(*2) SCL, SDA, RESET
(*3)2LRCK, 2BACK, 2DATA, LRCK, BCK, DATA, SDA, MUTE OUT, DGATE, DDATA, W, SEW,
MCLK, RCLK, RDATA, W/PCM
(*4)C_4, MONOZ, MONO1, STEREO
17 2001-06-19
TOSHIBA TB1212N/F
AC CHARACTERISTIC (1) (Ta =25°C, Vcc, VDD=5.0V)
SYM- TEST
TEST ITEM BOL CIR- SWITCH TEST CONDITION MIN. TYP. MAX. UNIT
CUIT 4 5 6
AGC Flat Level eF - b off (1) Apply 6.5MHz, 200mVp-p CW to pin 7. 0.4 0.7 1.0 Vp-p
(2) Measure amplitude at TP4.
AGC Flat Level vs eFV - b off (1) Apply 6.5MHz, 200mVp-p CW to pin 7. - 10 - 10 %/V
Power Supply (*A)
(2) Measure eF at VCC=VDD
=4.5V and 5.5V
eFV=((eF (5.5V)-eF (4.5V))/eF
AGC Flat Level vs eFT - b off (1) Apply 6.5MHz, 200mVp_p CW to pin 7. -0.1 - 0.1 %/°C
Temperature (2) Measure eF at Ta-- - 20°C and 65°C
eFT=((eF (65''C)-eF (-200/eF))/85
AGC Control A - b off (1) Apply 6.5MHz, 100mVp-p/400mVp-p CW - 10 0 1O %
Characteristics to pin 7. (*A)
(2) Measure Amplitude at TP4.
A=100x(eF-eF (100mV)/eF, and
A=100x(eF-eF (400mV)/eF
Output Level Dev. AEO - b off (1) Apply 6.5MHz, 200mVp-p ON to pin 7. - 100 - 100 mV
(2) Measure Amplitude at TP3 and TP4.
AEO=eF (TP4)-eF (TP3)
Relative Dev. Phase 4ls - b off (1) Apply 6.5MHz, 200mVp-p CW to pin 7. - 10 0 10 t2
'o=(t/T)x360-90
(a) Delay between TP3
and TP4, t.
(b) T at TP3.
_.y Cu-ta) : -- TP4
2nd Order DTH - b off (1) Apply 6.5MHz, 200mVp-p CW to pin 7. - - 50 - dB
Distortion (2) Measure level difference between the
fundamentals and the 2nd harmonics.
5g ...................
l" DTH
52 104 frequency (kHz)
(*A)Clock VCXO OFF (CL-VCXO-l2 (Pin 1) connect to GND)
18 2001-06-19
TOSHIBA TB1212N/F
SYM- TEST
TEST ITEM BOL CIR- SWITCH TEST CONDITION MIN. TYP. MAX. UNIT
CUIT 4 5 6
Demodulate Output eCW - b off (1) Apply 6.5MHz, 200mVp-p CW to pin 7. - - 50 - dB
Residual Carrier (2) Measure level difference between
Wave 52kHz and 6.5MHz component.
Analog SW Gs - a off (1) Apply 10kHz, 0.7Vp-p CW to TP6 and 3.0 4.5 6.0 mV/°
Sencitivity TP7 with 90° phase difference.
(2) Measure pin 19 output.
Gs= mVp-p
90° mhrp
Analog SW Output AVas - a off (1) Apply 10kHz, 0.7Vp_p CW to TP6 and O - 20 mV
Level Dev. TP7 with 90° phase difference.
(2) Measure peak level difference at pin 13
Analog SW Cycle RTB - a off (1) Apply 10kHz, 0.7Vp_p CW to TP6 and 0.8 1.0 1.2 -
Ratio TP7 with 90° phase difference.
(2) RTB is the ratio of the max. period
and the min. perdiod.
QPSK Input Level Qin - b off (1) Apply 1kHz QPSK modulated signal to 0.1 0.8 2.0 VP-p
QPSK IN.
(2) Monitor "Eye Pattern" by changeing
the QPSK input level.
(Note) Recommended input level to
untilize AGC function is
o.1~o.4vp_p.
19 2001-06-19
TOSHIBA TB1212N/F
SYM- TEST
TEST ITEM BOL CIR- SWITCH TEST CONDITION MIN. TYP. MAX. UNIT
CUIT 4 5 6 8
Carrier VCXO AFC - b b on a (1) Applying 3.3~3.8V DC as Control l 1.5 12.0 - kHz
Control Range Voltage at CA APC DC.
(2) Measure Control Range of Carrier
VCXO Frequency. (*B)
AFC = 6.552 - f (3.3)
= 6.552 - f (3.8)
C? ________ f (3.3)
g. l AFC
i.? I - 6.552MHZ
g l AFC
[r i ,' . l (3d0
- -3.'3-3.'ssc-ontro; voltage (V)
Carrier VCXO AFCV - b b off a (1) Apply 6.5MHz, 200mVp-p CW to pin 7. -2000 0 2000 Hz
Frequency vs Power (2) Measure carrier VCXO frequency at
Supply Vcc=VDD=4.5~5.5V. (*B)
AFCV is the max. frequency change.
Carrier VCXO AFCT - b b off a (1) Appiy 6.5MHz, 200mVp-p CW to pin 7. - - 400 Hz
Frequency vs (2) Measure carrier VCXO frequency at
Temperature Ta = - 20-65''C. (*B)
Characteristics AFCV is the max. frequency deviation
from 25°C value.
Carrier fpcQ - b b off a (1) Appiy 6.5MHz, 200mVp-p CW to pin 7. 1600 i 1000 - Hz
Regeneration PLL (2) Sweep pin7 frequency and note pull-in
PuII-in Rage. and hold lange. (*B)
Carrier fhcQ - b b off a 1600 11000 - Hz
Regeneration PLL
Hold Range
(*B)Method of measureing Carrier VCXO frequency.
(1) Stop the Clock VCXO oscilator. (Connect CL-VCXO-l2 (pin 1) to GND)
(2) Apply 6.5MHz, 200m1/p-p CW to pin 7.
(3) Measure frequency at TP4 (CH-A-OUT (pin 9)).
This is difference between input frequency (6.552MH2) and carrier VCXO
frequency.
20 2001-06-19
SYM- TEST
TEST ITEM BOL CIR- SWITCH TEST CONDITION MIN. TYP. MAX. UNIT
Clock VCXO Control AFk - b off (1) Measure control range of Clock VCXO + 1.5 12.0 - kHz
Rage frequency by applying control voltage
CL-APC-F (pin 16) through a 10k0
resistor.
(2) This control voltage is 1.6~3.4V DC at
CL-APC-FO (pin 4).
Cl i CL APC FO
10m 0 CL APC Fl
(3) Measure frequency difference between
Clock VCXO frequency and 11.648MHz.
AFk =11.648-f (1.6)
=11.648-f (3.4)
A f (1.6)
E __________
g. AFk
>, ------ 11.648MHZ
[if f (3.4)
1 6 3.4 CL APC FO (V)
Clock VCXO AFkV - b off Measure Clock VCXO frequency at -2000 0 2000 Hz/V
Frequency vs Power Vcc=VDD=4.5~5.5V. CC)
Supply AFKV is the max. frequency change.
Clock VCXO AFkT - b off Measure Clock VCXO frequency at Ta-- - - - 1300 Hz
Frequency Temp. 20--65''C. CC)
Characteristics AFKT is the max. frequency change.
Clock Regeneration fpk - a off (1) Apply 364kHz, 0.7Vp_p CW to TP6. 12000 13000 - Hz
PLL Hold Range (2) Sweep TP6 frequency and note pulI-in
Clock Regeneration fhk - a off and hold range. (*C) 12000 13000 - Hz
PLL PuII-in Range
(*C)Method of measuring Clock VCXO frequency.
Outputtest signalto MCLK (pin 68) by O-BS of " (address B4H, sub-address 1).
Thistest signal's frequency is half of clock VCXO frequency
2001 -06-1 9
TOSHIBA TB1212N/F
AC CHARACTERISTIC (2)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
SCL Clock Frequency fSCL - fscL=1/TSCL 0 - 100 kHz
SCL High Level tSH - CL=400pF 4.0 - - ps
SCL Low Level tSL - CL=400pF 4.7 - - ps
Data Setup Time tDS - CL=400pF 250 - - ns
Data Hold Time tDH - CL=400pF 5.0 - - ps
Transmittion Start Condition
Hold Time tSCH - CL=400PF 4.0 - - #5
Transmittion Stop Condition
Hold Time tECS - CL=400PF 4.7 - - ps
Data Transmittion Interval tBUF - CL=400pF 4.7 - - [15
" Time tlr - CL=400pF - - 1.0 ps
IZC Fall Time tif - CL=400pF - - 300 ns
AC CHARACTERISTIC (3)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Digital Filter Pass Band
Width Ripple DFpr - - - 0.2 - dB
Digital Filter Pass Band Dpr - GAIN - 1dB frequency - 15.0 - kHz
Digital Filter Attenuation DFrr - - - -40.0 - dB
Digital De-emphasis
Characteristics Error DEer - - - 0.5 - dB
Pc BUS TIMING CHART
wa/i-iN, / >< )( l /'"
tSCH tSL tSH
Purchase of TOSHIBA " components conveys a license under the Philips " Patent Rights to use these
components in an IZC system, provided that the system conforms to the " Standard Specification as
defined by Philips.
22 2001-06-19
TOSHIBA TB1212N/F
X'tal Specification
(1) 11.648MH2
Maker : TOKYO DENPA COMPANY, LTD.
Type : TR49(11.648MHZ)
Specification : load capacity LC=16pF
temperature characteristic i30ppm (- 10 to 70°C)
frequency deviation RT= t30ppm
resistance CI = 250
parallel capacity CO = ~7.0pF
(2) 6.552MHZ
Maker : TOKYO DENPA COMPANY, LTD.
Type : TR49(6.552MHz)
Specification : load capacity LC=16pF
temperature characteristic i30ppm (- 10 to 70°C)
frequency deviation RT= i30ppm
resistance CI = 500
parallel capacity CO = ~7.0pF
(3) 5.85MH2
Maker : TOKYO DENPA COMPANY, LTD.
Type : TR49(5.85MHz)
Specification : load capacity LC=16pF
temperature characteristic i30ppm (- 10 to 70°C)
frequency deviation RT= t30ppm
resistance CI = son
parallel capacity CO = ~7.0pF
23 2001-06-19
TOSHIBA
TEST CIRCUIT 1 (Digital de-emphasis)
MUTE GAIN
e MUTE LVL
Ji, Co] N.C
3-32 R3 Cot
N C 6 N.C
g g 3-l CL vcxo o
A 55: c eCL vcxo 12
F 4 iEIIIII><
'" ,_ col vcxo "
r- R c ®CL APC F0
-NVV-IF-a "di CL APC Fl
C6 +5v
-M-a- 0 @A Vcc
QPSK IN Wm R9 B.P.F) c7 OE @QPSK IN
R3 c0 ®AGC FILTER
+5VC TMC m c @CHAOUT
SW6 TP6 C11 1-®CH B OUT
CAAPCDC0-essd 0' -. OCHBIN
+5V c C12 C", a 4 ®CH A IN
13 9,-P-aosFs
mTP7 ®CA APC F
C14 R11 0. R15
'- c Hal ®CA vcxo o
it-, Iii' CA vcxo 1
jfr_6552MHz C
- . d? 16 @211 cm
g1 , sw Jo ®N.C
Ci)y T. ', @FM/PCM
Ci2y-o6o + 5V 0 Ciii DAC VDD
a D- 0, Cis' DOUT R
Ps (io) U a DOUT R
19 'gg' DAC GND
N 18 Citi DAC GND
< 17 c, Ciii DOUT L
F- 16 U Q DOUT L
D-t + 5v 0 Cai' DAC VDD
lit “Ema
Q.71 +9V AMUTE
CC) + + -
N .. "'H'--t
tu; I C25
About TA2047N
TB1212N
TB1212N/F
STEREO‘
G LED4
SERR LEDS
PERR LED6
MUTEOUT
MUTEIN
@@@Tfsst
@Qi’xfi)?
1. It is require to connect ceramic or film condenser not to receive temperature
characteristics. (*1)
2. Pin 7 to be open. (Don't connect to GND or VCC)
3. It is require to other writing GND line of pin 18, 19 and pin 15.
4 C38 connect between pin 6 and pin15.
2001 -06-1 9
TOSHIBA
TEST CIRCUIT 2 (Analog de-emphasis)
MUTEGAIN
e MUTE LVL
Ji, Co] N.C
3-32 13, Cot
N C 6 NC
g g 3-1 CL vcxo o
A Tr=C, c L‘CL vcxo 12
'" ,_ col vcxo "
r- R c ®CL APC F0
"tr"-" "di CL APC Fl
-M-a- 0 @A Vcc
QPSK IN m7 OE @QPSK IN
R3 c: ®AGC FILTER
+5VC TMC m c @CHAOUT
C11 _ ®CH B OUT
CA APC DC cr-sl/is TP6o-, ,b
.- (5cm BIN
. _ _ +5V C12 b a SW4
de-emphasis circuit C13 o-u :5 Cli' CH A IN
TP7 Cis) CA APC F
C14 R11 a. R15 C20DcAvcxoo
", C15 X'tal
, il it-, Ciii' CA vcxo l
, F 6.552MHZ
. - Cr, C15 @A GND
Dr sw Jo eBrmC
Ci)y Ir ', C2? m/PCM
Ci2y-o6o + 5V 0 Ciii DAC VDD
a D- 0, Cis' DOUT R
Ps (io) U a DOUT R
CD 19 'gg' DAC GND
N 18 Citi DAC GND
< 17 c, Ciii DOUT L
F- 16 U Q DOUT L
D-t + 5v 0 Cai' DAC VDD
lit "l.?,';
A AMUTE
Q.71 +9V
CC) + + -
N .. "'H'--t
tu; I C25
.."- de-emphasis circuit
About TA2047N
TB1212N
TB1212N/F
STEREO‘
G LED4
SERR LEDS
PERR LED6
MUTE OUT
MUTE IN
@@@Tfsst
@Qi’xfi)?
1. It is require to connect ceramic or film condenser not to receive temperature
characteristics. (*1)
2. Pin 7 to be open. (Don't connect to GND or VCC)
4. C38 connect between pin 6 and pin 15.
It is require to other writing GND line of pin 18, 19 and pin15.
2001 -06-1 9
2001 -06-1 9
TEST CIRCUIT 3 (Digital de—emphasis)
t..-yt,
(TA2047F : Vcc - 9V) C1
3" MUTE GAIN ‘
:23 mm
ft szavsru
wmmwaaamem ®®®®®®
'tli J
a)000g]
TP‘I ' 27PF
39m ca c.47,uF +5v
3900 C7 0.01 r
QPSK INO—w—IE II F
R9 mm 0.1 ,1:
R10 (-
“3 +sv 0 IPA . LEDS
“27 Rzz~27 : 3300
CC Jr, E3 [ti, (£3
:IZLZLSL
'1 13k0. n15 X'tal
Iv 24pF s.sszmgz
5W5 ha I
. ' + 5V
,8 +5V
OQMGGOGOQBGGQQQSQQQQGHEH'S
3'M'Mh0MrM'MhtllMMMhWf'htiMr-2
J, g- «+st
é: HZ?T?T:@@@@@?@@®
:ILVOZVJ.
It is require to connect ceramic or film condenser not to receive temperature characteristics. (*4)
Pin 7 to be open. (Don’t connect to GND or V C
It is require to other writing GND line of pin 1%, 19 and pin 15.
. C33 connect between pin 6 and pin15.
.crsirvid
TB1212N/F - 26
TOSHIBA
TB1212N/F
2001 -06-1 9
TEST CIRCUIT 4 (Analog de-e'mphasis)
(TA2047F : Vcc - 9V)
”‘Ll—‘fi.
QPSKING I a.” I
“9 4700 I
CA APC DC H
+5VC ' l
De-emphasls DAMP 39k!)
. E - . .
1 13k0 ETC“ OJpF 3“— Clrcmt
R41 5 352 3900 “g
3300pF1kQE R 1...
(453.. : 33m"... 5
: .851. ‘1
:1 10,1;
STS 23
0 F“ 3% _C +
AOUTR 7 0‘3
C37 mdm ""1
F 220!)
,9 znwsvsru
39m Ca 0.47m tsv
C; 0.01,»
220m. 0.1;;
R8 +5V o 10 9
001 F C12
C14 R11
6552an
SW; gl'° M c
a 10pF
—06dB l
R18 C 9
470m; FM R
533 13 r?
3“ 1o;
gdotmt
sdoom (Wo
:ILVOZVJ.
NMQMOBDM
10 kanfizo M1
A OUT L 10 15
..1kfl 10;_IF
‘t 11 14
M UTE GAIN
wwmmqnmmmm
gerebt11
Eito tpor
ce, CW, G)
R27 n22-” : 3300
68688$8®®66968886
@®@@€E 00$®®€E®®€E®®
“‘33 C44
§;Cs1 0-11“: 7— Circuit
T8121 ZNIF - 27
‘ De—qm phasis 3-
About TA2047F
'f.i',tv,'
o. 923
grtt 0
‘I. It is require to connect ceramic or film condenser not to receive temperature characteristics. (*1)
2. Pin 7 to be open. (Don't connect to GND or V C)
It is require to other writing GND line of pin 1%, 19 and pin 15.
4. C33 connect between pin6 and pin15.
TOSHIBA
TB1212N/F
TOSHIBA TB1212N/F
APPLICATION CIRCUIT 1 (Digital de-emphasis)
MUTE GAIN
D VDD 64 +5V
RDATA® ichs
NC RCLK D
N.C MCLK ED
N.C REiETCio)-
N.C TEsrID-t
_ CL VCXO o TEST2(iir-t
*2 "rt CL vcxo 12 TEST3D-t
CL vcxo " D GND D-t LEDI
CL APC FO STEREO‘ + 5V
CL APC Fl MONO1 LED2
*1 A Vcc MONO? LED3
QPSK IN o-tit-is] QPSK IN c7 LED4
'i2"-dUf 6 AGC FILTER a SERR LEDS
R4 C8 N
+ 5v CH A OUT PERR LED6
CH B OUT DDATAZ©
+ 5V CH B IN '- DGATE 219
CH CH A IN a: D GND D-t
CA APC F r- MUTE ouTCi6)-,
C12 R7 5
CA vcxo o MUTE IN D-'
CA vcxo 1 SEL1 D-t
- "U 6.552MH2 1"'yf2rii/,), GND $sz
@1 Q; N.C DESELD-t
D-(iii" m/PCM sDA(i)-o )
-CON I/F
@mOsdB + 5V o-(i3 DAC VDD scLD-o /d
a 21 26 DOUT R DATA 39
Ps 3 g; - O
(io) U 27 DOUT R BCK (ii)
CD 19 t-(iii DAC GND LRCK D
N 18 it-aio/sc GND D voDCi6)-o +5V
< 7 m DOUT L ZDATA@
F- D- U 31 DOUT L 2BCK D
j} + 5v o-a) DAC VDD 2LRCK D
Ch R16 AMUTE
19 9V "dt-dp
C) + *1 BPF : TOKO, INC.
.. + -i-t TH316BQM-2110QDAF (Carrier vcxo X'tal 6.552MHZ)
g; I C15 TH31SBQM-2080QDAF (Carrier VCXO X'tal 5.85MH2)
U *2, *3 X'tal : TOKYO DENPA COMPANY. LTD TR49
*4 13m
About TA2047N
1. It is require to connect ceramic or film condenser not to receive temperature
characteristics. (*4)
Pin 7 to be open. (Don't connect to GND or V C)
It is require to other writing GND line of pin1c8, 19 and pin 15.
C38 connect between pin 6 and pin15.
28 2001-06-19
TOSHIBA
TB1212N/F
APPLICATION CIRCUIT 2 (Analog de-emphasis)
MUTE GAIN
D VOD 64 R +5v
RDATA® +
RCLK D
MCLK D
RsirrCr0D-
TEsrID-t
TEST2D-t
*2 TEST? O-t
D GND D-t LED1
STEREO + 5V
CL APC Fl MONO1 LED?
*1 -' A Vcc MONO? LED?
QPSK IN o-pt-IB/FI " nQPSK IN c LED4
5 Re -
'tu-r,",-'] C AGC FILTER a s LEDS
4 8 N -
+5v CH A OUT PERR LED6
T- R27
CH B OUT N DDATA®
CH B IN T" DGATE®
de-emphasis circuit C11 CH A IN m D GND D-t
CA APC F I- MUTE ourcis)-,
c 20 CA vcxo o MUTE IN cis)-'
C-s-ct-ips vcxo l SEL1 Ci)-t
X'ta|3_l
:56 6.552MHz 3C14JCA GND 5'5sz
bi ffi, 3N.C DESEL D-o + 5V
D- 4F_M/PCM sDACi)-o )
-CON l/F
A OUT R @mowa +5v L't22ii'i1/ VDD scLD-o ’u
a 21 26 DOUT R DATA 39
Ps 3 a Cis)
Cioy U 27 DOUT R BCK D
o 19 DAC GND LRCK D
N DAC GND D VDD Cis)-o +5v
< 7 DOUT L 2DATA Ci)
_ cy U 31 DOUT L 2BCK Cia)
D-t oss/cr-aio/sc VDD 2LRCK®
l9 +5v 'hv-omutrrE
D- + + - *1 BPF : TOKO, INC.
{34 .. -Hi=t TH3168QM-2110QDAF (Carrier vcxo X'tal 6.552MHz)
u J ' C15 TH31GBQM-2080QDAF (Carrier VCXO X'tal 5.85MHz)
*2, *3 X'tal : TOKYO DENPA COMPANY. LTD TR49
N *4 13kn
i-- de-emphasis circuit
About TA2047N
characteristics. (*4)
2. Pin 7 to be open. (Don' t connect to GND or V
3. It is require to other writing GND line of pin1
4 C38 connect between pin 6 and pin 15.
It is require to connect ceramic or film condenser not to receive temperature
1C8,19 and pin15.
2001 -06-1 9
APPLICATION CIRCUIT 3 (Digital de-emphasis)
””04": : Vcc-QV)
TB1212N/F- 30
,3 xnwavsru
Sig J:
39“} C5 0.47,;F ,5v
C7 0.01 F
opsx m am in "
R9 4700 22mm. 0.1/1F
R10 C-
:ILVOZVL
“8 +sv 0
C8 0.01pF
0.47,“!:
0.01 [1F
C14 R11 1.8kn
R15 X'Ll .3
6.552MH:
IU Z4pF c
5w; *1: I
If +5 9
900909699999899866’6969
@wwmmmm
MUTE GAIN
geo um
am ®®®®®®
drrebt11
CtD0'00t,)0Q
[itil,:,):,
Cf'i)0,i,
R w LEDE
27 R22~27 : 3300
j,iij,
'ldMR,
Clf0Ct',D67,)0r,00itD6'r0CtrhtiD6O600r0Cg0W)0-p,
. OAMUTE About TA2047F
- k? 1. It is require to connect ceramic or film condenser not to receive temperature characteristics. (*4)
’1 2. Pin 7 to be open. (Don't connect to GND or V C
3. It is require to other writing GND line of pin1cs, 19 and pin 15.
4. C38 connect between pin6 and pin15.
@®@®@3 ®@@
'1 BPF : TOKO. INC.
> TH31SBQM-2’I1OQDAF (Carrier VCXO X'tal 6.552MHz)
+ TH31SBQM-ZOBOQDAF (Carrier VCXO X'tal 5.85MHz)
'2, '3 X"a| : TOKYO DENPA COMPANY. LTD TR49
'4 13kn
TOSHIBA
TB1212N/F
2001 -06-1 9
APPLICATION CIRCUIT 4 (Analog de-emphasis)
(TAZOUF : Vcc - 9V)
gy 1HWBV§H
llH---
223 mm
MUTE GAIN *
. . ‘f’
®®®®d§®®®®
391:0 C. 0.47yF tsv
3909 C7 0.01m
opsx m R 3.9.: 0 1|
9 4700 22°“ 0-1/1F
R5 + 5V 0 1 I
ca 0.01 pF
0.47/11:
0.01;:F
0.01 F
De—em phisis 0-47}1F 39kg
Circu‘n _
C14 R11 1.8K“
R15 X’tal e3
24pF 6 552 C2
adoom 053
gt#0etfl
St l E l 81
°®M°0900998®99999®®6~®3
®®®®®©
ce, Cf,','", Ct,'] 15 J',']
R27 R22~27 : 330“
}p-C0N l/F
1fMM'aBhfFMi,1fi'r'MMMM'r'Mt1LF'MME
(BG‘BQ‘ED‘DGQ’QGDQQHDQ‘ECD
TB1212N/F - 31
v v OAMUTE
+9v| 524*?
.3152 * S ' About TA2047F
"- ’3 "" c 1. It is require to connect ceramic or film condenser not to receive temperature characteristics. (*4)
2. Pin 7 to be open. (Don't connect to GND or V C
mphasis 3. It is require to other writing GND line of pin 1%, 19 and pin 15.
0W” 4. C38 connect between pin6 and pin15.
'1 aPF : TOKO. INC.
THa1sBQM-211OQDAF (Carrier vcxo X'tal 6.552MH1)
THJISBQM-ZOBOQDAF (Carrier vcxo X'tal 5.85MHz)
'2, '3 X’tal : Toxvo DENPA COMPANY. LTD TR49
'4 13m
TOSHIBA
TB1212N/F
TOSHIBA TB1212N/F
PACKAGE DIMENSIONS
SDIP64-P-750-1.78 Unit : mm
64 _ 33 .m
C1C1rOC1tOiOr-1r-1r-1rOrOrOt-1r-1t-1t-1rOr-1rV1r-tr-1r-1i-Tr-1r1r-nr-1t-nt-Tr-Tr-t - 0
r-lt-lt-ICICI/lull..)....):]))))..."-))...)).-:)..,),."..;.)))-) Irl ad
l mm 0
58.0MAX
57.5t0.2
w iii?
|4- mt, CD.
a d CD
m rig.
, , 1.0k0.1 'l 0.46t0.1 [j51EfiiE
1.191TYP 1.7_78l
Weight : 8.85g (Typ.)
32 2001-06-19
TOSHIBA TB1212N/F
PACKAGE DIMENSIONS
QFP80-P-1420-0.80A Unit : mm
1 .OTYP
‘2.7:i:Q12
, ,V 'l
‘ 3.05MAX
0.2i0.1
0,15 100.05
l l 1.2h0.2
Weight .' 1.6g (Typ.)
33 2001-06-19
TOSHIBA TB1212N/F
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
34 2001-06-19
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