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OP285GP-OP285GS
Dual 9 MHz Precision Operational Amplifier
REV. A
Dual 9 MHz Precision
Operational Amplifier
PIN CONNECTIONS
8-Lead Narrow-Body SO (S-Suffix)
8-Lead Epoxy DIP (P-Suffix)The combination of low noise, speed and accuracy can be used
to build high speed instrumentation systems. Circuits such as
instrumentation amplifiers, ramp generators, bi-quad filters and
dc-coupled audio systems are all practical with the OP285. For
applications that require long term stability, the OP285 has a
guaranteed maximum long term drift specification.
The OP285 is specified over the XIND—extended industrial—
(–40°C to +85°C) temperature range. OP285s are available in
8-pin plastic DIP and SOIC-8 surface mount packages.
FEATURES
Low Offset Voltage: 250 �V
Low Noise: 6 nV/√ Hz
Low Distortion: 0.0006%
High Slew Rate: 22 V/�s
Wide Bandwidth: 9 MHz
Low Supply Current: 5 mA
Low Offset Current: 2 nA
Unity-Gain Stable
SO-8 Package
APPLICATIONS
High Performance Audio
Active Filters
Fast Amplifiers
Integrators
GENERAL DESCRIPTIONThe OP285 is a precision high-speed amplifier featuring the
Butler Amplifier front-end. This new front-end design com-
bines the accuracy and low noise performance of bipolar
transistors with the speed of JFETs. This yields an amplifier
with high slew rates, low offset and good noise performance
at low supply currents. Bias currents are also low compared
to bipolar designs.
The OP285 offers the slew rate and low power of a JFET
amplifier combined with the precision, low noise and low
drift of a bipolar amplifier. Input offset voltage is laser-trimmed
and guaranteed less than 250 µV. This makes the OP285 useful
in dc-coupled or summing applications without the need for
special selections or the added noise of additional offset
adjustment circuitry. Slew rates of 22 V/µs and a bandwidth
of 9 MHz make the OP285 one of the most accurate medium
speed amplifiers available.
*Patents pending
OP285–SPECIFICATIONS(@ Vs = �15.0 V, TA = 25�C, unless otherwise noted.)NOTELong-term offset voltage is guaranteed by a 1,000 hour life test performed on three independent wafer lots at 125°C, with an LTPD of 1.3.
Specifications subject to change without notice.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP285 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±22 V
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . ±7.5 V
Output Short-Circuit Duration to Gnd3 . . . . . . . . . Indefinite
Storage Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP285G . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 Sec) . . . . . . . .300°C
NOTESAbsolute Maximum Ratings apply to packaged parts, unless otherwise noted.For supply voltages less than ±7.5 V, the absolute maximum input voltage is
equal to the supply voltage.Shorts to either supply may destroy the device. See data sheet for full details.�JA is specified for the worst case conditions, i.e., �JA is specified for device in
socket for cerdip, P-DIP, and LCC packages; �JA is specified for device soldered
in circuit board for SOIC package.
ORDERING GUIDE*Not for new designs. Obsolete April 2002.
OP285 TPC 1. Output Voltage Swing vs.
Supply Voltage
TPC 4. Slew Rate vs. Temperature
TPC 7. Common-Mode Rejection
vs. Frequency
TPC 2. Open-Loop Gain
vs. Temperature
TPC 5. Closed-Loop Gain
vs. Frequency
TPC 8. Power Supply Rejection
vs. Frequency
TPC 3. Slew Rate vs. Differential
Input Voltage
TPC 6. Closed-Loop Output Imped
ance vs. Frequency
TPC 9. Open-Loop Gain, Phase
vs. Frequency
TPC 10. Gain Bandwidth Product,
Phase Margin vs. Temperature
TPC 13. Maximum Output Swing
vs. Frequency
TPC 16. Input Bias Current vs.
Temperature
TPC 11. Small-Signal Overshoot vs.|
Load Capacitance
TPC 14. Supply Current vs.
Supply Voltage
TPC 17. Current Noise Density vs.
Frequency
TPC 12. Maximum Output Voltage
vs. Load Resistance
TPC 15. Short Circuit Current vs.
Temperature
TPC 18. tC VOS Distribution
OP285 TPC 19. Input Offset (VOS)
Distribution
TPC 22. Negative Slew Rate
RL =2 kΩ, VS = ±15 V, AV = +1
TPC 25. OP285 Voltage Noise Density
vs. Frequency VS = ±15 V, AV = 1000
TPC 20. Settling Time vs. Step Size
TPC 23. Positive Slew Rate
RL = 2 kΩ, VS = ±15 V, AV = +1
TPC 21. Slew Rate vs.
Capacitive Load
TPC 24. Small Signal Response
RL =2 kΩ, VS = ±15 V, AV = +1
APPLICATIONS
Short-Circuit ProtectionThe OP285 has been designed with inherent short-circuit
protection to ground. An internal 30 Ω resistor, in series with
the output, limits the output current at room temperature to
ISC+ = 40 mA and ISC- = –90 mA, typically, with ±15 V supplies.
However, shorts to either supply may destroy the device when
excessive voltages or current are applied. If it is possible for a
user to short an output to a supply, for safe operation, the out-
put current of the OP285 should be design-limited to ±30 mA,
as shown in Figure 1.
Figure 1. Recommended Output Short-Circuit Protection
Input Over Current ProtectionThe maximum input differential voltage that can be applied
to the OP285 is determined by a pair of internal Zener diodes
connected across the inputs. They limit the maximum differ-
ential input voltage to ±7.5 V. This is to prevent emitter-base
junction breakdown from occurring in the input stage of the
OP285 when very large differential voltages are applied. How-
ever, in order to preserve the OP285’s low input noise
voltage, internal resistance in series with the inputs were not
used to limit the current in the clamp diodes. In small-signal
applications, this is not an issue; however, in industrial appli-
cations, where large differential voltages can be inadvertently
applied to the device, large transient currents can be made to
flow through these diodes. The diodes have been designed to
carry a current of ±8 mA; and, in applications where the
OP285’s differential voltage were to exceed ±7.5 V, the resis-
tor values shown in Figure 2 safely limit the diode current to8 mA.
Figure 2. OP285 Input Over Current Protection
Output Voltage Phase ReversalSince the OP285’s input stage combines bipolar transistors
for low noise and p-channel JFETs for high speed performance,
the output voltage of the OP285 may exhibit phase reversal if
either of its inputs exceed its negative common-mode input
voltage. This might occur in very severe industrial applications
where a sensor or system fault might apply very large voltages on
the inputs of the OP285. Even though the input voltage range of
the OP285 is ±10.5 V, an input voltage of approximately –13.5 V
applications, the fix is a simple one and is illustrated in Figure 3.
A 3.92 kΩ resistor in series with the noninverting input of the
OP285 cures the problem.
Figure 3. Output Voltage Phase Reversal Fix
Overload or Overdrive RecoveryOverload or overdrive recovery time of an operational amplifier
is the time required for the output voltage to recover to a rated
output voltage from a saturated condition. This recovery time is
important in applications where the amplifier must recover quickly
after a large abnormal transient event. The circuit shown in Figure
4 was used to evaluate the OP285’s overload recovery time. The
OP285 takes approximately 1.2 µs to recover to VOUT = +10 V
and approximately 1.5 µs to recover to VOUT = –10 V.
Figure 4. Overload Recovery Time Test Circuit
Driving the Analog Input of an A/D ConverterSettling characteristics of operational amplifiers also include the
amplifier’s ability to recover, i.e., settle, from a transient output
current load condition. When driving the input of an A/D
converter, especially successive-approximation converters, the
amplifier must maintain a constant output voltage under
dynamically changing load current conditions. In these types of
converters, the comparison point is usually diode clamped, but
it may deviate several hundred millivolts resulting in high
frequency modulation of the A/D input current. Amplifiers that
exhibit high closed-loop output impedances and/or low unity-gain
crossover frequencies recover very slowly from output load
current transients. This slow recovery leads to linearity errors or
missing codes because of errors in the instantaneous input voltage.
Therefore, the amplifier chosen for this type of application should
exhibit low output impedance and high unity-gain bandwidth so
that its output has had a chance to settle to its nominal value
before the converter makes its comparison.
The circuit in Figure 5 illustrates a settling measurement circuit
for evaluating the recovery time of an amplifier from an output
load current transient. The amplifier is configured as a follower
with a very high speed current generator connected to its output.
In this test, a 1 mA transient current was used. As shown in
Figure 6, the OP285 exhibits an extremely fast recovery time of
OP285Figure 5. Transient Output Load Current Test Fixture
Figure 6. OP285’s Output Load Current Recovery Time
Measuring Settling TimeThe design of OP285 combines high slew rate and wide gain-
bandwidth product to produce a fast-settling (ts < l µs) amplifier
for 8- and 12-bit applications. The test circuit designed to measure
the settling time of the OP285 is shown in Figure 7. This test
method has advantages over false-sum node techniques in that
the actual output of the amplifier is measured, instead of an
error voltage at the sum node. Common-mode settling effects
are exercised in this circuit in addition to the slew rate and
bandwidth effects measured by the false-sum-node method. Of
course, a reasonably flat-top pulse is required as the stimulus.
The output waveform of the OP285 under test is clamped by
Schottky diodes and buffered by the JFET source follower.
The signal is amplified by a factor of ten by the OP260 and
then Schottky-clamped at the output to prevent overloading
the oscilloscope’s input amplifier. The OP41 is configured as
a fast integrator which provides overall dc offset nulling.
High Speed OperationAs with most high speed amplifiers, care should be taken with
supply decoupling, lead dress, and component placement. Rec-
ommended circuit configurations for inverting and noninverting
applications are shown in Figures 8 and Figure 9.
