OP270 ,Dual Very Low Noise Precision Operational AmplifierSPECIFICATIONSOP270A/E OP270F OP270GPARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX ..
OP270 ,Dual Very Low Noise Precision Operational AmplifierSPECIFICATIONS AOP270E OP270F OP270GPARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX ..
OP270AZ ,18V; 25mA; dual very low-noise precision operational amplifierGENERAL DESCRIPTION
5nV/V Hz at 1kHz Max, offering comparable performance
to PMI's industry sta ..
OP270EZ ,Dual Very Low Noise Precision Operational AmplifierSPECIFICATIONSS AOP270E OP270F OP270GPARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MA ..
OP270FZ ,18V; 25mA; dual very low-noise precision operational amplifierfeatures an input offset voltage below 75/1V and
an offset drift under 1yV/°C, guaranteed over the ..
OP270GP ,18V; 25mA; dual very low-noise precision operational amplifierCHARACTERISTICS at Vs = i15V, TA = +25°C, unless otherwise noted. Continued
OP-270A/E OP-27OF OP ..
P3100SCMCLRP , MC Series DO-214 are low capacitance SIDACtor® devices designed to protect
P3100SCMCLRP , MC Series DO-214 are low capacitance SIDACtor® devices designed to protect
P3100SCRP , Low voltage overshoot, Low on-state voltage, Low capacitance
P3100SCRP , Low voltage overshoot, Low on-state voltage, Low capacitance
P3100SCRP , Low voltage overshoot, Low on-state voltage, Low capacitance
P3100SCRP , Low voltage overshoot, Low on-state voltage, Low capacitance
OP270
Dual Very Low Noise Precision Operational Amplifier
REV. B
Dual Very Low Noise Precision
Operational Amplifier
FEATURES
Very Low Noise5nV/÷HzHzHzHzHz @ 1kHz Max
Excellent Input Offset Voltage 75 �V Max
Low Offset Voltage Drift1�V/�C Max
Very High Gain 1500 V/�V Min
Outstanding CMR 106 dB Min
Slew Rate 2.4V/ms Typ
Gain-Bandwidth Product5 �Hz Typ
Industry Standard 8-Lead Dual Pinout
FUNCTIONAL BLOCK DIAGRAM
(One of Two Amplifiers Is Shown)
GENERAL DESCRIPTIONThe OP270 is a high-performance monolithic dual operational
amplifier with exceptionally low voltage noise, 5n÷Hz at 1kHz Max,
offering comparable performance to ADI’s industry standard OP27.
The OP270 features an input offset voltage below 75 mV and an
offset drift under 1 mV/∞C, guaranteed over the full military tempera-
ture range. Open-loop gain of the OP270 is over 1,500,000 into akW load insuring excellent gain accuracy and linearity, even in
high-gain applications. Input bias current is under 20nA which
reduces errors due to signal source resistance. The OP270’s CMR of
over 106dB and PSRR of less than 3.2 mV/V significantly reduce
errors due to ground noise and power supply fluctuations. Power
consumption of the dual OP270 is one-third less than two OP27s,
a significant advantage for power conscious applications. The
OP270 is unity-gain stable with a gain bandwidth product of 5 MHz
and a slew rate of 2.4 V/ms.
The OP270 offers excellent amplifier matching which is important
for applications such as multiple gain blocks, low noise instrumen-
tation amplifiers, dual buffers, and low-noise active filters.
The OP270 conforms to the industry standard 8-lead DIP pinout. It
is pin-compatible with the MC1458, SE5532/A, RM4558, and
HA5102 dual op amps, and can be used to upgrade systems using
these devices.
For higher speed applications the OP271, with a slew rate of 8V/ms, is
recommended. For a quad op amp, see the OP470.
CONNECTION DIAGRAMS
16-LEAD SOL
(S-Suffix)
EPOXY MINI-DIP (P-Suffix)
8-LEAD HERMETIC DIP
(Z”Suffix)
OP270–SPECIFICATIONSNOTES
1. Guaranteed by not 100% tested.
2. Sample tested.
3. Guaranteed by CMR test.
Specifications subject to change without notice.
(Vs =�15
V, TA=25�C, unless otherwise noted.)
OP270SPECIFICATIONS
* Guaranteed by CMR test.
Specifications subject to change without notice.
* Guaranteed by CMR test.
Specifications subject to change without notice.
ELECTRICAL SPECIFICATIONS(Vs =�15V, –55∞C£TA£125�C for OP270A, unless otherwise noted.)
ELECTRICAL SPECIFICATIONS (Vs =�15
V, –40∞C£
TA£
85�C, unless otherwise noted.)
OP270–SPECIFICATIONS
WAFER LIMITS(Vs =�15V,TA=25∞C, unless otherwise noted.)
DICE CHARACTERISTICS
1. OUT A
2. -IN A
3. +INA
4. V-
5. +IN B
6. -IN B=
7. OUT B
8. V+
Substrate is internally connected to V-
NOTE:
1.Guaranteed by CMR test.Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yields loss, yield
afler packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot
assembly and testing.
Specifications subject to change without notice.
DIE SIZE 0.094 x 0.092 inch, 8,648 sq. mils
(2.39 x 2.34 mm, 5.60 sq. mm)
OP270SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . .±1.0 V
Differential Input Current2 . . . . . . . . . . . . . . . . . . . .±25 mA
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .Supply Voltage
Output Short-Circuit Duration . . . . . . . . . . . . . . .Continuous
Storage Temperature Range
P, S. Z-Package . . . . . . . . . . . . . . . . . . . . . .–65∞C to +150∞C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . .300∞C
Junction Temperature (TJ) . . . . . . . . . . . . .–45∞C to +150∞C
Operating Temperature change
OP270A . . . . . . . . . . . . . . . . . . . . . . . . . . . .–55∞C to +125∞C
OP270E, OP270F, OP270G . . . . . . . . . . . . . .40∞C to +85∞C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP270 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDENot for new design, obsolete April 2002qJA is specified for worst-case mounting conditions, i.e., qJA is specified
for device in socket for Cerdip and P-DIP packages; qJA is specified for
device soldered to printed circuit board for SOL package.
NOTES:Absolute maximum ratings apply to both DICE and packaged pans,
unless otherwise noted.The OP270’s inputs are protected by back-to-back diodes.
Current limiting resistors are not used in order to achieve low noise
performance. lf differential voltage exceeds +10 V, the input current
should be limited to ±25 mA.
For Military processed devices, please refer to the Standard
Microcircuit Drawing (SMD) available at
www.dscc.dla.mil/programs/milspec/default.asp
*Not for new designs; obsolete April 2002.
OP270
TPC 1. Voltage Noise Density
vs. Frequency
TPC 4. Current Noise Density
vs. Frequency
TEMPERATURE – �C
INPUT BIAS CURRENT – nA
–252575
TPC 7. Input Bias Current vs.
Temperature
TPC 2. Voltage Noise Density
vs. Supply Voltage
TPC 5. Input Offset Voltage vs.
Temperature
TEMPERATURE – �C
INPUT OFFSET CURRENT – nA
–252575
TPC 8. Input Offset Current vs.
Temperature
TPC 3. TBD
TIME – Minutes
CHANGE IN OFFSET
GE –
12345
TPC 6. Warm-Up Offset Voltage
Drift
TPC 9. Input Bias Current vs.
Common-Mode Voltage
–Typical Performance Characteristics
FREQUENCY – Hz
CMR – dB
1101001k10k100k1M
100
TPC 10. CMR vs. Frequency
FREQUENCY – Hz
PSR – dB
140110010k1M100M1k100k10M
120
TPC 13. PSR vs. Frequency
TPC 16. Open-Loop Gain Phase
Shift vs. Frequency
SUPPLY VOLTAGE – V
L SUPPL
Y CURRENT – mA�5�10�15�20
TPC 11. Total Supply Current
vs. Supply Voltage
FREQUENCY – Hz
LTA
GAIN – dB
140110010k1M100M1k100k10M
120
TPC 14. Open-Loop Gain vs.
Frequency
SUPPLY VOLTAVE – V
OPEN-LOOP GAIN –
V/mV
4000�10�15�20�25
TPC 17. Open-Loop Gain vs.
Supply Voltage
TEMPERATURE – �C
L SUPPL
Y CURRENT – mA
–50050100
TPC 12. Total Supply Current
vs. Temperature
TPC 15. Closed-Loop Gain vs.
Frequency
TEMPERATURE – �C
PHASE MARGIN – DEG–75
–50–250255075100125150GAIN B
AND
WIDTH PR
ODUCT – MHz
TPC 18. Gain-Bandwidth Phase
Margin vs. Temperature
OP270
TPC 19. Maximum Output
Swing vs. Frequency
FREQUENCY – Hz
OUTPUT IMPED
ANCE – 1k100k10M
10k1M
TPC 22. Output Impedance vs.
Frequency
FREQUENCY – Hz
DIST
TION – %
0.0011010k
0.01
TPC 25. Total Harmonic Distor-
tion vs. Frequency
LOAD RESISTANCE – �
MAXIMUM OUTPUT – 1k10k10k
TPC 20. Maximum OUTPUT
Voltage vs. Load Resistance
TEMPERATURE – �C
SLEW RA
TE –
2.7
TPC 23. Slew Rate vs.
Temperature
TPC 26. Large Signal Transcient
Response
CAPACITIVE LOAD – pF
VERSHOO
T – %04001000
200600800
TPC 21. Small-Signal Over-
shoot vs. Capacitive Load
FREQUENCY – Hz
CHANNEL SEP
ARA
TION – dB11k1M
10k
100100k10
160
TPC 24. Channel Separation vs.
Frequency
TPC 27. Small-Signal
Transient Response
