OP215AJMDA ,Dual Precision JFET-Input Operational AmplifierApplications include high-speed amplifiers for current outputLow input offset voltages, low input c ..
OP215AZ ,Dual, JFET InputCHARACTERISTICS otherwise noted.) OP215E OP215GParameter Symbol Conditions Min ..
OP215BRC/883 ,DUAL PRECISION JFET-INPUT OPERATIONAL AMPLIFIERGENERAL DESCRIPTION
The OP-215 offers the proven JFET-input performance ad-
vantages of high sp ..
OP215EZ ,Dual Precision JFET-Input Operational AmplifierCHARACTERISTICS otherwise noted.) OP215E OP215GParameter Symbol Conditions Min ..
OP215FZ ,DUAL PRECISION JFET-INPUT OPERATIONAL AMPLIFIERApplications include high-speed amplifiers for current output
DACs, active filters, sample-and-hol ..
OP215GS ,DUAL PRECISION JFET-INPUT OPERATIONAL AMPLIFIERFEATURES
. ngh Slew Rate .......................... 10Wys Min
. Put Settling Time ............... ..
P3002CAL , gas plasma arresters-package dimensions/specifications
P3002CBL , gas plasma arresters-package dimensions/specifications
P3002SAL , gas plasma arresters-package dimensions/specifications
P3002SB , DO-214AA Package Symbolization
P3002SBL , gas plasma arresters-package dimensions/specifications
P3002SBLRP , TwinChip™ Series DO-214 are very low capacitance SIDACtor® devices designed
OP215AJMDA-OP215EZ
Dual Precision JFET-Input Operational Amplifier
REV.A
Dual Precision JFET-Input
Operational Amplifier
FEATURES
High Slew Rate: 10 V/�s Min
Fast Settling Time: 0.9 �s to 0.1% Type
Low Input Offset Voltage Drift: 10 �V/�C Max
Wide Bandwidth: 3.5 MHz Min
Temperature-Compensated Input Bias Currents
Guaranteed Input Bias Current: 18 nA Max (125�C)
Bias Current Specified Warmed Up over Temperature
Low Input Noise Current: 0.01 pA/÷Hz Type
High Common-Mode Rejection Ratio 86 dB Min
Pin Compatible with Standard Dual Pinouts
Models with MIL-STD-883 Class B Processing Available
GENERAL DESCRIPTIONThe OP215 offers the proven JFET-input performance advantages
of high speed and low input bias current with the tracking and
convenience advantages of a dual op amp configuration.
Low input offset voltages, low input currents, and low drift are
featured in these high-speed amplifiers.
On-chip zener-zap trimming is used to achieve low VOS, while a
bias-current compensation scheme gives a low input bias current
Figure 1.Simplified Schematic (1/2 OP215)
at elevated temperature. Thus, the OP215 features an input bias
current of 1.4 nA at 70∞C ambient (not junction) temperature
which greatly extends the application usefulness of this device.
Applications include high-speed amplifiers for current output
DACs, active filters, sample-and-hold buffers, and photocell
amplifiers. For additional precision JFET op amps, see the
OP249 and AD712 data sheets.
OP215–SPECIFICATIONS
ELECTRICAL CHARACTERISTICSNOTESInput bias current is specified for two different conditions. The Tj = 25∞C specification is with the junction at ambient temperature; the device operating specification is
with the device operating in a warmed up condition at 25∞C ambient. The warmed up bias-current value is correlated to the junction temperature value via the curves
of IS versus Tj and IS versus TA. PMI has a bias-current compensation circuit that gives improved bias current and bias current over temperature versus standard
JFET input op amps. IS and IOS are measured at VCM = 0.Setting time is defined here for a unity gain inverter connection using 2 kW resistors. It is the time required for the error voltage (the voltage at the inverting input pin
on the amplifier) to settle to within a specified percent of its final value from the time a 10 V step input is applied to the inverter. See setting time test circuit.Sample tested.
Specifications are subject to change without notice.
(at VS = ±15 V, TA = 25�C, unless otherwise noted.)
OP215
SPECIFICATIONS
ELECTRICAL CHARACTERISTICSNOTESSample tested.Input bias current is specified for two different conditions. The Tj = 25∞C specification is with the junction at ambient temperature; the Device Operating specification is
with the device operating in a warmed up condition at 25∞C ambient. The warmed up bias-current value is correlated to the junction temperature value via the curves
of IS versus Tj and IS versus TA. PMI has a bias-current compensation circuit that gives improved bias current and bias current over temperature versus standard
JFET input op amps. IS and IOS are measured at VCM = 0.
Specifications are subject to change without notice.
(at VS = ±15 V, 0�C � TA � 70�C for E Grade, –40�C � TA � +85�C for G Grade, unless
otherwise noted.)
OP215
ORDERING INFORMATION1For military processed devices, please refer to the standard microcircuit drawing
(SMD) available at www.dscc.dla.mil/programs/milspec/default.asp
NOTESBurn-in is available on commercial and industrial temperature range parts in CerDIP and plastic
DIP packages.Not for new design, obsolete April 2002.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP215 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1Supply Voltage
OP215E, OP215G . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Operating Temperature Range
OP215E . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0∞C to +70∞C
OP215G . . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C
Maximum Junction Temperature (Tj) . . . . . . . . . . . . . .150∞C
Differential Input Voltage
OP215E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±40 V
OP215G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±30 V
Input Voltage2
OP215E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±20 V
OP215G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±16 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . .Indefinite
Storage Temperature Range . . . . . . . . . . . .–65∞C to +150∞C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . .300∞C
Junction Temperature (Tj) . . . . . . . . . . . . . –65∞C to +150∞C
NOTESAbsolute maximum ratings apply to packaged parts, unless otherwise noted.Unless otherwise specified, the absolute maximum negative input voltage is equal
to one volt more positive than the negative power supply voltage.
*�JA is specified for worst-case mounting conditions, i.e., �JA is specified for
device in socket for CerDIP and P-DIP packages.
PIN CONFIGURATION
TPC 1.Large-Signal Transient
Response
TPC 4.Closed-Loop Bandwidth and
Phase Shift vs. Frequency
TPC 7.Maximum Output Swing vs.
Frequency
TPC 2.Small-Signal Transient
Response
TPC 5.Bandwidth vs. Temperature
TPC 8.Slew Rate vs. Temperature
SETTLING TIME �s
OUTPUT
GE SWING FR
OM 0V
10
0.51.01.52.02.5TPC 3.Settling Time
TPC 6.Open-Loop Frequency
Response
TPC 9.Common-Mode Rejection
Ratio vs. Frequency
OP215
BASIC CONNECTIONSFigure 2.Settling Time Test Circuit
Figure 3.Slew Rate Test Circuit
TPC 10.Power Supply Rejection vs.
Frequency
TPC 11.Output Impedance vs.
Frequency
TPC 12.Voltage Noise Density vs.
Frequency
Figure 4.Input Offset Voltage Nulling
