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OP15AJPMIN/a15avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP15AZPMIN/a5avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP15FPPMIN/a133avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP15FZPMIN/a2avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP15FZADN/a90avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP15GJADIN/a200avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP15GPPMIN/a368avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP15GSADIN/a52avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP15GSADN/a2288avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP15GZADN/a100avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP15GZADIN/a37avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP16BJ/883 |OP16BJ883AD/BBN/a6250avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP16EZADN/a9avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP16FJADN/a970avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP16FZPMIN/a150avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP16GSPMIN/a5avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP16GZN/a5avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP17AJADN/a10avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP17AZADN/a44avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP17AZPMIN/a39avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP17EZADN/a1574avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP17GJPMIN/a15avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
OP17GZADN/a3avaiPRECISION JFET-INPUT OPERATIONAL AMPLIFIERS


OP16BJ/883 ,PRECISION JFET-INPUT OPERATIONAL AMPLIFIERSapplications requiring high closed-loop gain with high speed. See the OP-42 data sheet for unity g ..
OP16EZ ,PRECISION JFET-INPUT OPERATIONAL AMPLIFIERSfeatures a slew rate of 25V/ps and a settling time of 900ns to 0.1% which represents a significant ..
OP16FJ ,PRECISION JFET-INPUT OPERATIONAL AMPLIFIERSFEATURES (All Devices) 0 Significant Performance Advantages over LF155, 156 and tttr Devices. ..
OP16FZ ,PRECISION JFET-INPUT OPERATIONAL AMPLIFIERSapplications. The OP-16
OP16GS ,PRECISION JFET-INPUT OPERATIONAL AMPLIFIERSfeatures a slew rate of 25V/ps and a settling time of 900ns to 0.1% which represents a significant ..
OP16GZ ,PRECISION JFET-INPUT OPERATIONAL AMPLIFIERSfeatures of low supply current coupled with an input bias current of 9nA at 125° C ambient (not ju ..
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P2824 , POWERLINE CARRIER ISOLATION TRANSFORMER
P28F001BX-B120 , 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY


OP15AJ-OP15AZ-OP15FP-OP15FZ-OP15GJ-OP15GP-OP15GS-OP15GZ-OP16BJ/883-OP16EZ-OP16FJ-OP16FZ-OP16GS-OP16GZ-OP17AJ-OP17AZ-OP17EZ-OP17GJ-OP17GZ
PRECISION JFET-INPUT OPERATIONAL AMPLIFIERS
ANALOG
DEVICES
Precision JFET-lnput
Operational Amplifiers
OP-IMP-IMP-IT
FEATURES (All Devices)
. Slgrtifleant Performance Advantages over LF155, 156 and
151 Devlces.
. Low Input Offset Voltage ................... 500W Max
. Low Input Offset Voltage Drift ................ 2.%Nl''tl
. Minimum Stew Rate Guaranteed on All Models
. Temperature-compensated Input Bias Currents
. Guaranteed Input Blas Current iii) 125°C
. Bias Current Specllled WARMED UP Over Temperature
. internal Compensation
. Low Input Noise Current .................. 0.01 pA/vTiz'
. High Common-Mode Rejection Ratlo ............ 100dB
. Models With MIL-STD-tm Processing Available
q 125°C Temperature Tested DICE
o 156 Speed With 155 Dissipation ............ (80mW Typ)
q Wide Bandwidth ................................ 6MHa
. High Slew Rate ................................. 13V/ps
D Fast Settling to ttht% .......................... 1200ns
q Available in Die Form
q Higher Slew Rate .............................. 25V/ps
. Faster Settling to :0.1% ........................ l 900ns
. Wider Bandwidth ............................... 8MHa
. Available in Die Form
q Highest Slew Rate ............................. 60V/ps
0 Fastest Settling to :0.1% ........................ 600tttt
0 Highest Gain Bandwidth Product (AVCL = 5 Min)
............................................ 30MHz
. Avallabie In Die Form
SIMPLIFIED SCHEMATIC
GENERAL DESCRIPTION
The PMI JFET-input series of devices offer clear advantages
over industry-generic devices and are superior in both cost
and performance to many dielectrically-isolated and hybrid
op amps. All devices offer offset voltages as low as 0.5mV with
TCVosguaranteed to 5pV/°C. A unique input bias cancellation
circuit reduces the Is by a factor of 10 over conventional
designs. In addition, PMI specifies laand loswith the devices
warmed up and operating at 25°C ambient,
These devices were designed to provide real precision
performance along with high speed. Although they can be
nulled, the design objective was to provide low offset-voltage
without nulling. Systems generally become more cost etfec-
tive as the number of trim circuits is decreased. PMI achieves
this performance by use of an improved Bipolar compatible
JFET process coupled with on-chip, zener-zap offset trimming.
The OP-15 provides an excellent combination of high speed
and low input offset voltage. In addition, the OP-15 offers the
speed of the 156A op amp with the power dissipation of a
155A. The combination of a low input offset voltage of 500W.
slew rate of 13V/ps, and settling time of 1200ns to 0.1% makes the
OP-15 an op amp of both precision and speed. The additional
features of low supply current coupled with an input bias current
of 9nA at 125°C ambient (not junction) temperature makes the
OP-ls ideal for a wide range of applications.
The 0P-16 features a slew rate of 25V/ps and a settling time of
900ns to 0.1% which represents a significant improvement in
speed over the 156. Also, the OP-lt, has all the DC features of
the OP-15.
The OP-17 has a slew rate of 60V/ps and is the best choice
for applications requiring high closed-loop gain with high
speed. See the OP-42 data sheet for unity gain applications
and the OP-215 data sheet for a dual configuration ot the
OP-15.
Vt mcr-
ii1'joce-i'i-C
NONINVERTING "AIC
INNT (3)
'NOTE:
R7, R8 ARE ELECTRONICALLV
ADJUSTED ON CHIP FOR
MINIMUM OFFSET VOLTAGE.
:m 022
a IN OUTPUT
L f Re
V- (0 cr- . v
W-IMP-IMP-IT
ORDERING INFORMATION t
PACKAGE
Taos'rt OPERATING
vosmx camp PLASTIC so TEMPERATURE
(HM 1040 W 8-P1N a-PN RANGE
OPCAr OP15AZ‘ - -
os OPIW - - - Ml.
OP17AJ‘ OP17AZ‘ - -
OP1SEJ OPISEZ - -
os OP16tid OPIBEZ - - COM
OF17EJ OP17EZ - ...
OPISBJIBBG OPt5BD883 - -
" 0131889883 0P1882/883 - - Ml
OP17BJ‘ 0P17BZ - -
OPISFJ OP15FZ OP15FP -
1.0 OPISFJ OP16FZ OP16FP - COM
- _ OP17FP
- 0131760883 - -
ao 091W - - - Ml
OPISGJ OP1SGZ OP1SGP OP1SGS
3.0 OP1BGJ OP1SGZ 0P1SGP OP1GGS XIM)
OP17GJ OP17GZ OP1TGP OP17GS
. Fat devices processed in total compliance to MIL-STD-tm, add [883 after part
number. Consult facbry lot 883 data sheet.
t Burn-in In amiable on commercial and industrial temperatuve range pans in
CerDIP, plum: DIP, and T0.can packages.
PIN CONNECTIONS
BAL 1 7 Vt
.m I 9 our
8-PIN CERDIP
MN , ' 5 BAC (2-Suffix)
v- ICASEI 8-PIN PLASTIC DIP
TO-tttt (P-Suffix)
Ig-sumo" 8-PIN so
(S-Suffix)
BURN-IN CIRCUIT
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage
All Devices Except C. G (Packaged) & GR Grades ..... s22V
C, G (Packaged) & GR Grades ...................................... :18V
Operating Temperature
A, B, & C Grades .-.......i......._-.. -55''C to +125°C
E & F Grades _..........-...........-...............-. 0''C to +70°C
G Grade W....................................................... -aity'C to +85''C
Maximum Junction Temperature ................................. +150°C
DICE Junction Temperature (T j) ................... -65''C to +150°C
Differential Input Voltage
All Devices Except C, G (Packaged) & GR Grades ...... :40V
C. G (Packaged) & GR Grades ..................................... :SOV
Input Voltage (Note 2)
All Devices Except C. G (Packaged) & GR Grades ..... AOV
C, G Packaged) & GR Grades ..................................... s16V
Input Voltage
OP-15A, OP-1SB. OP-15E, 0P-15F ............................. :20V
OP-15G B........................................................................ s16V
0P-16A, OP-16B, OP-16E, 0P-16F ............................. :20V
OP-ISC, OP-1GG .......................................................... s16V
0P-17A, OP-17B, OP-17E, 0P-17F ............................. t20V
OP-17C, 0P-17G .......................................................... =16V
Output Short-Circuit Duration .................................... Indefinite
Storage Temperature Range ........................ -65''C to +150°C
Lead Temperature Range (Soldering, 60 sec) ............ +300''C
PACKAGE TYPE BIA (Note 3) 91c UNITS
TO-gg (J) 150 18 mm
8-Pin Hermetic DIP (Z) 148 " ‘CM
8-Pin Plastic DIP (P) 103 43 “CM
8-Pin so (S) 153 43 cm
NOTES:
1. Absolute maximum ratings apply to both DICE and packaged parts, unless other-
wise noted.
Unless otherwise specified the absolute maximum negative input voltage is equal
to the negative power-supply voltage.
8 Is specified for worst case mounting conditions, io., e A Is sptrciittxi for device
in txxSartforTO, CerDIP and P-DIP packages; N Is specified for device soldered
to printed circuit board for SO pad(age.
(P-IMP-IMP-H
ELECTRICAL CHARACTERISTICS at Vs = _+15V, TA = 25''C, unless otherwise noted.
OP-15A/E OP-tSB/F OP-1SG
OP-16A/E OP-OB/F OP-NC/G
OP-17A/E OP-17B/F OP-17C/G
PARAMETER SYMBOL CONDITIONS Mitt TYP MAX MIN TYP MAX um TYP MAX UNITS
Input Offset Voltage Vos Rs = son - 0.2 0.5 - 0.4 1.0 - 0.5 3.0 mV
Ti = 25''C (Nate 1) OP-15 - a 10 - 6 20 - 12 50
In §t~Oflset Current I Device Operating - 5 22 - IO 40 - 20 100 A
p os T,=25°c (Note 1) OP-16/OP-17 - 3 IO - 6 20 - 12 50 p
Device Operating - 5 25 - 10 50 - 20 125
T,=25°c (Note 1) OP-15 - +15 :50 - :30 :100 - _+60 t200
In ut Bias Current I Device Operating - :18 +110 - +40 i200 - t80 $400 A
p B Tj=25°C(Note1) OP-16/OP-17 - +15 :50 - 130 :100 - 160 :200 p
Device Operating - +20 +130 - :40 i250 - -t80 ue500
Input Resistance Rm - 1012 - - 1O12 - - 1012 - n
Large-Signal RL 2 2kft
4 - 7 2 - -
Voltages Gain Avo vo = 110V 100 2 0 5 2 0 50 200 V/mV
Output Voltage V h = 10m :12 :13 - :12 A13 ", - :12 :13 - v
Swing o RL=2m +11 :12.7 - +11 :12.7 - :11 :12.7 -
0P-15 - 2.7 4.0 - 2.7 4.0 - 2.8 5.0
Supply Current tsr OP-N/OP-l - 4.6 7.0 - 4.6 7.0 _ - 4.8 8.0 mA
_ 0P-15 IO 13 - 7.5 11 - 5 9 -
Slew Rate SR Avcc - +1 (Note 3) 01:45 18 25 - 12 21 - 9 17 - los
AVCL = +5 (Note 3) 0P-17 45 60 - 35 50 - 25 40 -
. . 0P-15 4.0 6.0 - 3.5 5.7 - 3.0 5.4 -
"Je,:':''' GBW (Note 3) OP-16 6.0 6.0 - 5.5 7.6 - 5.0 7.2 - MHz
OP-l 20 30 - 15 28 - 11 26 -
OP-15 - 14 - - 13 - - 12 -
''t,',',te'l',' CLBW Avcc - +1 0P-16 - 19 - - 18 - - 17 - MHz
AVCL = +5 OP-17 - 11 - - IO - - 9 -
to 0.01% - 4.5 - - 4.5 - - 4.7 -
to 0.05% (Note 2) OP-15 - 1.5 - - 1.5 - - 1.5 -
to 0.10% - 1.2 - - 1.2 - - 1.3 -
to 0.01% - 3.8 - - 3.8 - - 4.0 -
Settling Time ts to 0.05% (Note 2) OP-16 - 1.2 - - 1.2 - - 1.3 - us
to 0.10% - 0.9 - - 0.9 - - 1.0 -
to 0.01% - 1.5 - - 1.5 - - 1.6 -
to 0.05% (Note 4) OP-17 - 0.7 - - 0.7 - - 0.8 -
to 0.10% - 0.6 - - 0.6 - - 0.7 -
Input Voltage Range IVR , 10.5 - - 110.5 - - 110.3 - - V
Common-Mode IG, = 110.5V 86 100 - 86 100 - - - -
Rejection Ratio C VCM = +_10.3V - - - - - - 82 96 - dB
Power Supply IIs = 110V to t181t - 10 51 - IO 51 - - -
Rejection Ratio s Vs = :1ov to :15v - - - - - - - IO 80 "W
Input Noise fo --. 100Hz - 20 - - 20 - - 20
Voltage Density Bn to = 1000Hz - 15 - - 15 - - 15 "W V Hz
Input Noise . to--- 100112 - 0.01 - - 0.01 - - 0.01 -
Current Density In fo-- 1000112 - 0.01 - - 0.01 - - 0.01 - PA/ V Hz
Input Capacltance Cm - 3 - - 3 - - 3 - pF
NOTES:
1. Input blas cunent Is specified tor two different conditions. The Ti = 25°C inverting input pin on the amplifier) to settle to within a specified percent 01
specification is with the junction at ambient temperature: the Device
Operating specification is with the device operating In a warmed-up
condition at 25°C ambient. The warmed-up bias current value is correlated
to thejunction temperature value via the curves of I BVS r, and la vs TA. PMI
has a bias current compensation circuit which gives improved bias current
over the standard JFET input op amps. Iaend losers measured at ch =0.
Settling time is defined here tore unitygain itwerttttcttttrtttthltm using 2110
resistors. It is the tlme required tor the error voltage (the voltage at the
Its final value from the time a10V step Input ls applied to the inverter. See
settling time test circuit.
Sample tested.
Settling time is defined here for a Av---5 connection wlth RF=2kn. It Is the
time required for the error voltage (the voltage at the inverting input pin on
the amplifier) to settle to within 0.01% of its final value from the time a 2V
step input Is applied to the inverter. See settling tlme test circult.
tp-IMP-IMP-IT
ELECTRICAL CHARACTERISTICS at Vs = i15V, -55°C 5 TAS 125°C, unless otherwise noted.
OP-15A OP-ISB
OP-16A OP-1SB OP-1GC
. OP-17A OP-17B OP-17C
PARAMETER SYMBOL CONDITIONS MIN TYP aaAlt MIN TYP MAX MIN TYP MAX UNITS
Input Offset Voltage Vos Rs = son - 0.4 0.9 - 0.7 2.0 - 0.9 4.5 mV
Average Input
Offset Voltage Drift (Note 2)
Wit {ourExternai T CVos - 2 5 - 3 10 - 4 15
Trim NPC;
With External "
Trim TCVOSn Hp = 100m - 2 - - 3 - - 4 -
Ti = 125°C - 0.6 4.0 - 0.8 6.0 - 1.0 9.0
TA .125 C . OP-15 - 0.8 7.0 - 1.2 11 - 1.5 17
Input Offset Dewce Operating
los nA
Current (Note 1) T, = 125°C - 0.6 4.0 - 0.8 6.0 - 1.0 9.0
= a - -
TA 125 C . OP 16/0P 17 - 1.0 8.5 - 1.3 14.5 - 1.7 22
Device Operating
Tj= 125°C - $1.2 $5.0 - $1.5 $7.5 - $18 :10
Ts .125 C _ oP-15 - +17 19.0 - $2.2 ur14 - +27 $19
Input Bias I Devxce Operating nA
Current tNote l) B Tj -- 125°C - +_1.2 t5.0 - tldi 17.5 - t1.8 t10
yt 125 c . OP-16/OP-17 - t2 o tll - ur2.5 :15 - t3.0 125
DeVIce Operating
Input Voltage Range IVR 110.4 - - $10.4 - - i 10.25 - - V
Common-Mode ch = i10.4V 85 97 - 85 97 - - - -
Rejectlon Ratio CMRR ch = :11].st - - - - - - 80 93 - dB
Power Supply Vs = i10V to i18V - 15 57 - 15 57 - - -
Rejection Ratio PSRR Vs = :1ov to :15v - - - - - - - 23 100 PV/V
Large-Signal Rc 2 2kn
120 - 30 110 - 2 1 -
Voltage Gain Avo Vo = t10V 35 5 oo V/mV
o"f"f Voltage V0 HLZ10kn 1'12 _+13 - t12 t13 - $12 $13 - V
NOTES:
1. Input bias current is specified tor two different conditions. The T}: 25''C
specification is with the junction at ambient temperature; the Device
Operating specification is with the device operating in a warmed-up
condition at 25''C ambient. The warmed-up bias current value is corre-
lated to the junction temperature value via the curves of ltsvsr T] and la vs
TA. PMI has a bias current compensation circuit which gives improved bias
current over the standard JFET input op amps. Its and los are measured
at vm, = 0.
2. Sample tested.
OP-I MP-IMP-H
ELECTRICAL CHARACTERISTICS at VS = 115V, 0°C s T, s 70°C for E and F, -A0 s T, s +85''C for G grade, unless otherwise
1. Input Bias current is specified for two different conditions. The Tj = 25'' C
specification is with the junction at ambient temperature; the Device
Operating specification is with the devlce operating in a warmed-up
condition at tttPC ambient. The warmed-up blas current value is corre-
lated to the junction temperature value via the curves of lav: r, and IBvs
TA. PMI has a bias current compensation circuit which gives improved bias
currem over the standard JFET input op amps. Iaand los are measured
at VCM = 0.
2. Sample tested.
noted.
OP-‘ISE OP-‘ISF OP-15G
OPA6E OP-IBF OP-1GG
0P-17E OP-17F 0P-17G
PARAMETER swam. CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Input oftsetVottagtt Vos Rs=500 - 0.3 0.75 - 0.55 1.5 - 0.7 3.8 mV
Avé'rSgelnput
Offset Voltage Drift (Note 2)
Without External
Trim TCVos - 2 5 - 3 10 - 4 30 V/°C
With External "
Trim TCVOS" Rp-100kn - 2 - - 3 - - 4 -
Ti=70"C - 0.04 0.30 - 0.06 0.45 - 0.08 0.65
y-yo c . OP-IS - 0.06 0.55 - 0.08 0.80 - 0.10 1.2
Input Offset I Device Operating A
Current (Note1) s Ti=rty't3 - 0.04 0.30 - 0.06 0.45 - 0.08 0.65
TA--TO c . OP-tti/OP-l - 0.07 0.70 - 0.10 1.1 - 0.15 1.7
Device Operating
Tj=70°C - 10.10 10.40 - 10.12 10.60 - 10.14 10.80
TA .70 c . op1s - 10.13 10.75 - 10.16 11.1 - 10.19 11.5
Input Bias l DeVIce operating A
CurrentiNtote1) B Tj=m°c - 10.10 10.40 - 10.12 10.60 - 10.14 10.60
TAtro C . OP-e/OP-lr - 10.15 10.00 - 10.20 11.4 - 10.25 12.0
Device Operating
Input Voltage Range IVR 110.4 - - 110.4 - - 110.25 - - V
Common-Mode Vcu = 110.4V 85 98 - 85 95 - - - -
Rejection Ratio CMRR VcM = 110.25V - - - - - - 80 94 - dB
Power Supply Vs = 110V to 113V - 13 57 - 13 57 - - -
Rejection Ratio PSRR Vs=-+10Vto-+15V - - - - - - - 20 100 tNN
Large-Signal Ru 2 2m
Voltage Gain Avo Vo-- 110v 65 200 50 100 - 35 160 - V/mV
001p01Votage vo Rszm 112 113 - 112 113 - 112 113 - v
NOTES:
OP-IMP-IMP-l
DICE CHARACTERISTICS (125°C TESTED DICE AVAILABLE)
DIE SIZE 0.068 X 0.056 Inch, 3808 sq. mils
(1.73 x 1.42mm, 2.46 sq. mm)
. BALANCE
. INVERTING INPUT
. NONlNVERTtNt3 INPUT
BALANCE
. OUTPUT
Naayupun-s
DIE SIZE 0.068 X 0.056 inch. 3808 sq. mils
(1.73 X 1.42mm, 2.46 sq. mm)
BALANCE
. INVERTING INPUT
. NONINVERTING INPUT
BALANCE
. OUTPUT
34019199)»,-
DIE SIZE 0.068 X 0.056 inch, 3808 sq. mlls
(1.73 X 1.42mm, 2.46 sq. mm)
. BALANCE
. INVERTING INPUT
. NONINVERTING INPUT
BALANCE
. OUTPUT
sappun-n
WAFER TEST LIMITS at V5: i15V, TA-- 25'' C for OP-15/16/17N, OP-15/16/17G and OP-15/16/17GR devices; TA-- 125° C for
0P-15/16/17NT and OP-15/16/17GT devices, unless otherwise noted.
OP-15NT OP-15N OP-1SGT OP-1SG OP-1SGR
OP-18NT OP-16N OP-ISGT OP-1GG OP-1SGR
OP-17NT OP-ITN OP-17GT OP-17G OP-17GR
PARAMETER SYMBOL CONDITIONS LIMIT LIMIT LIMIT LIMIT LIMIT UNITS
Input Offset Voltage Vos Rs = son 0.9 0.5 2.0 1.0 3.0 mV MAX
Large-Signal V0 = :10v
Voltage Gain Avo BL: gen 35 100 30 75 50 V/mV MIN
Input Voltage Range NR * 10.4 i 10.5 AI0.4 $10.5 t 10.3 V MIN
Common-Modo
Rejection Ratio CMRR IG, +_IVR 85 86 85 86 82 dB MIN
Power Supply Vs = 110V to A20V 57 51 57 51 -
Rejection Ratio PSRR vs--- , tOV to .t15V - - - - 80 tNN MAX
Output Voltage RL = 10ktt t12 + , 12 t 12
Swing Ito RL= 2m - - tll V WN
OP-15 - 4 - 4 5
Supply Current lsy 0P-18. OP-17 - 7 - 7 8 mA MAX
. OP-15 A9 - :14 - -
Input Bias Current l3 OP-18. OP-17 tll - t18 - - nA MAX
' 0P-15 7.0 - 11.0 - -
Input Offset Current los OP-16, OP-17 8.5 - 14.5 - - nA MAX
NOTES:
For2tPCchttmgtttristictt of 0P-1 5/16/17NT and 0P-15/16/17GT, see OP-15/16/17N
and OP-15/16/17G trharacteristitts, respectively.
Electrical tests are performed at water probe to the limits shown. Due to varlations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
ic,good price


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