OMAP3503DCUS ,Applications Processor 423-FCBGA 0 to 90Features12– 256-KB L2 Cache• OMAP3515 and OMAP3503 Devices:• 112KB of ROM– OMAP™ 3 Architecture• 64 ..
OMAP3515DCBC ,Applications Processor 515-POP-FCBGA 0 to 90Features12– 256-KB L2 Cache• OMAP3515 and OMAP3503 Devices:• 112KB of ROM– OMAP™ 3 Architecture• 64 ..
OMAP3525DZCBC ,OMAP3525-HiRel Applications Processor 515-POP-FCBGA -40 to 90– Embedded Trace Macrocell (ETM) Support – Parallel Digital Outputfor Non-Invasive Debug• Up to 24- ..
OMAP3530DCUS ,Applications Processor 423-FCBGA 0 to 90Features10 MPoly/sec– Byte-Addressable (8-, 16-, 32-, and 64-Bit• Universal Scalable Shader Engine: ..
OMAP3530DCUSA ,Applications Processor 423-FCBGA -40 to 105Associative) • Luma and Chroma Separate Video (S-Video)– 16-KB Data Cache (4-Way Set-Associative)– ..
OMAP3530ECUS ,Applications Processor 423-FCBGA 0 to 90 SPRS507H–FEBRUARY 2008–REVISED OCTOBER 2013• 65-nm CMOS Technologies .65-mm Ball Pitch (Top), .5-m ..
P2001 , LINE MATCHING TRANSFORMER
P2005AF-08SR , Low Frequency EMI Reduction IC
P2027A , General Purpose EMI Reduction IC
P2027A , General Purpose EMI Reduction IC
P2027A-08TR , General Purpose EMI Reduction IC
P2033 , SMT GATE DRIVE TRANSFORMERS 1500VDC Basic and Operational Insulation
OMAP3503DCUS
Applications Processor
OMAP3515, OMAP3503
www.ti.com SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013
OMAP3515 and OMAP3503 Applications Processors
Checkfor Samples: OMAP3515, OMAP3503 OMAP3515 and OMAP3503 Applications Processors
1.1 Features 256-KB L2 Cache• OMAP3515 and OMAP3503 Devices: 112KBof ROM– OMAP™3 Architecture 64KBof Shared SRAM– MPU Subsystem Endianess:• Upto 720-MHz ARM® Cortex™-A8 Core ARM Instructions– Little Endian• NEON™ SIMD Coprocessor ARM Data– Configurable– PowerVR® SGX™ Graphics Accelerator
(OMAP3515 Device Only) • External Memory Interfaces: Tile-Based Architecture Delivering upto – SDRAM Controller (SDRC) MPoly/sec • 16- and 32-Bit Memory Controller with Universal Scalable Shader Engine: Multi- 1GBof Total Address Space
threaded Engine Incorporating Pixel and • Interfacesto Low-Power Double Data
Vertex Shader Functionality Rate (LPDDR) SDRAM Industry Standard API Support: • SDRAM Memory Scheduler (SMS) andOpenGLES 1.1 and 2.0, OpenVG1.0 Rotation Engine Fine-Grained Task Switching, Load – General Purpose Memory Controller (GPMC)Balancing, and Power Management • 16-Bit-Wide Multiplexed Address and• Programmable High-Quality Image Anti- Data BusAliasing • Upto8 Chip-Select Pins with 128-MB– Fully Software-Compatible with ARM9™ Address Space per Chip-Select Pin Commercial and Extended Temperature • Glueless Interfaceto NOR Flash, NAND
Grades Flash (with ECC Hamming Code ARM Cortex-A8 Core Calculation), SRAM, and Pseudo-SRAM ARMv7 Architecture • Flexible Asynchronous Protocol Control
for Interfaceto Custom Logic (FPGA,• TrustZone® CPLD, ASICs, and so forth)• Thumb®-2 • Nonmultiplexed Address and Data Mode• MMU Enhancements (Limited 2-KB Address Space) Superscalar • System Direct Memory Access (sDMA) Controller (32 Logical Channels with Architecture Configurable Priority) SIMD • Camera Image Signal Processor (ISP) Imager Interface – BT.601 (8-Bit) (10-Bit) Digital YCbCr 4:2:2 Branch – Glueless Interface CommonTarget Address History Decoders Resize Engine Support • Resize Separate Vertical Control Display Subsystem Set- – Parallel Digital Output
