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OM4068HPHILIPSN/a15avaiLCD driver for low multiplex rates


OM4068H ,LCD driver for low multiplex ratesGENERAL DESCRIPTION1⁄3The OM4068 is a low-power CMOS LCD driver, designed• 32 segment driversto dri ..
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OM4068H
LCD driver for low multiplex rates

Philips Semiconductors Product specification
LCD driver for low multiplex rates OM4068
FEATURES
Single-chip LCD controller/driver Static/duplex/triplex drive modes with up to
32/64/96 LCD segments drive capability per device Selectable backplane drive configuration: static oror3 backplane multiplexing Selectable display bias configuration drive: static,1 ⁄2 or
1⁄3 32 segment drivers Serial data input (word length 32to96 bits) On-chip generation of intermediate LCD bias voltages2 MHz fast serial bus interface CMOS compatible Compatible with any 4-bit, 8-bit or 16-bit
microprocessors/microcontrollers May be cascaded for large LCD applications Logic supply voltage range (VDD− VSS) of 2.5to 5.5V Display supply voltage range (VLCD− VSS) of
3.5to 6.5V Low power consumption, suitable for battery operated
systems No external components needed by the oscillator Manufactured in silicon gate CMOS process.
APPLICATIONS
Telecom equipment Portable instruments Alarm systems Automotive equipment.
GENERAL DESCRIPTION

The OM4068 is a low-power CMOS LCD driver, designed
to drive Liquid Crystal Displays (LCDs) with low multiplex
rates. It generates the drive signals for any static or
multiplexed LCD containing up to three backplanes and up
to 32 segment lines and can be easily cascaded for larger
LCD applications. All necessary functions for the display
are provided in a single chip, including on-chip generation
of LCD bias voltages, resulting in a minimum of external
components and lower power consumption. A 3-line bus
structure enables serial data transfer with most
microprocessors/microcontrollers. All inputs are CMOS
compatible.
ORDERING INFORMATION
Notes
Gull Wing package. For details see Chapter “Bonding pad locations”.
Philips Semiconductors Product specification
LCD driver for low multiplex rates OM4068
BLOCK DIAGRAM
Philips Semiconductors Product specification
LCD driver for low multiplex rates OM4068
PINNING

See notes1to8.
Philips Semiconductors Product specification
LCD driver for low multiplex rates OM4068
Notes
SEG1to SEG32 (LCD segment driver outputs) output the multi-level signals for the LCD segments. BP0, BP1 and BP2 (LCD backplane driver outputs) output the multi-level signals for the LCD backplanes. VLCD (LCD power supply): power supply for the LCD. SDIN (serial data line): input for the bus data line. SCL (serial clock line): input for the bus clock line. SDOUT (serial data output): output of the shift register to allow serial cascading of the OM4068 with other devices. SCE (serial clock enable): input for enable/disable acquisition on the data input line. If disabled, data on the serial
bus are not accepted by the device. M0 and M1 (display mode select inputs): inputs to select the LCD drive configurations; static, duplex or triplex.
Philips Semiconductors Product specification
LCD driver for low multiplex rates OM4068
Philips Semiconductors Product specification
LCD driver for low multiplex rates OM4068
Philips Semiconductors Product specification
LCD driver for low multiplex rates OM4068
FUNCTIONAL DESCRIPTION

The OM4068 is a low-power LCD driver designed to
interface with any microprocessor/microcontroller and a
wide variety of LCDs. It can drive any static or multiplexed
LCD containing up to three backplanes andto96 segments.
The display configurations possible with the OM4068
depend on the number of active backplane outputs
required; a selection of display configurations is given in
Table1.
A typical system (MUX1: 3) is shown in Fig.4.
Table 1
Selection of display configurations
The host microprocessor/microcontroller maintains the
3-line bus communication channel with OM4068.
The internal oscillator requires no external components.
The appropriate intermediate biasing voltage for the
multiplexed LCD waveforms are generated on-chip.
The only other connections required to complete the
system are to the power supplies (VSS, VDD and VLCD) and
suitable capacitors to decouple the VLCD and VDD pins to
VSS.
Philips Semiconductors Product specification
LCD driver for low multiplex rates OM4068
Power-on reset

The on-chip power-on reset block initializes the chip after
power-on or power failures. The OM4068 resets to a
starting condition as follows: All backplane and segment outputs are set to VSS
(display off) All shift registers and latches are set in 3-state SDOUT (allowing serial cascading) is set to logic 0 (with
SCE LOW) Power-down mode.
Data transfers on the serial bus should be avoided for
0.5 ms following power-on to allow completion of the reset
action.
Power-down

After power-on the chip is in power-down mode as long as
the serial clock is not active. During power-down all static
currents are switched off (no internal oscillator, no timing
and no bias level generation) and all LCD-outputs are
3-stated. The power-on reset functions remain enabled.
The power-down mode is disabled at the first rising edge
of the serial clock SCLK.
LCD bias voltage generator

The intermediate bias voltages for the LCD display are
generated on-chip. This removes the need for an external
resistive bias chain and significantly reduces the system
power consumption. The full-scale LCD voltage VOP
equals VLCD− VSS. The optimum value of VOP depends on
the LCD threshold voltage (Vth) and the number of bias
levels.
Fractional LCD biasing voltages are obtained from an
internal voltage divider of three series resistors (1 ⁄3bias)
connected between VLCD and VSS. The centre resistor can
be switched out of the circuit to provide a1 ⁄2bias voltage
level for the 1:2 multiplex configuration.
The bias levels depend on the multiplex rate and are
selected automatically when the display configuration is
selected using M1 and M0.
LCD voltage selector

The LCD voltage selector (control logic) coordinates the
multiplexing of the LCD in accordance with the selected
drive or display configuration. The operation of the voltage
selector is controlled by the input pins M0 and M1
(see Table2).
Table 2
Drive mode selection
For multiplex rates of 1: 2 three bias levels are used
including VLCD and VSS. Four bias level are used for the:3 multiplex rate. The various biasing configurations
together with the biasing characteristics as functions of
VOP =VLCD− VSS and the resulting discrimination ratios
(D), are given in Table3.
A practical value for VOP is determinated by equating
Voff(rms) with a defined LCD threshold voltage (Vth),
typically when the LCD exhibits approximately 10%
contrast. In static mode a suitable choice is VOP >3Vth.
Philips Semiconductors Product specification
LCD driver for low multiplex rates OM4068
Table 3
LCD drive modes: summary of characteristics
LCD drive mode waveforms

The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive
waveforms for this mode are shown in Fig.5.
Philips Semiconductors Product specification
LCD driver for low multiplex rates OM4068
1:2MULTIPLEX DRIVE MODE
When two backplanes are provided in the LCD, the 1: 2 multiplex mode applies, as shown in Fig.6.
1:3MULTIPLEX DRIVE MODE
When three backplanes are provided in the LCD, the 1:3 multiplex mode applies, as shown in Fig.7.
Philips Semiconductors Product specification
LCD driver for low multiplex rates OM4068
Philips Semiconductors Product specification
LCD driver for low multiplex rates OM4068
Oscillator

The internal logic and the multi-level LCD drive signals of
the OM4068 are generated by the built-in RC oscillator. external components are required.
In order to minimize radio frequency interference, the
oscillator operates with symmetrical and slew-rate limited
capacitor charge/discharge.
The oscillator runs continuously once the power down
state after power-on has been left.
Interface to microprocessor unit: serial interface

A three-line bus structure enables serial unidirectional
data transfer with microprocessors/microcontrollers.
The three lines are a serial data input line (SDIN), a serial
clock line (SCLK) and a data line enable (SCE). All inputs
are CMOS compatible. These lines must always be in a
defined state VSSor VDD.Floating inputs could damage the
chip.
On the bus, one data bit is transferred during each clock
pulse. The data on the SDIN line remains stable during the
whole clock period. Data changes arrive with the falling
edge of the serial clock SCLK (see Fig.8).
Shift register

Data present on the SDIN pin is shifted into a shift register
with the rising edge of the serial clock SCLK in a
synchronous manner. The shift register serves to transfer
display information from the serial bus to the (display) latch
while previous data is displayed.
The shift register is organized as three 32-bit shift
registers. Depending on the display driving mode selected
(see Table 3), one, two or three registers are used and
cascaded resulting in a shift register length of 32, 64 or bits. Figure 9 shows the shift register organization with
the display data bits after a shift operation is completed.
The shift sequence begins with data bit D32 and finishes
with data bit D1. The correspondence between the data bit
numbers and the LCD display segments is shown in
Table4.
Data from the last stage of the register is supplied to the
SDOUT pin to allow serial cascading of the OM4068 with
other peripheral devices. Depending on the display driving
mode selected, SDOUT corresponds to bit 32, 64 or 96 of
the register (see Fig.10). Data on the SDOUT pin is shifted
out with the falling edge of the SCLK clock. SDOUT is
therefore delayed by1 ⁄2SCLK cycle before it is applied to
the SDIN pin of the next IC in the serial chain (see Fig.8).
The clock enable SCE signal must be HIGH in order to
enable the shift operation. SDOUT output is latched with
the last data after SCE returned to HIGH (shift operation
terminated).
SDOUT is in 3-state mode when SCE is LOW.
Philips Semiconductors Product specification
LCD driver for low multiplex rates OM4068
Display latch

The 96-bit display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch and the LCD segment outputs. An LCD segment is
activated when the corresponding data bit in the display
latch is HIGH.
Display latches are in HOLD mode (SCE HIGH) during the
shift operation to maintain the display data constant.
Data are latched into the display latch with the internal
frame clock. Thus there is a delay of up to one half frame
before new data are latched after signal SCE returns to
zero.
Timing

The timing of the OM4068 organizes the internal data flow
of the device. This includes the transfer of display data
from the shift register to the display segments outputs.
The timing also generates the LCD frame frequency which
is derived from the clock frequency generated in the
internal clock generator: fr(LCD)osc
2400-------------=
Shift register configuration
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