NDS352AP_NL ,P-Channel Logic Level Enhancement Mode Field Effect TransistorElectrical Characteristics (T = 25°C unless otherwise noted)ASymbol Parameter Conditions Min Typ Ma ..
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NDS355AN ,N-Channel Logic Level Enhancement Mode Field Effect TransistorFeaturesTMSuperSOT -3 N-Channel logic level enhancement mode1.7A, 30 V, R = 0.125 Ω @ V = 4.5 V ..
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NDS352AP_NL
P-Channel Logic Level Enhancement Mode Field Effect Transistor
February 1997 NDS352AP P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These P -Channel logic level enhancement mode power field -0.9 A, -30 V. R = 0.5 W @ V = -4.5 V DS(ON) GS effect transistors are produced using Fairchild's proprietary, R = 0.3 W @ V = -10 V. DS(ON) GS high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. Industry standard outline SOT-23 surface mount package TM These devices are particularly suited for low voltage applications using proprietary SuperSOT -3 design for superior thermal such as notebook computer power management, portable and electrical capabilities. electronics, and other battery powered circuits where fast High density cell design for extremely low R . high-side switching, and low in-line power loss are needed in a DS(ON) very small outline surface mount package. Exceptional on-resistance and maximum DC current capability. ________________________________________________________________________________ D G S Absolute Maximum Ratings T = 25°C unless otherwise noted A Symbol Parameter NDS352AP Units V Drain-Source Voltage -30 V DSS V Gate-Source Voltage - Continuous ±20 V GSS I ±0.9 A Maximum Drain Current - Continuous (Note 1a) D - Pulsed ±10 P Maximum Power Dissipation (Note 1a) 0.5 W D (Note 1b) 0.46 T ,T Operating and Storage Temperature Range -55 to 150 °C J STG THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W R qJA Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W R JC q © 1997 NDS352AP Rev.D
