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NDS336FAIRCHILN/a12000avaiP-Channel Logic Level Enhancement Mode Field Effect Transistor


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NDS336
P-Channel Logic Level Enhancement Mode Field Effect Transistor
June 1997 NDS336P P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features TM SuperSOT -3 P-Channel logic level enhancement mode power -1.2 A, -20 V,  R = 0.27 W @ V = -2.7 V DS(ON) GS field effect transistors are produced using Fairchild's R = 0.2 W @ V = -4.5 V. DS(ON) GS proprietary, high cell density, DMOS technology. This very high Very low level gate drive requirements allowing direct density process is especially tailored to minimize on-state operation in 3V circuits. V < 1.0V. resistance. These devices are particularly suited for low voltage GS(th) applications such as notebook computer power management, Proprietary package design using copper lead frame for portable electronics, and other battery powered circuits where superior thermal and electrical capabilities. fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package. High density cell design for extremely low R . DS(ON) Exceptional on-resistance and maximum DC current capability. Compact industry standard SOT-23 surface Mount package. ________________________________________________________________________________ D G S Absolute Maximum Ratings T = 25°C unless otherwise noted A Symbol Parameter NDS336P Units Drain-Source Voltage -20 V V DSS Gate-Source Voltage - Continuous ±8 V V GSS I Maximum Drain Current - Continuous (Note 1a) -1.2 A D - Pulsed -10 P Maximum Power Dissipation (Note 1a) 0.5 W D (Note 1b) 0.46 T ,T Operating and Storage Temperature Range -55 to 150 °C J STG THERMAL CHARACTERISTICS R Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W qJA R Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W qJC © 1997 NDS336P Rev. E
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