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NDC632P_NLFAIRCHILN/a1000avaiP-Channel Logic Level Enhancement Mode Field Transistor


NDC632P_NL ,P-Channel Logic Level Enhancement Mode Field TransistorELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)ASymbol Parameter Conditions Min Typ Ma ..
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NDC632P_NL
P-Channel Logic Level Enhancement Mode Field Transistor
June1996 NDC632P P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These P-Channel logic level enhancement mode -2.7A, -20V.  R = 0.14W @ V = -4.5V DS(ON) GS power field effect transistors are produced using R = 0.2W @ V = -2.7V. DS(ON) GS Fairchild's proprietary, high cell density, DMOS TM technology. This very high density process is Proprietary SuperSOT -6 package design using copper especially tailored to minimize on-state resistance. lead frame for superior thermal and electrical capabilities. These devices are particularly suited for low voltage High density cell design for extremely low R . DS(ON) applications such as notebook computer power management and other battery powered circuits Exceptional on-resistance and maximum DC current where fast high-side switching, and low in-line power capability. loss are needed in a very small outline surface mount package. ___________________________________________________________________________________________ 4 3 5 2 6 1 TM SuperSOT -6 Absolute Maximum Ratings T = 25°C unless otherwise noted A Symbol Parameter NDC632P Units V Drain-Source Voltage -20 V DSS V Gate-Source Voltage - Continuous -8 V GSS I Drain Current - Continuous -2.7 A D - Pulsed -10 Maximum Power Dissipation (Note 1a) 1.6 W P D (Note 1b) 1 (Note 1c) 0.8 T ,T Operating and Storage Temperature Range -55 to 150 °C J STG THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W R JA q Thermal Resistance, Junction-to-Case (Note 1) 30 °C/W R JC q © 1997 NDC632P Rev. B1
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