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NDB5060LFAIRCHILN/a36500avaiN-Channel Logic Level Enhancement Mode Field Effect Transistor
NDB5060LNSN/a467avaiN-Channel Logic Level Enhancement Mode Field Effect Transistor


NDB5060L ,N-Channel Logic Level Enhancement Mode Field Effect TransistorElectrical Characteristics (T = 25°C unless otherwise noted)CSymbol Parameter Conditions Min Typ Ma ..
NDB5060L ,N-Channel Logic Level Enhancement Mode Field Effect TransistorFeaturesThese logic level N-Channel enhancement mode power26 A, 60 V. R = 0.05 Ω @ V = 5 V ..
NDB510A ,N-Channel Enhancement Mode Field Effect TransistorElectrical Characteristics (T = 25°C unless otherwise noted)CSymbol Parameter Conditions Type Min T ..
NDB6020P ,P-Channel Logic Level Enhancement Mode Field Effect TransistorGeneral Description Enhancement Mode Field Effect Transistor / NDB6020P NDP6020P September (T = 2 ..
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NDB6030L ,NDP6030L / NDB6030L N-Channel Logic Level Enhancement Mode Field Effect Transistorapplications such as DC/DC convertersand high efficiency switching circuits where fastswitching, lo ..
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NDB5060L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
October 1996 NDP5060L / NDB5060L N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These logic level N-Channel enhancement mode power 26 A, 60 V. R = 0.05 W @ V = 5 V DS(ON) GS field effect transistors are produced using Fairchild's R = 0.035 W @ V = 10 V. DS(ON) GS proprietary, high cell density, DMOS technology. This Critical DC electrical parameters specified at elevated very high density process has been especially tailored temperature. to minimize on-state resistance, provide superior switching performance, and withstand high energy Rugged internal source-drain diode can eliminate the need for an external Zener diode transient suppressor. pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage 175°C maximum junction temperature rating. applications such as automotive, DC/DC converters, PWM motor controls, and other battery powered High density cell design for extremely low R . DS(ON) circuits where fast switching, low in-line power loss, 2 TO-220 and TO-263 (D PAK) package for both through hole and resistance to transients are needed. and surface mount applications. ________________________________________________________________________________ D G S Absolute Maximum Ratings T = 25°C unless otherwise noted C Symbol Parameter NDP5060L NDB5060L Units V Drain-Source Voltage 60 V DSS 60 V V Drain-Gate Voltage (R < 1 MW) DGR GS V Gate-Source Voltage - Continuous ±16 V GSS ±25 - Nonrepetitive (t < 50 µs) P I Drain Current - Continuous 26 A D - Pulsed 78 P Total Power Dissipation @ T = 25°C 68 W D C Derate above 25°C 0.45 W/°C T ,T Operating and Storage Temperature Range -65 to 175 °C J STG © 1997 NDP5060L Rev.A
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