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NC7WZ32K8XFAIN/a3000avaiTinyLogic UHS Dual 2-Input OR Gate
NC7WZ32L8XFAIRCHILDN/a5000avaiTinyLogic UHS Dual 2-Input OR Gate


NC7WZ32L8X ,TinyLogic UHS Dual 2-Input OR GateFeaturesThe NC7WZ32 is a dual 2-Input OR Gate from Fairchild’s

NC7WZ32K8X-NC7WZ32L8X
TinyLogic UHS Dual 2-Input OR Gate
NC7WZ32 TinyLogic UHS Dual 2-Input OR Gate April 2000 Revised January 2005 NC7WZ32 TinyLogic UHS Dual 2-Input OR Gate General Description Features The NC7WZ32 is a dual 2-Input OR Gate from Fairchild’sSpace saving US8 surface mount package Ultra High Speed Series of TinyLogic. The device is fabri-MicroPak Pb-Free leadless package cated with advanced CMOS technology to achieve ultra Ultra high speed t 2.4 ns Typ into 50 pF at 5V V PD CC high speed with high output drive while maintaining low High output drive ±24 mA at 3V V static power dissipation over a very broad V operating CC CC range. The device is specified to operate over the 1.65V toBroad V operating range 1.65V to 5.5V CC 5.5V V range. The inputs and output are high impedance CC Matches the performance of LCX when operated at when V is 0V. Inputs tolerate voltages up to 7V indepen- CC 3.3V V CC dent of V operating voltage. CC Power down high impedance inputs/output Overvoltage tolerant inputs facilitate 5V to 3V translation Patented noise/EMI reduction circuitry implemented Ordering Code: Product Order Package Code Package Description Supplied As Number Number Top Mark NC7WZ32K8X MAB08A WZ32 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel NC7WZ32L8X MAC08A N5 Pb-Free 8-Lead MicroPak, 1.6 mm Wide 5k Units on Tape and Reel Pb-Free package per JEDEC J-STD-020B. Logic Symbol Connection Diagrams IEEE/IEC Pin Descriptions (Top View) Pin One Orientation Diagram Pin Names Description A , B Inputs n n Y Output n AAA represents Product Code Top Mark - see ordering code Function Table Note: Orientation of Top Mark determines Pin One location. Read the top product code mark left to right, Pin One is the lower left pin (see diagram). Y = A + B Input Output Pad Assignments for MicroPak AB Y LLL LH H HL H HHH H = HIGH Logic Level L = LOW Logic Level (Top Thru View) TinyLogic is a registered trademark of . MIcroPak is a trademark of . © 2005 DS500270
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