IC Phoenix
 
Home ›  NN4 > NC7WZ02K8X-NC7WZ02L8X,TinyLogic UHS Dual 2-Input NOR Gate
NC7WZ02K8X-NC7WZ02L8X Fast Delivery,Good Price
Part Number:
If you need More Quantity or Better Price,Welcom Any inquiry.
We available via phone +865332716050 Email
Partno Mfg Dc Qty AvailableDescript
NC7WZ02K8XFAIRCHILD ?N/a1701avaiTinyLogic UHS Dual 2-Input NOR Gate
NC7WZ02L8XFAIRCHILDN/a3000avaiTinyLogic UHS Dual 2-Input NOR Gate


NC7WZ02L8X ,TinyLogic UHS Dual 2-Input NOR GateFeaturesThe NC7WZ02 is a dual 2-Input NOR Gate from Fairchild’s

NC7WZ02K8X-NC7WZ02L8X
TinyLogic UHS Dual 2-Input NOR Gate
NC7WZ02 TinyLogic UHS Dual 2-Input NOR Gate April 2000 Revised January 2005 NC7WZ02 TinyLogic UHS Dual 2-Input NOR Gate General Description Features The NC7WZ02 is a dual 2-Input NOR Gate from Fairchild’sSpace saving US8 surface mount package Ultra High Speed Series of TinyLogic. The device is fabri-MicroPak Pb-Free leadless package cated with advanced CMOS technology to achieve ultra Ultra High Speed: t 2.4 ns typ into 50 pF at 5V V PD CC high speed with high output drive while maintaining low High Output Drive: ±24 mA at 3V V static power dissipation over a very broad V operating CC CC range. The device is specified to operate over the 1.65V toBroad V Operating Range: 1.65V to 5.5V CC 5.5V V range. The inputs and output are high impedance CC Matches the performance of LCX when operated at when V is 0V. Inputs tolerate voltages up to 7V indepen- CC 3.3V V CC dent of V operating voltage. CC Power down high impedance inputs/output Overvoltage tolerant inputs facilitate 5V to 3V translation Patented noise/EMI reduction circuitry implemented Ordering Code: Product Order Package Code Package Description Supplied As Number Number Top Mark NC7WZ02K8X MAB08A WZ02 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel NC7WZ02L8X MAC08A P5 Pb-Free 8-Lead MicroPak, 1.6 mm Wide 5k Units on Tape and Reel Pb-Free package per JEDEC J-STD-020B. Logic Symbol Connection Diagrams IEEE/IEC (Top View) Pin Descriptions Pin One Orientation Diagram Pin Names Description A , B Inputs n n Y Output n AAA represents Product Code Top Mark - see ordering code Function Table Note: Orientation of Top Mark determines Pin One location. Read the top product code mark left to right, Pin One is the lower left pin (see diagram). Y = A + B Inputs Output Pad Assignments for MicroPak AB Y LL H LH L HL L HH L H = HIGH Logic Level L = LOW Logic Level (Top Thru View) TinyLogic is a registered trademark of . MicroPak is a trademark of . © 2005 DS500269
ic,good price


TEL:86-533-2716050      FAX:86-533-2716790
   

©2020 IC PHOENIX CO.,LIMITED