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NB7N017MMNGQFN52N/a24avai3.3V SiGe 8-Bit Dual Modulus Programmable Divider/Prescaler with CML Outputs
NB7N017MMNR2GONN/a50avai3.3V SiGe 8-Bit Dual Modulus Programmable Divider/Prescaler with CML Outputs


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NB7N017MMNG-NB7N017MMNR2G
3.3V SiGe 8-Bit Dual Modulus Programmable Divider/Prescaler with CML Outputs
NB7N017M
3.3V SiGe 8−Bit Dual
Modulus Programmable
Divider/Prescaler with CML
Outputs
The NB7N017M is a high speed 8–bit dual modulus
programmable divider/prescaler with 16 mA CML outputs capableof switching at input frequencies greater than 3.5 GHz. The CML
output structure contains internal 50 � source termination resistor toVCC. The device generates 400 mV output amplitude with 50 �
receiver resistor to VCC. This I/O structure enables easyimplementation of the NB7N017M in 50 � systems.
The differential inputs contain 50 � termination resistors to VTpads and all differential inputs accept RSECL, ECL, LVDS,
LVCMOS, LVTTL, and CML. Internally, the NB7N017M uses a > 3.5 GHz 8–bit programmabledown counter. A select pin, SEL, is used to select between two
words, Pa[0:7] and Pb[0:7], that are stored in REGa and REGbrespectively. Two parallel load pins, PLa and PLb, are used to load
the level triggered programming registers, REGa and REGb,respectively. A differential clock enable, CE, pin is available.
The NB7N017M offers a differential output, TC. Terminal countoutput, TC, goes high for one clock cycle when the counter has
reached the all zeros state. To reduce output phase noise, TC isretimed with the rising edge triggered latches. Maximum Input Clock Frequency > 3.5 GHz Typical Differential CLK Clock Input Differential CE Clock Enable Input Differential SEL Word Select Input 50 � Internal Input and Output Termination Resistors Differential TC Terminal Count Output All Outputs 16 mA CML with 50 � Internal Source Termination
to VCC All Single–Ended Control Pins CMOS and PECL/NECL
Compatible Counter Programmed Using One of Two Single−Ended Words,
Pa[0:7] and Pb[0:7], Stored in REGa and REGb REGa and REGb Implemented with Level Triggered Latch Compatible with Existing 3.3 V LVEP, EP, and SG Devices Ability to Program the Divider without Disturbing Current Settings Positive CML Output Operating Range: VCC = 3.0 V to 3.465 V
with VEE = 0 V Negative CML Output Operating Range: VCC = 0 V
with VEE = –3.0 V to –3.465 V VBB Reference Voltage Output CML Output Level: 400 mV Peak−Peak Output with 50 � Receiver
Resistor to VCC Pb−Free Packages are Available*
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