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N74F373D
Octal D flip-flop (3-State)
Product data
Supersedes data of 1994 Dec 05
2002 Nov 20
Philips Semiconductors Product data
74F373/74F374Latch/flip-flop74F373 Octal transparent latch (3-State)
74F374 Octal D-type flip-flop (3-State)
FEATURES 8-bit transparent latch — 74F373 8-bit positive edge triggered register — 74F374 3-State outputs glitch free during power-up and power-down Common 3-State output register Independent register and 3-State buffer operation SSOP Type II Package
DESCRIPTIONThe 74F373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is HIGH. The latch remains transparent to the data
input while E is HIGH, and stores the data that is present one set-up
time before the HIGH-to-LOW enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-LOW output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is LOW, latched or
transparent data appears at the output.
When OE is HIGH, the outputs are in high impedance “off” state,
which means they will neither drive nor load the bus.
The 74F374 is an 8-bit edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one
set-up time before the LOW-to-HIGH clock transition is transferred
to the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-LOW output enable (OE) controls all eight 3-State buffers
independent of the register operation. When OE is LOW, the data in
the register appears at the outputs. When OE is HIGH, the outputs
are in high impedance “off” state, which means they will neither drive
nor load the bus.
ORDERING INFORMATION
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
NOTE: One (1.0) FAST unit load is defined as: 20 μA in the HIGH state and 0.6 mA in the LOW state.
Philips Semiconductors Product data
74F373/74F374Latch/flip-flop
PIN CONFIGURATION – 74F373
LOGIC SYMBOL – 74F373
IEC/IEEE SYMBOL – 74F373
PIN CONFIGURATION – 74F374
IEC/IEE SYMBOL – 74F374
IEC/IEEE SYMBOL – 74F374
Philips Semiconductors Product data
74F373/74F374Latch/flip-flop
LOGIC DIAGRAM FOR 74F373
LOGIC DIAGRAM FOR 74F374
FUNCTION TABLE FOR 74F373
NOTES:= High-voltage level= HIGH state must be present one set-up time before the HIGH-to-LOW enable transition= Low-voltage level = LOW state must be present one set-up time before the HIGH-to-LOW enable transition
NC= No change= Don’t care= High impedance “off” state= HIGH-to-LOW enable transition
Philips Semiconductors Product data
74F373/74F374Latch/flip-flop
FUNCTION TABLE FOR 74F374
NOTES:= High-voltage level= HIGH state must be present one set-up time before the LOW-to-HIGH clock transition= Low-voltage level = LOW state must be present one set-up time before the LOW-to-HIGH clock transition
NC= No change= Don’t care= High impedance “off” state= LOW-to-HIGH clock transition= Not LOW-to-HIGH clock transition
ABSOLUTE MAXIMUM RATINGSOperation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.
RECOMMENDED OPERATING CONDITIONS
Philips Semiconductors Product data
74F373/74F374Latch/flip-flop
DC ELECTRICAL CHARACTERISTICS(Over recommended operating free-air temperature range unless otherwise noted.)
NOTES: For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. All typical values are at VCC = 5 V, Tamb = 25 °C. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
AC ELECTRICAL CHARACTERISTICS
Philips Semiconductors Product data
74F373/74F374Latch/flip-flop
AC SET-UP REQUIREMENTS
AC WAVEFORMSFor all waveforms, VM = 1.5 V.
The shaded areas indicate when the input is permitted to change for
predictable output performance.
Waveform 1. Propagation delay for clock input to output,
clock pulse widths, and maximum clock frequency
Waveform 2. Propagation delay for enable to output
and enable pulse width
Waveform 3. Propagation delay for data to output
Waveform 4. Data set-up time and hold times
