MTC20455MB7K ,Quad ADSL DMT TransceiverMTC20455QUAD ADSL DMT TRANSCEIVER■ Quad DMT modem ATM framer■ Supports ANSI T1.413 issue 2, ITU G.9 ..
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N83C198 , COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER
MTC20455MB7K
Quad ADSL DMT Transceiver
1/23
MTC20455February 2004 Quad DMT modem ATM framer Supports ANSI T1.413 issue 2, ITU G.992.1,
and G.992.2 standards Low power consumption (1W for four lines) Standard Utopia level 2 ATM interface 160 PQFP Package 160 LFBGA Package
DESCRIPTIONThe MTC20455 is the DMT modem and ATM
Framer of the MTK20450 Quad Rate adaptive
ADSL DynaMiTe chipset. When used in conjunc-
tion with the MTC20454 or MTC20154 analog
front-end, the product supports ANSI T1.413 re-
lease 2, ITU G.992.1 and G.992.2 (G.Lite) ADSL
specifications through software configuration. It
provides a cell based UTOPIA Level 2 ATM data
interface.
The MTC20455 performs the DMT modulation,
demodulation, Reed-Solomon encoding, bit inter-
leaving and trellis coding for four ADSL modems.
The ATM section provides framing functions for
the generic and ATM Transmission Convergence
(TC) layers. The generic TC consists of data
scrambling and Reed-Solomon error corrections,
with and without interleaving.
The MTC20455 is controlled and configured by the
MTC20136 Transceiver Controller. All program-
mable coefficients and parameters are loaded by
the Controller. The MTC20136 also controls the
initialisation procedure and performs the monitor-
ing and adaptive functions during operation.
QUAD ADSL DMT TRANSCEIVER
Figure 1. Block Diagram
MTC20455
Figure 2. PQF160 package pin out
Table 1. I/O types
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MTC20455
Table 2. I/O driver function
Table 3. PQFP 160 pin list
MTC20455
Table 3. PQFP 160 pin list (continued)
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MTC20455
Table 3. PQFP 160 pin list (continued)
MTC20455
Table 3. PQFP 160 pin list (continued)
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MTC20455
Figure 3. LFBGA160 package pin out (Sachem4 top view)
Table 4. LFBGA 160 pin list
MTC20455
Table 4. LFBGA 160 pin list (continued)
9/23
MTC20455
Table 4. LFBGA 160 pin list (continued)
MTC20455
ELECTRICAL SPECIFICATIONS GENERICThe values presented in the following table apply for all inputs and/or outputs unless specified otherwise.
Specifically they are not influenced by the choice between CMOS or TTL levels.
Table 5. I/O Buffers generic DC Characteristics
Table 6. IO buffers dynamic characteristic
Table 4. LFBGA 160 pin list (continued)
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MTC20455
Input/Output CMOS Generic CharacteristicsThe values presented in the following table apply for all CMOS inputs and/ or outputs unless specified oth-
erwise.
Table 7. TTL IO buffers generic characteristics* The reference current is dependent on the exact buffer chosen and is part of the buffer name. The available values are 4 and 8mA.
Input/Output TTL Generic CharacteristicsThe values presented in the following table apply for all TTL inputs and/or outputs unless specified other-
wise.
Table 8. TTL IO buffers generic characteristics* The reference current is dependent on the exact buffer chosen and is part of the buffer name. The available values are 2,4, and 8mA.
Operating Conditions
Table 9. Operating Conditions
MTC20455
Functional DescriptionFig.4 shows the global block diagram of the MTC20455. The functions can be grouped into the following: DMT modems Quad or single AFE interface Utopia interface Controller interface Miscellaneous
DMT Modem DescriptionThe following section essentially describes the sequence of actions for the receive direction, correspond-
ing functions for the transmit direction are readily derived.
DSP Front-EndThe DSP Front-End contains 4 parts in the receive direction: the Input Selector, the Analog Front-End In-
terface, the Decimator and the Time Equaliser. The input selector is used internally to enable test loop-
backs inside the chip. The Analog Front-End Interface transfers 1 6-bits word, multiplexed on 4 input/
output signals. As a result, 4 clock cycles are needed to transfer 1 word. The Decimator receives the 16-
bits samples at 8.8 MHz (as sent by the Analog Front-End chip) and reduces this rate to 2.2 MHz. The
Time Equaliser (TEQ) module is an FIR filter with programmable coefficients. Its main purpose is to reduce
the effect of Inter-Symbol Interference (ISI) by shortening the channel impulse response. Both the Deci-
mator and TEQ can be bypassed. In the transmit direction, the DSP Front-End includes: sidelobe filtering,
clipping, delay equalisation and interpolation. The sidelobe filtering and delay equalisation are implement-
ed by IIR filters, reducing the effect of echo in FDM systems. Clipping is a statistical process limiting the
amplitude of the output signal, optimising the dynamic range of the AFE. The interpolator receives data at
2.2 MHz and generates samples at a rate of 8.8 MHz.
Figure 4. DSP Front-End
DMT ModemThis computational module is a programmable DSP unit. Its instruction set enables functions like FFT, IF-
FT, Scaling, Rotor and Frequency Equali-sation (FEQ). This block implements the core of the DMT algo-
rithm as specified in ANSI T1.413. In the RX path, the 512-point FFT transforms the time-domain DMT
symbol into a frequency domain representation which can be further decoded by the subsequent de-map-
ping stages. After the first stage time / domain equalisation and FFT block – an essentially ICI (InterCarrier
Interference) – free carrier information stream has been obtained.
This stream is still affected by carrier-specific channel distortion resulting in an attenuation of the signal
