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MTC20136MBI1
ADSL Transceiver Controller
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MTC20136February 2004 Dedicated controller for use with ADSL
transceiver chips MTC20134, MTC20135 and
MTC20455 Performs ADSL control functions : Initialization procedure Line monitoring during operation Rate adaptive modes Supports the modem control interface protocol
(CTRLE) Embedded high speed ARM microcore Glueless connection to MTC20135 and
MTC20455 Parallel or serial modem control interface
(CTRLE) for glueless connection to
management entities Embedded UART Supports code download External Bus Interface for 8 and 16-bit FEPROM
and 16-bit SDRAM 144 pins PQFP
DESCRIPTIONThe MTC20136 is a dedicated controller chip, spe-
cifically designed to control operations of the ST-
Microelectronics DynaMiTe chipset. The
MTC20136 offers direct glueless interfaces to the
MTC20135 and MTC20455 DMT/ATM transciever
and implements a complete control interface for
parameters and commands exchange between
transceiver and system management. All real time
ADSL-related functions (including EOC process-
ing) are completely handled by the MTC20136.
ADSL TRANSCEIVER CONTROLLER
Figure 1. Block Diagram
MTC20136
Functional DescriptionFigure 1 is showing the global block diagram of the MTC20136. The functions can be grouped into the
following: Microcontroller External Bus Interface Control Interface (CTRLE) Peripherals Miscellaneous
MicrocontrollerThe microcontroller block includes an ARM-based microcore and its associated internal memory. 16
Kbytes on internal RAM and 128 x 32-bit words of ROM are foreseen. The ROM essentially contains the
boot sequence needed for code download at startup. The use of the ROM by the microcore is defined by
the state of the TROM pin during reset.
External Bus InterfaceThe External Bus Interface extends the internal microcontroller bus for connection of external devices. In
particular, the bus is used to connect to the MTC20135 or MTC20455 modem chip and to external SDRAM
(and optional FEEPROM).
The CTRLE functional block implements the ADSL modem command and data buffer and the interface
logic supporting the physical interfaces of the CTRLE.
PeripheralsThe peripherals block includes two UARTS for RS232 interfacing to external systems and two general =
purpose parallel I/O lines.
MiscellaneousThis includes the clock circuitry, reset circuitry, test functions and configuration control signals.
CTRLE Interfaces
External Bus InterfaceThe external bus interface (EBI) provides a glueless interface to 8 and 16-bit asynchronous Flash EE-
PROM, 16 bit SDRAM devices and to slave devices with an i960-like 16 bit bus interface with multiplexed
address and data (as available on DynaMiTe chips).
The EBI provides two chip selects (E_nCS[1:0]) to be used for memory access (SRAM-like), one dedicat-
ed SDRAM chip select ((E_nCS_S) and four chip selects (E_nCS[7:4]) to be used for access to ADSL
slave devices. The chip selects all correspond to a fixed 1Mbyte memory region in the microcontroller
memory map, except for SDRAM access.
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MTC20136
PIN LAYOUT
Functional Pin SummaryThe signals hereunder are grouped per functional interface.
Figure 2. Pin functional description and type per interface
MTC20136 The table below describes the pins, organized per interface. Some of these pins have a multiple function-
ality. In this case both functionalities are mentioned.
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MTC20136 = Input, CMOS levels
I-PU = Input with pull-up resistance, CMOS levels
I-PD = Input with pull-down resistance, CMOS levels
I-TTL= Input TTL levels = Push-pull output = Push-pull output with high-impedance state = Open Drain output = input / Tri-state Push-pull output
PQFP144 Pin Configuration (Default Value between ( ))
MTC20136
PQFP144 Pin Configuration (continued)(Default Value between ( ))
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MTC20136
PQFP144 Pin Configuration (continued)(Default Value between ( ))
MTC20136
PQFP144 Pin Configuration (continued)(Default Value between ( ))
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MTC20136
LFBGA160 Pin Configuration
MTC20136
LFBGA160 Pin Configuration (continued)
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MTC20136
LFBGA160 Pin Configuration (continued)
MTC20136
External pinsThese physical pins are used for different logical functions, depending on the external device which is ac-
cessed. The correspondance between physical and logical functions is given in Table 1
E_D[15:0] 16 bit data, multiplexed address/data
E_A[19:0] 20 bit address (including commands for SDRAM)
nCS[7:4] external chip select
E_CLK external clock
ALE Address Latch Enable
nRDYRCV Ready/Recover driven by selected device together with external pull-up
nOE output enable
nWE0 Write enable for LSB byte lane E_D[7:0]
nWE1 Write enable for MSB byte lane E_D[15:8]
Table 1.
LFBGA160 Pin Configuration (continued)
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MTC20136
Memory map modesThree modes are defined :
a) Normal mode:
The internal RAM is mapped in the lower part of memory. This is the normal operating mode, it allows
maximum speed access to exception vectors.
b) Normal boot mode:
If the TROM external pin is high at reset, the MTC20136 boots from an external FEPROM.
c) Internal boot mode:
If the TROM external pin is low at reset, the MTC20136 boots from its internal ROM. This mode can be
used to perform code download from a host.
Boot modes are used at RESET time.
Boot_M0 andBoot_M1 on pin 26 and 27 conrol the port to be used for downloading the code into the
SDRAM after Bootup. This when TROM is low.
MTC20135, MTC20455 accessThe MTC20136 directly connects to the MTC20135 without glue logic. Following features are provided for
MTC20135 access : 16 bit multiplexed address/data bus giving 64Kbyte address space per MTC20135. synchronous ready-controlled operation - control signals : nCS[4:7], E_CLK, ALE, W/nR, nRDYRCV Little endian byte ordering on 16 bit bus - nRDYRCV timeout mechanism
The timing diagram of the access to the MTC20135 or MTC20455 is shown in figure 3:
Table 1. (continued)
