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MTB30P06ONN/a500avaiTMOS POWER FET 30 AMPERES 60 VOLTS
MTB30P06VMOT N/a11avaiPower MOSFET 30 Amps, 60 Volts


MTB30P06 ,TMOS POWER FET 30 AMPERES 60 VOLTSELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)JCharacteristic Symbol Min Typ Max Unit ..
MTB30P06V ,Power MOSFET 30 Amps, 60 Voltselectrical characteristics apply to operation atallows code to be written before hardware design is ..
MTB30P06V ,Power MOSFET 30 Amps, 60 VoltsMAXIMUM RATINGS (T = 25°C unless otherwise noted)CRating Symbol Value UnitDrain–to–Source Voltage V ..
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MTB50N06EL ,TMOS POWER FET LOGIC LEVEL 50 AMPERES 60 VOLTSMAXIMUM RATINGS (T = 25°C unless otherwise noted)CRating Symbol Value UnitDrain–Source Voltage V 60 ..
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MTB30P06-MTB30P06V
TMOS POWER FET 30 AMPERES 60 VOLTS
 --  -- P–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resis-
tance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETS
Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature Static Parameters are the Same for both TMOS V and TMOS E–FET Surface Mount Package Available in 16 mm 13–inch/2500 Unit T ape & Reel,
Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions—
The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves— representing boundaries on device characteristics— are given to facilitate “worst case” design.
E–FET, Designer’s and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
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