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MPC993FA
Dynamic switch PLL clock driver
SEMICONDUCTOR TECHNICAL DATA- -
The MPC993 is a PLL clock driver designed specifically for redundant
clock tree designs. The device receives two differential LVPECL clock
signals from which it generates 5 new differential LVPECL clock outputs.
Two of the output pairs regenerate the input signals frequency and phase
while the other three pairs generate 2x, phase aligned clock outputs.
External PLL feedback is used to also provide zero delay buffer
performance. Fully Integrated PLL Intelligent Dynamic Clock Switch LVPECL Clock Outputs LVCMOS Control/Statis I/O 3.3V Operation 32–Lead TQFP Packaging ±50ps Cycle–Cycle Jitter
The MPC993 continuously monitors the two input signals to identify faulty reference clocks. Upon identification of a faulty
input clock (input clock stuck HIGH or LOW for at least 3 feedback clock edges), an input bad flag will be set and the device will
automatically switch from the bad reference clock input to the good one. During this dynamic switch of the input references, the
MPC993 outputs will slew, with minimal period disturbances to the new phase.
Figure 1. Block DiagramCLK0
CLK1
Ext_FBSel_Clk
PLL_En
Qb0
Qb1
Qb2
Qa0
Qa1
Man_OV
erride
Alarm_Reset Inp0badInp1badClk_Selected
