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MPC9443FIRECRONN/a101avaiMPC9443 2.5V and 3.3V LVCMOS Clock Fanout Buffer


MPC9443 ,MPC9443 2.5V and 3.3V LVCMOS Clock Fanout BufferLogic Diagram36 35 34 33 32 31 30 29 28 27 26 25VCCA 37 24 VCCDQA4 QD038 23QA3 39 22 QD1QA2 40 21 Q ..
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MPC9443
MPC9443 2.5V and 3.3V LVCMOS Clock Fanout Buffer
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9443/D
Rev 2, 05/2002
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The MPC9443 is a 2.5V and 3.3V compatible 1:16 clock distribution
buffer designed for low-voltage high-performance telecom, networking
and computing applications. The device supports 3.3V, 2.5V and dual
supply voltage (mixed-voltage) applications. The MPC9443 offers 16
low-skew outputs which are divided into 4 individually configurable banks.
Each output bank can be individually supplied by 2.5V or 3.3V,
individually set to run at 1X or 1/2X of the input clock frequency or be
disabled (logic low output state). Two selectable LVPECL compatible
inputs support differential clock distribution systems. In addition, one
selectable LVCMOS input is provided for LVCMOS clock distribution
systems. The MPC9443 is specified for the extended temperature range
of –40 to +85°C.
Features
• Configurable 16 outputs LVCMOS clock distribution buffer Compatible to single, dual and mixed 3.3V/2.5V voltage supply Output clock frequency up to 350 MHz Designed for high-performance telecom, networking and computer
applications Supports applications requiring clock redundancy Max. output skew of 250 ps (125 ps within one bank) Selectable output configurations per output bank Individually per-bank high–impedance tristate Output disable (stop in logic low state) control 48 ld LQFP package Ambient operating temperature range of –40 to 85°C
Functional Description

The MPC9443 is a full static design supporting clock frequencies up to 350 MHz. The signals are generated and retimed
on-chip to ensure minimal skew between the four output banks.
Two independent LVPECL compatible clock inputs are available. This feature supports redundant differential clock sources. In
addition, the MPC9443 supports single-ended LVCMOS clock distribution systems. Each of the four output banks can be
individually supplied by 2.5V or 3.3V, supporting mixed voltage applications. The FSELx pins choose between division of the
input reference frequency by one or two. The frequency divider can be set individually for each output bank. The MPC9443 output
banks are in high–impedance state by deasserting the OEN pins. Asserting OEN will the enable output banks. Please see the
Output High–Impedance Control table on page 4 for details. The outputs can be synchronously stopped (logic low state). The
outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For series terminated
transmission lines, each of the MPC9443 outputs can drive one or two traces giving the devices an effective fanout of 1:32 at VCC
= 3.3V. The device is packaged in a 7x7 mm2 48-lead LQFP package.
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