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MM74HCT05SJFAIRCHILN/a62avaiHex Inverter (Open Drain)


MM74HCT05SJ ,Hex Inverter (Open Drain)Featureswide power supply range. The device is also input and out- Open drain for wire-NOR function ..
MM74HCT05SJX ,Hex Inverter (Open Drain)Electrical Characteristics(V = 5V ± 10%,unless otherwise specified)CC T = 25°CT = −40 to 85°CA A Sy ..
MM74HCT08M ,Quad 2-Input AND GateFeaturesThe MM74HCT08 is a logic function fabricated by using

MM74HCT05SJ
Hex Inverter (Open Drain)
MM74HCT05 Hex Inverter (Open Drain) February 1984 Revised February 1999 MM74HCT05 Hex Inverter (Open Drain) These parts are also plug-in replacements for LS-TTL General Description devices and can be used to reduce power consumption in The MM74HCT05 is a logic function fabricated by using existing designs. advanced silicon-gate CMOS technology, which provides the inherent benefits of CMOS—low quiescent power and Features wide power supply range. The device is also input and out- � Open drain for wire-NOR function put characteristic and pinout compatible with standard DM74LS logic families. The MM74HCT05 open drain Hex � LS-TTL pinout and threshold compatible Inverter requires the addition of an external resistor to per- � Fanout of 10 LS-TTL loads form a wire-NOR function. � Typical propagation delays: All inputs are protected from static discharge damage by t (with 1 kΩ resistor) 10 ns PLH internal diodes to V and ground. CC t (with 1 kΩ resistor) 8 ns PHL MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. Ordering Code: Order Number Package Number Package Description MM74HCT05M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow MM74HCT05SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HCT05MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HCT05N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Typical Application Top View © 1999 DS005358.prf
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