MM74HC240WM ,Inverting Octal 3-STATE BufferFeaturesThe MM74HC240 3-STATE buffer utilizes advanced sili-
MM74HC240MTC-MM74HC240N-MM74HC240SJ-MM74HC240SJX-MM74HC240WM
Inverting Octal 3-STATE Buffer
MM74HC240 Inverting Octal 3-STATE Buffer September 1983 Revised August 2000 MM74HC240 Inverting Octal 3-STATE Buffer General Description Features The MM74HC240 3-STATE buffer utilizes advanced sili-Typical propagation delay: 12 ns con-gate CMOS technology. It possesses high drive cur-3-STATE outputs for connection to system buses rent outputs which enable high speed operation even when Wide power supply range: 2–6V driving large bus capacitances. These circuits achieve Low quiescent supply current: 80 μA (74 Series) speeds comparable to low power Schottky devices, while retaining the advantage of CMOS circuitry, i.e., high noiseOutput current: 6 mA immunity and low power consumption. It has a fanout of 15 LS-TTL equivalent inputs. The MM74HC240 is an inverting buffer and has two active LOW enables (1G and 2G). Each enable independently controls 4 buffers. All inputs are protected from damage due to static dis- charge by diodes to V and ground. CC Ordering Code: Order Number Package Number Package Description MM74HC240WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide MM74HC240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC240N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table 1G 1A 1Y 2G 2A 2Y LL H L L H LH L L H L HL Z H L Z HH Z H H Z H = HIGH Level L = LOW Level Z = HIGH Impedance Top View © 2000 DS005020
