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MM74HC174M-MM74HC-174M-MM74HC174MTC-MM74HC174MX-MM74HC174N Fast Delivery,Good Price
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MM74HC174MNSCN/a3avaiHex D-Type Flip-Flop with Clear
MM74HC-174M |MM74HC174MONN/a700avaiHex D-Type Flip-Flop with Clear
MM74HC174MTCFAIRCHILN/a239avaiHex D-Type Flip-Flop with Clear
MM74HC174MXFSCN/a4816avaiHex D-Type Flip-Flop with Clear
MM74HC174NFSCN/a14avaiHex D-Type Flip-Flop with Clear


MM74HC174MX ,Hex D-Type Flip-Flop with ClearFeaturesmon clock and common clear. Data on the D input havingthe specified setup and hold times is ..
MM74HC174N ,Hex D-Type Flip-Flop with ClearMM74HC174 Hex D-Type Flip-Flops with ClearSeptember 1983Revised February 1999MM74HC174Hex D-Type Fl ..
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MM74HC175MTC ,Quad D-Type Flip-Flop with ClearGeneral Descriptioncompatible with the standard 74LS logic family. All inputsThe MM74HC175 high spe ..
MM74HC175MX ,Quad D-Type Flip-Flop with ClearGeneral Descriptioncompatible with the standard 74LS logic family. All inputsThe MM74HC175 high spe ..
MM74HC175MX ,Quad D-Type Flip-Flop with ClearMM74HC175 Quad D-Type Flip-Flop With ClearSeptember 1983Revised February 1999MM74HC175Quad D-Type F ..
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MM74HC174M-MM74HC-174M-MM74HC174MTC-MM74HC174MX-MM74HC174N
Hex D-Type Flip-Flop with Clear
MM74HC174 Hex D-Type Flip-Flops with Clear September 1983 Revised February 1999 MM74HC174 Hex D-Type Flip-Flops with Clear Each output can drive 10 low power Schottky TTL equiva- General Description lent loads. The MM74HC174 is functionally as well as pin The MM74HC174 edge triggered flip-flops utilize advanced compatible to the 74LS174. All inputs are protected from silicon-gate CMOS technology to implement D-type flip- damage due to static discharge by diodes to V and CC flops. They possess high noise immunity, low power, and ground. speeds comparable to low power Schottky TTL circuits. This device contains 6 master-slave flip-flops with a com- Features mon clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q � Typical propagation delay: 16 ns output on the LOW-to-HIGH transition of the CLOCK input. � Wide operating voltage range: 2–6V The CLEAR input when LOW, sets all outputs to a low � Low input current: 1 μA maximum state. � Low quiescent current: 80 μA (74HC Series) � Output drive: 10 LSTTL loads Ordering Code: Order Number Package Number Package Description MM74HC174M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74HC174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC174MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC174N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table (Each Flip-Flop) Pin Assignments for DIP, SOIC, SOP and TSSOP Inputs Outputs Clear Clock D Q LX X L H ↑ HH H ↑ LL HL X Q 0 H = HIGH Level (steady state) L = LOW Level (steady state) X = Don't Care ↑ = Transition from LOW-to-HIGH level Q = The level of Q before the indicated steady state input conditions were 0 established. © 1999 DS005318.prf
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