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MM74HC139SJX
Dual 2-to-4 Line Decoder
MM74HC139 Dual 2-To-4 Line Decoder September 1983 Revised February 1999 MM74HC139 Dual 2-To-4 Line Decoder equivalent to the 74LS139. All inputs are protected from General Description damage due to static discharge by diodes to V and CC The MM74HC139 decoder utilizes advanced silicon-gate ground. CMOS technology, and is well suited to memory address decoding or data routing applications. It possesses the Features high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds compara- � Typical propagation delays — ble to low power Schottky TTL logic. Select to outputs (4 delays): 18 ns The MM74HC139 contain two independent one-of-four Select to output (5 delays): 28 ns decoders each with a single active low enable input (G1, or Enable to output: 20 ns G2). Data on the select inputs (A1, and B1 or A2, and B2) � Low power: 40 μW quiescent supply power cause one of the four normally high outputs to go LOW. � Fanout of 10 LS-TTL devices The decoder’s outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally as well as pin � Input current maximum 1 μA, typical 10 pA Ordering Code: Order Number Package Number Package Description MM74HC139M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74HC139SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC139MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP) JEDEC MO-153, 4.4mm Wide MM74HC139N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP, SOIC, SOP and TSSOP Inputs Outputs Enable Select G B A Y0Y1Y2Y3 H X X HHH H LL L L H H H LL H H L H H LH L H H L H L H H HHH L H = HIGH Level L = LOW Level X = Don't Care © 1999 DS005311.prf
